CM_DSI1ECTL_SRC_CLR 0xfffffff0
CM_SLIMCTL_BUSYD_LSB 8
PM_GRAFX_V3DRSTN_MSB 6
UART_LCR_SP_LSB 5
HD_CSC_CTL_USERGB2YCC_CLR 0xfffffffd
CM_SMICTL_ENAB_MSB 4
CAM0_CAMIBEA0_RESET 0000000000
HDMI_RAM_PACKET_7_8_RESET 0000000000
PCM_CS_A_RXSEX_BITS 23:23
PWM_CTL_MSEN1_SET 0x00000080
DMA3_TXFR_LEN_YLENGTH_SET 0x3fff0000
SD_STALL_CYCLES_CLR 0xfffffc00
SD_DMRCRC0_LOW_MSB 15
SD_DQRCRC1_RISE_BITS 31:16
A2W_PLLA_ANA_SSCSR_RESET 0000000000
SD_CS_PUSKIP_SET 0x00000010
DMA6_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
AVE_IN_CTRL_ENABLE_LSB 31
OTP_PRIVATE_KEY_SIZE_IN_ROWS 4
DSI0_CTRL_CTRL1_SET 0x00000002
HD_MAI_CTL_DLATE_MSB 15
A2W_XOSC_CTRL_SMPSOK_CLR 0xffff7fff
DMA_ENABLE_EN11_MSB 11
VEC_CONFIG0_WIDTH 32
USB_DOEPCTL0_USB_ACT_EP_BITS 15:15
SCALER_DISPECTRL_POSTED_CTRL_CLR 0xffc0ffff
CM_PLLB_ANARST_MSB 8
DMA1_TXFR_LEN 0x7e007114:RO
HD_MAI_THR_DREQHIGH_MSB 13
FPGA_CTRL0_SPI0_SEL_B_BITS 12:12
CM_AVEODIV_DIV_SET 0x0000f000
TB_JTB_CONFIG_ENABLE_SET 0x00000800
OTP_BOOT_EXTRAS_ROW_SIZE_IN_ROWS 1
SCALER_DISPSTAT 0x7e400004:RW
MPHI_C0INDS_VALID_SET 0x40000000
CM_DPIDIV_DIV_CLR 0xffff000f
PM_CAM0_WIDTH 21
A2W_PLLD_PER_CHENB_CLR 0xfffffeff
CM_VECCTL_FRAC_BITS 9:9
CMI_CAMTEST_SRC_CLR 0xfffffff0
A2W_HDMI_CTL_RCAL_SELAVG_BITS 1:0
CM_INTEN_WRFAIL_CLR 0xfff7ffff
TIMER_CTRL_32BIT (1 << 1)
EMMC_DMA_STATUS_ERR_AT_MSB 1
CM_UARTCTL_BUSYD_CLR 0xfffffeff
TXP_CTRL_ABORT_SET 0x00004000
SCALER_DISPCTRL_DSP1_IRQ_CTRL_BITS 10:9
CM_CCP2CTL_ENAB_LSB 4
JP_ICST 0x7e005004:RW
HDMI_READ_POINTERS_DRFT_UNDERFLOW_CLR 0xfffeffff
SLIM_DCC7_PROT_WIDTH 32
SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_SET 0x00000003
CAM1_CAMDAT0_RESET 0x00000002
V3D_DBQRUN_WIDTH 32
USB_GRSTCTL_FRM_CNTR_RST_LSB 2
A2W_SMPS_C_CLKR 0x7e1029c0:RW
CM_GP0CTL_BUSY_MSB 7
AVE_IN_CTRL_MASK 0x87ffffff
V3D_IDENT0 0x7ec00000 +0x0000:RW
V3D_IDENT1 0x7ec00000 +0x0004:RW
V3D_IDENT2 0x7ec00000 +0x0008:RW
V3D_IDENT3 0x7ec00000 +0x000c:RW
I2C_SPI_SLV_DEBUG1_DATA_SET 0x03ffffff
L2END 0x7ee01008:RW
DMA5_DEBUG_READ_ERROR_BITS 2:2
USB_DOEPDMAB9_WIDTH 32
SMI_DSR0_RHOLD_BITS 21:16
A2W_PLLB_DIG0R_MASK 0x00ffffff
SPI_CS_CPOL_CLR 0xfffffff7
MPHI_C0INDS_MASK 0xdfffffff
CM_INTEN_A2WDONE_BITS 20:20
EMMC_CONTROL1_SRST_CMD_SET 0x02000000
CM_EVENT_LOSSH_LSB 9
EMMC_INTERRUPT_INT_C_MSB 11
USB_GHWCFG2_NUM_EPS_CLR 0xffffffff11
L1_IC1_PRIORITY_IC1_APRIORITY2_CLR 0xfffff0ff
EMMC_INTERRUPT_DEND_ERR_SET 0x00400000
DMA0_DEBUG_LITE_BITS 28:28
USB_GHWCFG2_MODE_LSB 0
TXP_CTRL_POWERDOWN_RESET 0x0
PM_PROC_ARMRSTN_CLR 0xffffffbf
EMMC_IRPT_EN_BOOTACK_MSB 13
USB_DCFG_EP_MIS_CNT_LSB 18
DMA0_CS_ACTIVE_MSB 0
AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_LSB 31
DMA14_DEBUG_DMA_STATE_SET 0x01ff0000
EMMC_HWCAP1_SDR104_LSB 1
CM_UARTCTL_ENAB_MSB 4
UMSR 0x7e201000 + 0x18:RW
I2C_SPI_SLV_ICR_RXIC_BITS 0:0
DSI0_CTRL_CTRL0_BITS 0:0
PM_AVS_INTEN_ALERT_ARM_P_CLR 0xffffffef
PM_CCP2TX_CTRLEN_CLR 0xfffffffe
I2C_SPI_SLV_IFLS_TXIFLSEL_BITS 2:0
A2W_PLLD_CTRL_MASK 0x000373ff
USB_DIEPCTL0_ENA_CLR 0x7fffffff
CAM1_CAMIVSTA 0x7e80112c:RW
HDMI_DETECTED_VERTA1_MANUAL_VSP1_BITS 24:20
PM_IMAGE_ISFUNC_BITS 5:5
SD_DMRCRC0_HIGH_CLR 0x0000ffff
GP_FEN2_WIDTH 6
PCM_TXC_A_MASK 0xffffffff
ST_CHI 0x7e003008:RO
CM_HSMCTL_SRC_LSB 0
GP_FSEL3_FSEL32_MSB 8
DMA1_DEBUG_DMA_ID_MSB 15
DMA15_CS_PAUSED_LSB 4
PM_DFT_STOPALLCLOCKS_CLR 0xfffffffd
SMI_DSW0_WPACE_SET 0x00007f00
GP_FSEL5_FSEL53_CLR 0xfffff1ff
DMA7_CS_PANIC_PRIORITY_LSB 20
A2W_PLLC_CORE2_BYPEN_LSB 9
DSI0_PHYC_dlane_hsen_0_sync_LSB 0
AVE_OUT_CTRL_INVERT_HSYNC_CLR 0xffffbfff
DMA2_TI_DEST_INC_CLR 0xffffffef
SD_PT1_MASK 0x0fffffff
SCALER_DISPSTAT_DSP0_STATUS_LSB 8
SMI_CS_WRITE_SET 0x00000020
USB_DTXFSTS3_MASK 0xffffffff
HDMI_RAM_PACKET_8_6_WIDTH 32
AVE_IN_STATUS_MAX_HIT_SET 0x00010000
USB_GOTGCTL_A_SES_VLD_SET 0x00040000
PM_CAM0_LDOCTRL_MSB 20
DMA8_DEBUG_LITE_LSB 28
PCM_CS_A_RXERR_LSB 16
TRANSPOSER_PROGRESS 0x7e004010:RO
DMA4_DEBUG_DMA_STATE_LSB 16
AUX_MU_CNTL_AUCTSINV 0x80
PM_GNRIC_ISFUNC_LSB 5
DMA9_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
CM_BURSTCNT_CNT_SET 0x00ffffff
V3D_PCTRS12_MASK 0x0000001f
HDMI_MAI_CONFIG 0x7e902094:RW
SH_HSTS_CMD_TIME_OUT_CLR 0xffffffbf
PIXELVALVE_VSYNC_0 PIXELVALVE0_VSYNC
PIXELVALVE_VSYNC_1 PIXELVALVE1_VSYNC
SMI_FD_FCNT_LSB 0
SMI_CS_SETERR_LSB 13
DMA6_TXFR_LEN_YLENGTH_BITS 29:16
CM_SMICTL_KILL_CLR 0xffffffdf
RNG_INT_MASK_WIDTH 32
CCP2TX_TC_CLKM_LSB 2
DMA2_TI_SRC_INC_SET 0x00000100
SLIM_DCC0_PA1_WIDTH 24
VEC_CGMSAE_BOT_CONTROL_WIDTH 32
AVE_IN_CALC_LINE_STEP 0x7e910030:RW
TXP_CTRL_EI_SET 0x00000004
CM_PLLD_LOADPER_CLR 0xffffffbf
AUX_MU_STAT_RTR 0x00000040
CM_VPUCTL_BUSY_BITS 7:7
ACISCA 0x1C004800 + 0x08:RW
CAM1_CAMANA_WIDTH 32
ASB_V3D_S_CTRL_WCOUNT_MSB 23
ACISCD 0x1C004800 + 0x0C:RW
SLIM_DCC9_PA0_WIDTH 24
DMA2_CONBLK_AD_WIDTH 32
MPHI_C0INDFS_CFIFOLVL_LSB 16
I2C_SPI_SLV_DMACR_RXDMAE_SET 0x00000001
A2W_PLLD_ANA2_WIDTH 24
PM_CCP2TX_MASK 0x0007ffff
DSI1_CTRL 0x7e700000:RW
EMMC_HWCAP1_DRV18_TYPEC_BITS 5:5
ACISCS 0x1C004800 + 0x00:RW
DMA3_TI_BURST_LENGTH_MSB 15
CM_SMICTL_SRC_BITS 3:0
UNICAM_ICC(x) MACRO
USB_GINTMSK_GIN_N_NAK_EFF_LSB 6
GP_FSEL4_FSEL42_SET 0x000001c0
SCALER_DISPECTRL_CR_BUSY_BITS 31:11
A2W_PLLD_CTRL_NDIV_SET 0x000003ff
PIXELVALVE_VSYNC_x(x) MACRO
CM_OSCFREQI_INT_SET 0x000000ff
CCP2TX_TTC_LSC_BITS 7:4
UNICAM_ICS(x) MACRO
SD_MR_WIDTH 32
OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS 4
PM_GNRIC_CFG_BITS 22:16
APERF0_BW0_CTRL_RESET_LSB 31
EMMC_INTERRUPT_RETUNE_CLR 0xffffefff
PCM_RX_DMA ( 3*(1<<16))
USB_GUSBCFG_TOUT_CAL_BITS 2:0
HD_MAI_CTL_RST_MAI_RESET 0x0
SYSAC_TRANS_PRIORITY_P_PRIORITY_CLR 0xffffff0f
SD_DQLCRC7_FALL_RESET 0x0
AVE_IN_BLOCK_ID_WIDTH 32
MPHI_C0INDCF_HANDLE_BITS 27:20
CM_DSI0ECTL_SRC_BITS 3:0
DMA8_CS_PAUSED_MSB 4
EMMC_STATUS_DAT_INHIBIT_BITS 1:1
SMI_CS_TXE_RESET 0x1
MS_SEMA_13_MASK_SET 0x00000001
GP_SET1 0x7e200020:RW
CM_SLIMDIV_DIV_MSB 23
MS_MBOX_7_MBOX_CLR 0x00000000
APERF1_BW2_CTRL 0x7ee080c0:RW
SMI_DSR0_MODE68_SET 0x00800000
DMA0_TI_DEST_IGNORE_MSB 7
SD_PT2_T_INIT5_BITS 15:0
CM_ARMCTL_RESET 0x00000004
USB_GHWCFG3_TRANS_COUNT_WIDTH_RESET 0x0
AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_SET 0x80000000
DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
USB_HCTSIZ0_PID_BITS 30:29
ARM_0_BELL0 (0x7E00B000 +0x800)+0x40:RW
ARM_0_BELL1 (0x7E00B000 +0x800)+0x44:RW
ARM_0_BELL2 (0x7E00B000 +0x800)+0x48:RW
ARM_0_BELL3 (0x7E00B000 +0x800)+0x4C:RW
PM_RSTC_FRCFG_CLR 0xfffcffff
A2W_SMPS_L_SPA_ANA_CLR 0xfffffc00
PM_PXLDO_CTRL_MSB 15
AVE_IN_CURRENT_ADDRESS_WIDTH 32
PM_PADS3_HYST_MSB 3
FPGA_CTRL0_CAM_CTL1_BITS 1:1
DMA5_CS_INT_BITS 2:2
CM_EVENT_LOSSA_CLR 0xffffffdf
PM_PADS5_SLEW_CLR 0xffffffef
UNICAM_IDS(x) MACRO
SD_SD_T_RC_RESET 0x14
CM_DFTDIV_RESET 0000000000
MS_SEMA_23_MASK_BITS 0:0
EMMC_FORCE_IRPT_CCRC_ERR_CLR 0xfffdffff
CM_HSMCTL_WIDTH 10
USB_DIEPINT10_WIDTH 32
DMA2_STRIDE_MASK 0xffffffff
SD_CARCRC_RISE_CLR 0x0000ffff
SMI_CS_PXLDAT_MSB 14
IC1_FORCE1_CLR_MASK 0xffffffff
A2W_SMPS_LDO1R_WIDTH 24
GP_PUD_MASK 0x00000003
DMA11_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
APERF0_BW1_CTRL_LATHALT_LSB 28
MPHI_C1INDCF_ORUN_RESET 0x0
GP_FSEL6_FSEL63_BITS 11:9
MPHI_C0INDCF_LENERR_MSB 30
SMI_DSR0_RWIDTH_MSB 31
PCM_GRAY_FLUSH_LSB 2
A2W_PLLD_ANA_SCTL_MASK 0x0000001f
DMA7_CS_INT_MSB 2
HD_HDM_CTL_WIDTH 10
SMI_DSR2_FSETUP_SET 0x00400000
SMICS_EDREQ 15
DMA12_CS_RESET_CLR 0x7fffffff
CCP2TX_TPC_TPP_MSB 7
USB_HCCHAR0_DEV_ADDR_CLR 0xe03fffff
SD_RWC_MARGIN_LSB 22
GP_FSEL5_FSEL55_BITS 17:15
AUX_SPI_CNTL1_HOLDIN 0x00000001
TB_JTB_CONFIG_SBITS_LSB 0
CCP2TX_TTC_LEC_SET 0x00000f00
EMMC_CMDTM_CMD_INDEX_LSB 24
DMA10_NEXTCONBK_ADDR_MSB 31
A2W_SMPS_C_CTL_CTRLEN_BITS 0:0
GP_PUD_WIDTH 2
DSI1_TA_TO_CNT 0x7e700044:RW
DMA4_TI_SRC_WIDTH_BITS 9:9
GP_FSEL4_FSEL47_BITS 23:21
CM_EVENT_GAIND_MSB 3
A2W_PLLH_RCAL_BYPEN_MSB 9
CAM0_CAMIDCA 0x7e800140:RW
PM_RSTC_WRCFG_SET 0x00000030
DMA6_DEST_AD_MASK 0xffffffff
CAM0_CAMIDCD 0x7e800144:RW
CM_SMICTL_SRC_LSB 0
DMA15_TI_PERMAP_LSB 16
CM_PERIADIV_DIV_LSB 12
DMA_INT_STATUS_INT7_CLR 0xffffff7f
CM_GNRICDIV_RESET 0000000000
DMA3_CS_ACTIVE_BITS 0:0
SMI_DSW3_WPACE_BITS 14:8
TB_BOOT_OPT_FPGA_LSB 2
CM_PLLD_LOADCORE_CLR 0xffffffef
AVE_OUT_CB_COEFF_RED_COEFF_MSB 29
FPGA_MB_XSYS_BUILD_NUM_MASK 0xffffffff
SCALER_DISPSTAT_WR_IRQ_LSB 5
APERF1_BW2_CTRL_BUS_CLR 0xffffffe0
I2C1_FIFO_RESET 0000000000
A2W_PLLD_ANA_SCTL_RESET_BITS 4:4
APERF0_BW2_CTRL_MASK 0xf0001f1f
USB_GUSBCFG_ULPI_AUTO_RES_MSB 18
CM_EVENT_FLOSSB_LSB 15
HDMI_VERTB1_MANUAL_VBP1_CLR 0xfffffeff
SD_PHYC_VREF_ENB_CLR 0xffffffef
APERF1_BW1_CTRL_EN_CLR 0xbfffffff
A2W_PLLD_ANA_SCTL_WIDTH 5
PCM_CS_A_RXSEX_SET 0x00800000
USB_HCCHAR0_MPS_SET 0x000007ff
V3D_VPACNTL_WIDTH 32
USB_GRXSTSP_DEV_DPID_BITS 16:15
A2W_PLLH_ANA_SCTL_RESET_CLR 0xffffffef
MPHI_INTSTAT_RX0MEND_SET 0x00000001
SD_SECSRT1 0x7ee00044:RW
SD_SECSRT2 0x7ee0004c:RW
SD_SECSRT3 0x7ee00054:RW
GP_REN2_RENn64_BITS 5:0
L1_D_PRIORITY_c0_uc_priority_BITS 7:4
VEC_SECAM_GAIN_VAL_MASK 0xffffffff
GP_FSEL0_FSEL08_LSB 24
DMA7_DEBUG_LITE_LSB 28
CM_EVENT_A2WDONE_SET 0x00100000
AUX_MU_FCR_REG (0x7E215000 +0x048)
DMA3_CS_ERROR_LSB 8
MPHI_TXAXICFG_TXNPRIO_BITS 3:0
FPGA_CTRL0_SPI0_SEL_A_CLR 0xfffffdff
SMI_DSW3_WSTROBE_BITS 6:0
APHY_CSR_DDR_PLL_CH1_DESKEW_CTRL 0x7ee06060:RW
HDMI_RAM_PACKET_8_1_MASK 0xffffffff
SD_MR_ADDR_BITS 7:0
A2W_PLLD_ANA_SSCL_RESET 0000000000
SMI_CS_INTT_SET 0x00000400
EMMC_IRPT_MASK_DEND_ERR_SET 0x00400000
GP_LEN2_LENn64_SET 0x0000003f
USB_DCFG_DEV_SPD_CLR 0xfffffffc
HDMI_RAM_PACKET_5_5_RESET 0000000000
USB_HFNUM_REM_CLR 0x0000ffff
I2C_SPI_SLV_FR_TXBUSY_SET 0x00000001
PIXELVALVE_1_BASE_ADDRESS 0x7e207000
PCM_RXC_A_CH2POS_SET 0x00003ff0
DMA15_TI_WAITS_LSB 21
SD_SECSRT2_ADDR_MS_MSB 31
A2W_PLLC_DIG3_WIDTH 24
EMMC_IRPT_MASK_OEM_ERR_MSB 31
CM_PCMCTL_BUSYD_SET 0x00000100
DMA3_DEBUG_VERSION_SET 0x0e000000
DMA7_CS_DREQ_CLR 0xfffffff7
DMA8_NEXTCONBK_ADDR_CLR 0x0000001f
SH_EDM_FIFO_COUNT_CLR 0xfffffe0f
USB_HCINT0_XACT_ERR_MSB 7
MS_SEMA_9_MASK_BITS 0:0
USB_DIEPTSIZ14_WIDTH 32
V3D_SQRSV0 0x7ec00000 +0x0410:RW
V3D_SQRSV1 0x7ec00000 +0x0414:RW
HDMI_RAM_PACKET_1_7_RESET 0000000000
AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_CLR 0xfffff000
SD_DQLCRC14_RISE_RESET 0x0
SMI_CS_INTT_BITS 10:10
A2W_PLLC_DIG1_MASK 0x00ffffff
A2W_PLLD_ANA_SSCS_MODE_CLR 0xfffeffff
FPGA_STATUS0_SW_SPI_SPI_IN_MSB 7
FPGA_MB_XH264_BUILD_NUM 0x7e20b710:RO
DMA6_DEST_AD_D_ADDR_CLR 0x00000000
TB_JTB_TMS_MASK 0xffffffff
DMA0_DEBUG_OUTSTANDING_WRITES_BITS 7:4
DMA11_TI_SRC_IGNORE_SET 0x00000800
DMA2_CS_DREQ_CLR 0xfffffff7
HDMI_AUDIO_PACKET_CONFIG 0x7e90209c:RW
ALIAS_STREAMING(x) MACRO
IMASK1_1 0xffffffff:RW
PM_RSTS_HADWRQ_BITS 4:4
USB_GPVNDCTL_CTRL_ULPI_CLR 0xffffc0ff
SPI_FIFO_DATA_LSB 0
HDCP_KEY_CTL_DONE_CLR 0xfffffffd
HDMI_RAM_PACKET_13_2_RESET 0000000000
V3D_CT1PC_MASK 0xffffffff
BIT_STREAM_DMA (0*(1<<16))
A2W_PLLB_ANA1R_RESET 0x001d0000
EMMC_HWCAP0_ADMA2_CLR 0xfff7ffff
FPGA_STATUS0_SD_WP_BITS 4:4
MS_IREQ_0_IREQ_0_MSB 31
CM_LOCK_FLOCKB_LSB 9
CM_PCMCTL_KILL_SET 0x00000020
AUX_MU_FCR_RXCLR 0x02
DMA4_CS_PAUSED_SET 0x00000010
IC0START L1_I_FLUSH_S
DMA3_TI_DEST_IGNORE_SET 0x00000080
CM_DFTCTL_FRAC_CLR 0xfffffdff
V3D_PCTR14_WIDTH 32
HDMI_RAM_PACKET_12_5_RESET 0000000000
PIXELVALVE1_INTSTAT_WIDTH 10
L2_CONT_OFF_l2_standby_BITS 11:10
USB_DIEPTSIZ0_RX_DPID_LSB 29
SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_BITS 15:8
SD_SECSRT2_ADDR_MS_LSB 13
USB_GHWCFG2_EN_PERIO_HOST_SET 0x00040000
CM_GP0DIV_DIV_CLR 0xff000000
A2W_XOSC_CTRL_MASK 0x000ff0ff
DMA1_TXFR_LEN_YLENGTH_CLR 0xc000ffff
SD_DQRCRC6_FALL_SET 0x0000ffff
ASB_H264_S_CTRL_WCOUNT_MSB 23
CM_SYSDIV_DIV_MSB 12
USB_GINTMSK_P_TXF_EMP_LSB 26
USB_HCTSIZ0_PKT_CNT_CLR 0xe007ffff
EMMC_HWCAP0_MAXLEN_CLR 0xfffcffff
A2W_PLLB_ANA_SSCSR_RESET 0000000000
DMA11_DEST_AD 0x7e007b10:RO
CM_SDCCTL_UPDATE_MSB 17
PM_PADS2_DRIVE_SET 0x00000007
DMA15_TI_DEST_IGNORE_SET 0x00000080
PCM_CS_A_TXCLR_BITS 3:3
USB_DIEPINT0_BNA_CLR 0xfffffdff
TXP_DIM_HEIGHT_CLR 0xf000ffff
A2W_PLLH_ANA_KAIP_KA_SET 0x00000700
PWM_CTL_POLA4_LSB 28
HDMI_RAM_PACKET_2_0_MASK 0xffffffff
CM_TD1CTL_GATE_CLR 0xffffffbf
CCP2TX_TS_IS_BITS 16:16
EMMC_IRPT_EN_TUNE_ERR_MSB 26
EMMC_FORCE_IRPT_TUNE_ERR_LSB 26
CM_ARMDIV_DIV_LSB 12
AVE_OUT_Y_COEFF 0x7e24000c:RW
SD_CMD_WIDTH 28
A2W_PLLA_ANA_SCTL_UPDATE_CLR 0xfffffff7
CSI2_THSSTO CSI2_BASE_ADDRESS + 0x14:RW
USB_GOTGINT_HST_NEG_SUC_STS_CHG_SET 0x00000200
TXP_CTRL_VERSION_CLR 0xff3fffff
DMA12_CS_DREQ_BITS 3:3
SPI_CS_RXD_MSB 17
UART_MSR_DCD_MSB 7
A2W_PLLC_CORE0R_WIDTH 10
NU_HOSTIO_OF_WIDTH 32
CM_PWMCTL_BUSYD_CLR 0xfffffeff
ASB_ISP_M_CTRL_WIDTH 24
HDMI_CTS_PERIOD_0 0x7e9020b4:RW
HDMI_CTS_PERIOD_1 0x7e9020b8:RW
DMA13_NEXTCONBK_ADDR_SET 0xffffffe0
DMA15_TI_PERMAP_BITS 20:16
SD_CS_DLLCAL_MSB 11
INTERRUPT_TIMER2 ((64) + 2 )
USB_HPRT_ENA_MSB 2
PM_AVS_INTEN_ALERT_V3D_G_LSB 3
CM_SMICTL_BUSYD_LSB 8
A2W_PLLC_ANA2_MASK 0x00ffffff
V3D_DBQRUN 0x7ec00000 +0x0e20:RW
SMI_A_ADDR_CLR 0xffffffc0
USB_GHWCFG3_I2C_INTERFACE_BITS 8:8
IC0_FORCE1_MASK 0xffffffff
A2W_XOSC_BIAS_BIAS_BITS 3:0
DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
V3D_SQCNTL_MASK 0x0000000f
DMA11_DEST_AD_D_ADDR_SET 0xffffffff
GRTCS0 0x1A005200 + 0x00:RW
GP_AREN0_ARENn0_BITS 31:0
SH_HSTS_WIDTH 11
CM_VECCTL_ENAB_MSB 4
CM_SDCCTL_FRAC_MSB 9
USB_DPTXFSIZ6_MASK 0xffffffff
CM_CAM0CTL_BUSY_LSB 7
GP_FSEL0_FSEL01_CLR 0xffffffc7
A2W_PLLA_ANA_SCTL_SEL_LSB 0
CM_ISPCTL_BUSY_MSB 7
MPHI_C1INDCF_EMPTY_MSB 31
GRPSBCG 0x1A005600 + 0x48:RW
DMA4_CS_INT_MSB 2
DMA7_NEXTCONBK 0x7e00771c:RO
SCALER_DISPSTAT_PROF_IRQ_LSB 0
CM_SDCDIV_DIV_BITS 17:12
PWM_STA_EMPT1_CLR 0xfffffffd
A2W_SMPS_C_CLK_OSCDIV_CLR 0xfffffffc
CCP2TX_TAC_TPC_MSB 3
EMMC_IRPT_MASK_CBAD_ERR_MSB 19
DMA3_DEBUG_DMA_ID_CLR 0xffff00ff
DMA10_CS_PAUSED_LSB 4
TE_2C_MASK 0xffffffff
PM_RSTS_HADDRF_MSB 1
INTERRUPT_SPARE1 ((64) + 35 )
USB_GHWCFG4_EN_IDDIG_FILTER_BITS 20:20
INTERRUPT_SPARE3 ((64) + 61 )
INTERRUPT_SPARE4 ((64) + 62 )
IC1_MASK7 0x7e00282c:RW
A2W_PLLB_ANA_KAIP_KA_BITS 10:8
USB_DOEPINT0_BNA_BITS 9:9
CAM1_CAMIDI1_WIDTH 32
A2W_PLLB_FRAC_RESET 0000000000
EMMC_SLOTISR_VER_MASK 0xffff00ff
SCALER_DISPSTAT_DMA_ERR_BIT2_SET 0xffffff80
I2C_SPI_SLV_DR_RXBUSY_SET 0x00200000
VEC_CGMSAE_TOP_CONTROL_WIDTH 32
GRFCFG 0x1A005400 + 0x04:RW
PIXELVALVE2_VERTB_EVEN_MASK 0xffffffff
SMI_CS_ENABLE_BITS 0:0
GP_AJBTDO_WIDTH 32
USB_DTHRCTL_ISO_THR_EN_BITS 1:1
MPHI_C1INDCF_ORUN_MSB 29
CAM0_CAMDAT2_WIDTH 32
CM_SDCDIV 0x7e1011ac:RW
DSI1_PHYC_MASK 0xffffffff
L2_FLUSH_STA 0x7ee01004:RW
EMMC_INTERRUPT_BLOCK_GAP_BITS 2:2
CPG_Param0_MASK 0xffffffff
MPHI_C1INDDB_TENDINT_BITS 29:29
CM_AVEOCTL_SRC_LSB 0
A2W_SMPS_CTLB2R_MASK 0x00ffffff
CM_TDCLKEN_HDMIBYP_CLR 0xfffffeff
HDMI_SCHEDULER_CONTROL_IGN_VSYNC_PREDS_LSB 5
DMA0_DEBUG_VERSION_CLR 0xf1ffffff
DSI0_LPRX_TO_C_RESET 0000000000
MPHI_C0INDDB_MORUN_LSB 31
MULTICORE_SYNC_VPU_SEMA_0 MULTICORE_SYNC_BASE_ADDRESS + 0xC0:RW
MULTICORE_SYNC_VPU_SEMA_1 MULTICORE_SYNC_BASE_ADDRESS + 0xC4:RW
EMMC_CMDTM_RESET 0000000000
USB_HPRT_CONN_DET_CLR 0xfffffffd
PWM_CTL_MSEN2_LSB 15
SH_DATA 0x7e202040:RW
SMI_DSW0_WPACEALL_BITS 15:15
USB_DOEPCTL0_DPID_CLR 0xfffeffff
CAM1_CAMIHWIN 0x7e801120:RW
DMA2_DEBUG_VERSION_BITS 27:25
GROPCTR_FBC_EZ_FE_HITS 0x3B
HDMI_SCHEDULER_CONTROL_ENC_ONLY_WHEN_AUTH_LSB 6
JP_QCTRL 0x7e005048:RW
CM_PCMCTL_RESET 0x00000200
SMI_CS_TXD_RESET 0x1
AVE_IN_CTRL_PRIORITY_LIMIT_MSB 26
DSI0_CTRL_CTRL2_LSB 2
SMI_DSW3_WSETUP_MSB 29
DMA3_TI_DEST_INC_CLR 0xffffffef
AUX_IO_BASE 0x7E215000
USB_DIEPINT0_TXF_EMPTY_RESET 0x0
GP_FSEL5_FSEL57_BITS 23:21
APERF0_BW1_CTRL 0x7e009880:RW
PM_CCP2TX_LDOEN_BITS 1:1
DMA4_TI_PERMAP_SET 0x001f0000
USB_DIEPTXF1_FIFO_SIZE_BITS 31:16
TB_JTB_TMS 0x7e20b804:RW
DMA1_TI_WAIT_RESP_LSB 3
SH_CDIV_WIDTH 11
SMICS_SETERR 13
PCM_INTEN_A_MASK 0x0000000f
AJB_IN_FALL 0x000000
GP_AREN1_ARENn32_MSB 31
SD_DQRCRC1_RISE_MSB 31
DMA8_TI_PERMAP_BITS 20:16
MULTICORE_SYNC_VPU_SEMA_x(x) MACRO
AVE_OUT_CTRL_BYTE_SWAP_CLR 0xff07ffff
GP_FSEL4_FSEL47_MSB 23
SD_DQLCRC14_RISE_SET 0xffff0000
PM_PADS0_SLEW_BITS 4:4
DMA12_DEBUG_DMA_STATE_LSB 16
USB_GINTMSK_RXF_LVL_CLR 0xffffffef
GP_FSEL6_FSEL68_CLR 0xf8ffffff
CM_DFTCTL_FRAC_BITS 9:9
DMA14_CS_PAUSED_MSB 4
TXP_CTRL_BUSY_BITS 1:1
PM_PADS2_HYST_LSB 3
PCM_TXC_A_CH1WID_CLR 0xfff0ffff
A2W_PLLC_DIG1R_RESET 0x00004000
SCALER_DISPSTAT_DSP0_IRQ_BITS 31:1
SMI_DSR3_RPACEALL_BITS 15:15
DMA13_DEBUG_MASK 0x1ffffff7
MPHI_C0INDDB_MTERM_CLR 0xefffffff
SD_DQRCRC10_RISE_LSB 16
CM_UARTCTL_WIDTH 10
PIARBCTL_CAM_DELAY_CLR 0xfffffff3
DSI_DMA ( 1*(1<<16))
CM_GNRICCTL_KILL_CLR 0xffffffdf
DMA3_CONBLK_AD_WIDTH 32
PWM_CTL_PWEN2_CLR 0xfffffeff
CM_GP1DIV_WIDTH 24
PIARBCTL_CAM_THRESHOLD_RESET 0x0
A2W_PLLD_DSI0R_WIDTH 10
DMA13_DEBUG_DMA_STATE_BITS 24:16
SD_DQLCRC11_RISE_RESET 0x0
SLIM_CON2_MASK 0xff008001
CM_SYSCTL_GATE_SET 0x00000040
MPHI_C0INDDB_MENDINT_SET 0x40000000
A2W_PLLC_CTRL_PRSTN_LSB 17
A2W_PLLC_CTRLR_RESET 0x00010000
MPHI_HSINDCF_LENERR_CLR 0xbfffffff
OTP_BASE 0x7e20f000
A2W_PLLH_DIG1_RESET 0000000000
HD_CSC_12_11_RESET 0000000000
HD_HDM_CTL_ENDIAN_CLR 0xfffffffd
PIXELVALVE0_VSYNCD_EVEN_WIDTH 17
USB_GINTMSK_ULPI_CK_INT_MSB 8
AVE_OUT_CR_COEFF_BLUE_COEFF_BITS 9:0
DMA8_TI_SRC_IGNORE_MSB 11
FPGA_DCM_RD_DATA_DATA_MSB 15
A2W_PLLH_PIXR_WIDTH 10
DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
I2C1_DEL_MASK 0xffffffff
HDMI_RAM_PACKET_5_3_WIDTH 32
USB_DFIFO14_MASK 0xffffffff
TXP_CTRL_TRANSPOSE_LSB 6
MPHI_INTSTAT_HSDISC_CLR 0xbfffffff
DMA9_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
CM_SDCCTL_BUSYD_MSB 8
EMMC_STATUS_CARD_STABLE_CLR 0xfffdffff
USB_GPVNDCTL 0x7e980034:RW
GRFECFG 0x1A005400 + 0x30:RW
CM_VECCTL_KILL_CLR 0xffffffdf
L2_CONT_OFF_l2_flush_mode_SET 0x00000018
USB_DIEPCTL0_DIS_SET 0x40000000
GP_SET0_SETn0_MSB 31
I2C2_C_MASK 0x00008701
CAM0_CAMCMP1_RESET 0000000000
GP_FSEL5_FSEL57_SET 0x00e00000
EMMC_BUS_CTRL_CLK_PINS_BITS 2:0
DMA4_CS 0x7e007400:RW
V3D_BXCF_MASK 0x00000003
USB_GOTGINT_DBNCE_DONE_MSB 19
HDMI_RAM_PACKET_1_5_WIDTH 32
EMMC_IRPT_MASK_ENDBOOT_BITS 14:14
DMA_TI_D_32 0
MS_MBOX_2_WIDTH 32
SCALER_DISPECTRL_Y_NE_CTRL_BITS 31:28
DMA6_DEBUG_FIFO_ERROR_MSB 1
SD_MR_HI_Z_SET 0x20000000
DMA6_CS_RESET_CLR 0x7fffffff
USB_GHWCFG4_EN_DED_TX_FIFO_SET 0x02000000
CM_EVENT_LOSSB_LSB 6
CM_VECCTL_SRC_BITS 3:0
EMMC_BLKSIZECNT 0x7e300004:RW
PM_PADS3_DRIVE_SET 0x00000007
A2W_PLLB_SP1_DIV_CLR 0xffffff00
CM_SDCCTL_ENAB_LSB 4
SH_EDM_WRITE_THRESHOLD_MSB 13
SD_WDC_RESET 0000000000
MPHI_C1INDCF_LENERR_MSB 30
CM_GNRICCTL_GATE_LSB 6
EMMC_CONTROL2_ACEND_ERR_MSB 3
CM_CAM0CTL_KILL_MSB 5
USB_DOEPINT0_STS_PHSE_RCVD_LSB 5
L1_IC1_RD_HITS_WIDTH 0
HDMI_RAM_PACKET_7_0_RESET 0000000000
HD_VID_CTL_EMPRGB_RESET 0x0
DMA13_CONBLK_AD 0x7e007d04:RW
A2W_XOSC_CTRL_PLLAOK_LSB 18
INTERRUPT_DMA_ALL ((64) + 28 )
I2C_SPI_SLV_DR_RXFLEVEL_SET 0xf8000000
APHY_CSR_GLBL_ADR_DLL_LOCK_STAT 0x7ee06020:RW
CAM1_CAMDCS_WIDTH 32
L1_D_CONTROL_DC_DISABLE_MSB 0
EMMC_CMDTM_TM_DAT_DIR_MSB 4
CM_HSMCTL_FRAC_BITS 9:9
DMA3_CONBLK_AD 0x7e007304:RW
A2W_SMPS_B_STAT_VOLTS_CLR 0xffffffe0
VEC_CPS1213_CPS1415_WIDTH 32
EMMC_FORCE_IRPT_SDOFF_ERR_BITS 23:23
PCM_TXC_A_CH1EN_BITS 30:30
UART_LSR_FE_BITS 3:3
SD_IDL_WIDTH 28
DMA15_CS 0x7ee05000:RW
DPHY_CSR_NORM_READ_DQS_GATE_CTRL 0x7ee0703c:RW
DMA11_CS_DREQ_MSB 3
USB_DSTS_ENUM_SPD_BITS 2:1
DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
HDMI_RAM_PACKET_3_2_RESET 0000000000
CM_OTPDIV 0x7e101094:RW
USB_DTXFSTS9_WIDTH 32
USB_DSTS 0x7e980808:RW
L1_L1_SANDBOX_START1_START_ADDR_SET 0x3fffffe0
AVE_OUT_CB_COEFF_RED_COEFF_BITS 29:20
INTERRUPT_CODEC0 ((64) + 4 )
INTERRUPT_CODEC1 ((64) + 5 )
INTERRUPT_CODEC2 ((64) + 6 )
APERF0_BW1_CTRL_LATHALT_RESET 0x0
TS_TSENSSTAT_INTERUPT_SET 0x00000800
CM_PLLH_LOADAUX_LSB 1
SMI_CS_TXE_CLR 0xbfffffff
SCALER_DISPBASE2_MASK 0xffffffff
USB_DTHRCTL_RX_THR_EN_RESET 0x0
V3D_CT1EA_MASK 0xffffffff
DMA12_TI_DEST_DREQ_CLR 0xffffffbf
SMI_DCS_WRITE_LSB 3
SMI_DC_PANICR_CLR 0xff03ffff
CAM0_CAMIDPO 0x7e80013c:RW
I2C_SPI_SLV_SLV_RESET 0000000000
USB_HCTSIZ0 0x7e980510:RW
USB_HCTSIZ1 0x7e980530:RW
GP_FSEL4_FSEL43_LSB 9
USB_HCTSIZ3 0x7e980570:RW
USB_HCTSIZ4 0x7e980590:RW
USB_HCTSIZ5 0x7e9805b0:RW
USB_HCTSIZ6 0x7e9805d0:RW
USB_HCTSIZ7 0x7e9805f0:RW
CM_LOCK_RESET 0000000000
FPGA_STATUS0_HW_ID_CLR 0xfffffff0
APERF0_BW1_RTWAIT 0x7e0098a0:RO
SMI_DSR3_RWIDTH_MSB 31
SCALER_DISPCTRL_DSP2_PANIC_BITS 29:28
USB_DOEPDMAB1_WIDTH 32
VCE_REGISTERS_BASE 0x7f000000 + 0x120000:RW
USB_GUSBCFG_ULPI_EXT_VBUS_IND_RESET 0x0
EMMC_SPI_INT_SPT_WIDTH 8
CM_AVEOCTL_BUSYD_CLR 0xfffffeff
USB_GUSBCFG_ULPI_AUTO_RES_CLR 0xfffbffff
AUX_IRQ (0x7E215000 +0x000)
USB_DIEPTSIZ0_PKT_CNT_SET 0x1ff80000
USB_DIEPTSIZ1_MASK 0xffffffff
USB_DOEPDMAB2_MASK 0xffffffff
SCALER_DISPLACT0_MASK 0xffffffff
DMA_INT_STATUS_INT13_CLR 0xffffdfff
I2CC_INTD (1 << 8)
HDMI_PERT_CONFIG 0x7e902074:RW
USB_DOEPCTL0_ENA_MSB 31
APERF0_BW0_ATRANS_WIDTH 32
A2W_HDMI_CTL_MULTI_RESET 0000000000
ACPLAYRATE 0x2c
CM_ARMDIV_DIV_CLR 0xffffefff
HDMI_FIFO_CTL_USE_FULL_CLR 0xfffffffd
GROPCTR_FEZCULLEDQUADS 0x06
IC1_MASK0_MASK 0x77777777
HDCP_KEY_ADR_RESET 0000000000
I2C_SPI_SLV_CR_TXE_BITS 8:8
DMA9_TI_WAITS_LSB 21
A2W_SMPS_A_GAIN_DIGGAIN_CLR 0xfffffff8
DMA11_TI_WAIT_RESP_LSB 3
USB_DIEPTXF1_FIFO_STADDR_CLR 0xffff0000
PM_APB_ID 0x0000706d
HDMI_HOTPLUG_INT 0x7e902008:RW
PM_RSTS_HADWRF_LSB 5
GP_REN2_MASK 0x0000003f
DSI1_LP_DLT6_WIDTH 32
DMA5_TI_DEST_INC_BITS 4:4
DMA5_STRIDE_D_STRIDE_MSB 31
BOOTROM_RAM_START ( 0x10000000 + 0x8000 )
USB_GRXSTSP_DEV_FN_SET 0x01e00000
ARM_MC_ERRUNDRFLW 0x00000400
A2W_PLLB_ANA_SSCS_STEP_CLR 0xffff0000
CM_INTEN_MASK 0x00ffffff
CM_TSENSCTL_BUSYD_BITS 8:8
HDMI_ASYNC_RM_PHASE_INC (HDMI_BASE_ADDRESS + 0x300) + 12:RW
MS_SEMA_21_WIDTH 1
DPHY_CSR_DQ_PVT_COMP_DEBUG 0x7ee07060:RW
TS_TSENSCTL_CTRL_SET 0x0000001c
SMI_CS_PRDY_CLR 0xfeffffff
ASB_V3D_S_CTRL_EMPTY_BITS 2:2
L2_CONT_OFF_l2_flush_flush_limit_SET 0x000f0000
VCE_BUSY_DMAOUT 0x09
EMMC_INTERRUPT_SDOFF_ERR_MSB 23
HDCP_KEY_CTL 0x7e809000:RW
VEC_CPS2021_CPS2223 0x7e806134:RW
A2W_SMPS_A_VOLTS_VOLTS_BITS 4:0
DMA7_DEBUG_VERSION_MSB 27
PM_DSI0_LDOLPEN_LSB 1
CCP2TX_TAC_CTATADJ_MSB 31
APERF1_BW2_WMAX_RESET 0000000000
TXP_CTRL_ALPHA_ENABLE_MSB 20
SH_CDIV_CLOCKDIV_MSB 10
CM_ARMCTL_KILL_BITS 5:5
DMA10_SOURCE_AD_S_ADDR_LSB 0
SD_SECSRT2_EN_BITS 0:0
HD_HDM_CTL_RESET 0x000000f0
USB_DCFG_WIDTH 26
INTERRUPT_USB ((64) + 9 )
CM_EMMCCTL_ENAB_SET 0x00000010
SYSAC_L2_ARBITER_CONTROL_DELAY_LSB 2
DMA11_SOURCE_AD_S_ADDR_MSB 31
DMA4_TXFR_LEN_YLENGTH_MSB 29
I2C2_S_RESET 0x00000050
A2W_PLLD_ANA3R_WIDTH 24
DMA7_TI_DEST_IGNORE_LSB 7
PWMSTA_STA1 9
PWMSTA_STA2 10
PWMSTA_STA3 11
PWMSTA_STA4 12
HDMI_RAM_PACKET_10_4_MASK 0xffffffff
A2W_PLLH_RCAL_DIV_CLR 0xffffff00
USB_HCCHAR0_CH_DIS_RESET 0x0
HD_HDM_CTL_SW_RST_LSB 2
USB_HCINT0_CH_HLTD_CLR 0xfffffffd
CMPLL3 0x7C:RW
SYSAC_SRC_ARBITER_CONTROL_LIMIT_MSB 1
SD_PHYC_PHYRST_LSB 0
CMPLLC 0x7C:RW
EMMC_HWCAP1_MULTIPLIER_CLR 0xff00ffff
CM_OTPDIV_DIV_LSB 12
PWM_DAT2_MASK 0xffffffff
A2W_PLLC_ANA_SSCSR_RESET 0000000000
SPI_CS 0x7e204000:RW
A2W_PLLH_FRAC_RESET 0000000000
DMA15_CS_ERROR_SET 0x00000100
ASB_H264_S_CTRL_CLR_ACK_LSB 1
DMA5_NEXTCONBK_ADDR_LSB 5
SYSAC_DMA_ARBITER_CONTROL_LITE_RESET 0000000000
AVE_IN_CTRL_OVERRUN_IRQ_EN_MSB 0
SYSAC_DMA_ARBITER_CONTROL_L2_MASK 0x0000ffff
I2C_SPI_SLV_FR 0x7e214010:RW
DMA5_TI_DEST_WIDTH_SET 0x00000020
CM_ISPCTL_FRAC_LSB 9
DMA4_TXFR_LEN_XLENGTH_LSB 0
SMI_DSR3_RHOLD_SET 0x003f0000
EMMC_STATUS_CMD_INHIBIT_LSB 0
ARM_C0_PRIO_L2 0x0F000000
USB_DIEPINT_off(n) MACRO
DMA3_DEST_AD_D_ADDR_LSB 0
CRYPTO_ISR 0x7e00200c:RO
DMA9_DEBUG_MASK 0x1ffffff7
PM_IMAGE_H264RSTN_BITS 7:7
MS_SEMA_17_MASK_CLR 0xfffffffe
SD_SECSRT1_ADDR_MS_CLR 0x00001fff
HDMI_CPU_SET_WIDTH 32
CM_PLLTCTL_KILL_CLR 0xffffffdf
PM_PADS0_HYST_SET 0x00000008
DMA10_TI_SRC_IGNORE_MSB 11
EMMC_IRPT_EN_OEM_ERR_BITS 31:30
SPI_CS_DONE_SET 0x00010000
EMMC_CONTROL2_SIGTYPE_CLR 0xfff7ffff
DPHY_CSR_DQ_PAD_MISC_CTRL 0x7ee07050:RW
MS_SEMA_6_MASK_LSB 0
PM_PROC_CFG_MSB 22
PM_DUMMY_ONE_MSB 0
FPGA_CTRL0_SPARE_OUT_SET 0xfff00000
RNG_CTRL_WIDTH 32
APERF1_BW0_RPEND 0x7ee08068:RO
MPHI_OUTDDB_CHANNEL_CLR 0xefffffff
PWM_CTL_SBIT3_LSB 19
DMA11_DEBUG_FIFO_ERROR_SET 0x00000002
SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_RESET 0x0
EMMC_IRPT_EN_CARD_IN_CLR 0xffffffbf
DMA15_STRIDE_MASK 0xffffffff
EMMC_CONTROL0_PWCTL_ON_CLR 0xfffffeff
DMA15_DEST_AD_D_ADDR_LSB 0
PCM_POS1(x) MACRO
PCM_POS2(x) MACRO
USB_DOEPINT12_MASK 0xffffffff
MS_SEMA_0 0x7e000000:RW
HDMI_DETECTED_VERTA1_MANUAL_VSP1_CLR 0xfe0fffff
MS_SEMA_2 0x7e000008:RW
MS_SEMA_3 0x7e00000c:RW
CM_PLLTCTL_SRC_BITS 2:0
MS_SEMA_5 0x7e000014:RW
MS_SEMA_6 0x7e000018:RW
MS_SEMA_7 0x7e00001c:RW
MS_SEMA_8 0x7e000020:RW
CM_SLIMCTL_MASH_LSB 9
EMMC_IRPT_EN_CCRC_ERR_SET 0x00020000
I2C_SPI_SLV_RSR_RXDMABREQ_LSB 5
DMA10_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
SD_DQRCRC7_FALL_BITS 15:0
CM_INTEN_FGAINB_BITS 11:11
SD_SB_INHIBIT_LA_BITS 8:8
SD_DQLCRC3_MASK 0xffffffff
EMMC_HWMAXAMP0_AMP_33V_SET 0x000000ff
SLIM_DMA_MC_TX_RESET 0000000000
CM_INTEN_FLOSSD_LSB 17
USB_GSNPSID_WIDTH 32
USB_DOEPCTL0_MPS_RESET 0x0
DMA2_DEBUG_LITE_BITS 28:28
EMMC_FORCE_IRPT_CARD_IN_CLR 0xffffffbf
USB_GRXSTSP_DEV_BCNT_RESET 0x0
PWM_STA_GAPO3_CLR 0xffffffbf
USB_GHWCFG3_VENDOR_CTL_INTERFACE_RESET 0x0
GP_FSEL1_FSEL16_CLR 0xffe3ffff
DMA_INT_STATUS_INT2_LSB 2
APHY_CSR_GLBL_ADR_MSTR_DLL_BYPEN 0x7ee0601c:RW
CM_PLLC_HOLDPER_LSB 7
GP_REN2_RESET 0000000000
EMMC_IRPT_EN_RETUNE_BITS 12:12
USB_HCCHAR0_CH_ENA_RESET 0x0
SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_BITS 5:4
SYSAC_V3D_LIMITER_HOLDOFF_RESET 0x0
HDMI_CTS_1_MASK 0x000fffff
CM_TSENSDIV 0x7e1010e4:RW
JDCCTRL_DCCOMP_MASK 0xFFFF
TB_BOOT_OPT_BOOT_HALT_LSB 7
CM_V3DCTL_MASK 0x000003ff
DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
PM_SMPS_CTRLEN_SET 0x00000001
CM_INTEN_FLOSSC_BITS 16:16
SD_CARCRC_FALL_CLR 0xffff0000
INTERRUPT_CCP2TX ((64) + 34 )
TS_BASE 0x7e212000
CM_SDCCTL_FRAC_LSB 9
SD_SD_T_RPab_MSB 31
SMICS_START 3
UNICAM_CTRL(x) MACRO
L1_L1_SANDBOX_START7_MASK 0x3fffffff
USB_GRXSTSP_HST_CH_NUM_MSB 3
PM_DSI1_LDOCTRL_SET 0x001ffff8
DMA5_TI_TDMODE_LSB 1
GROPCTR0 0x1A005100 + 0x080:RW
GROPCTR1 0x1A005100 + 0x088:RW
GROPCTR2 0x1A005100 + 0x090:RW
GROPCTR3 0x1A005100 + 0x098:RW
GROPCTR4 0x1A005100 + 0x0A0:RW
GROPCTR5 0x1A005100 + 0x0A8:RW
GROPCTR6 0x1A005100 + 0x0B0:RW
GROPCTR7 0x1A005100 + 0x0B8:RW
GROPCTR8 0x1A005100 + 0x0C0:RW
GROPCTR9 0x1A005100 + 0x0C8:RW
A2W_PLLB_ANA_SSCS_WIDTH 17
A2W_PLLB_SP2R_MASK 0x000003ff
CAM1_CAMIBEA1_RESET 0000000000
CM_INTEN_RESUS_BITS 22:22
CM_TSENSCTL_BUSYD_CLR 0xfffffeff
GROPCTRE 0x1A005100 + 0x074:RW
DMA4_TI_DEST_INC_CLR 0xffffffef
DMA2_CS_DREQ_STOPS_DMA_BITS 5:5
HDMI_RAM_PACKET_3_0_WIDTH 32
MPHI_INTCTRL_RX1DISC_RESET 0x0
DMA15_TI_DEST_INC_BITS 4:4
CM_INTEN_GAINC_CLR 0xfffffffb
SD_SD_T_XP_LSB 16
USB_GINTMSK_FET_SUSP_LSB 22
TS_TSENSSTAT_VALID_SET 0x00000400
L1_D_FLUSH_S_MASK 0x3fffffe0
CMI_CAM0_RX1SRC_LSB 4
FPGA_CTRL0_DIS_BL_SET 0x00000002
PM_USB_CTRLEN_BITS 0:0
EMMC_FORCE_IRPT_DCRC_ERR_MSB 21
PM_GNRIC_POWOK_SET 0x00000002
DMA5_CS_PRIORITY_BITS 19:16
EMMC_CONTROL0_HCTL_LED_SET 0x00000001
SYSAC_SRC_ARBITER_CONTROL_LIMIT_RESET 0x0
GP_FSEL0_FSEL05_SET 0x00038000
DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
HD_MAI_CTL_PAREN_RESET 0x0
ASB_H264_M_CTRL_CLR_ACK_BITS 1:1
CAM1_CAMDBG2_WIDTH 32
A2W_PLLD_ANA_SCTL_SEL_CLR 0xfffffff8
DMA3_CS_MASK 0xf0ff017f
TS_TSENSCTL_REGULEN_MSB 26
DMA2_TI_INTEN_SET 0x00000001
PM_PADS4_HYST_CLR 0xfffffff7
HDMI_RAM_PACKET_12_8_MASK 0xffffffff
CM_SDCDIV_DIV_MSB 17
PWM_CTL_RPTL1_LSB 2
EMMC_CONTROL0_READWAIT_EN_SET 0x00040000
IC1_MASK6_MASK 0x77777777
USB_DAINTMSK_WIDTH 32
AVE_OUT_STATUS_VFRONT_PORCH_SET 0x00000080
CM_DPICTL_WIDTH 10
DMA4_CONBLK_AD_WIDTH 32
USB_HCTSIZ0_DO_PNG_LSB 31
CM_TDCLKEN_PLLCBYP_BITS 2:2
A2W_PLLC_CORE0_BYPEN_BITS 9:9
USB_DOEPINT0_TX_FIFO_UNDRN_LSB 8
L1_L1_SANDBOX_PERI_BR_sandbox_peri_CLR 0xffffe0ff
PM_PXLDO_RSTOSCDR_MSB 16
DMA10_CS_DREQ_STOPS_DMA_MSB 5
V3D_CT0EA_WIDTH 32
A2W_SMPS_B_MULTI_WIDTH 0
RNG_FF_THRESHOLD_WIDTH 32
DMA11_TI_WAITS_MSB 25
DMA15_CS_DREQ_CLR 0xfffffff7
SCALER_DISPSTAT_WR_IRQ_BITS 31:5
V3D_DBSCS 0x7ec00000 +0x0e04:RW
PWMCTL 0x7e20c000 + 0x00:RW
CM_PULSECTL_ENAB_CLR 0xffffffef
PM_PADS4_POWOK_MSB 5
ASB_V3D_M_CTRL_EMPTY_MSB 2
A2W_PLLC_CORE0 0x7e102620:RW
DMA0_STRIDE_D_STRIDE_CLR 0x0000ffff
A2W_PLLC_CORE2 0x7e102320:RW
DMA2_DEBUG_OUTSTANDING_WRITES_MSB 7
ASB_H264_S_CTRL_EMPTY_BITS 2:2
PCM_CS_A_DMAEN_BITS 9:9
A2W_PLLA_ANA2_RESET 0000000000
SCALER_DISPSTAT_DSP1_IRQ_LSB 2
HDMI_VERTA1_MANUAL_VSP1_LSB 20
SMI_A_DEVICE_LSB 8
PM_AVS_RSTDR_H264_I_LSB 2
L1_IC0_PRIORITY_IC0_APRIORITY0_BITS 3:0
APERF1_BW0_RMAX_WIDTH 24
HDMI_RAM_PACKET_7_5_MASK 0xffffffff
DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
L1_IC0_CONTROL_DISABLE_VLINE_BITS 6:5
HDMI_RAM_PACKET_1_4_MASK 0xffffffff
SMI_DSW0_WPACE_CLR 0xffff80ff
USB_DIEPINT0_EP_DISBLD_MSB 1
DSI1_HS_CLT2 0x7e700058:RW
DMA9_DEST_AD 0x7e007910:RO
DMA6_TI_WAIT_RESP_MSB 3
A2W_PLLH_ANA0 0x7e102070:RW
A2W_PLLH_ANA1 0x7e102074:RW
A2W_PLLH_ANA2 0x7e102078:RW
A2W_PLLH_ANA3 0x7e10207c:RW
CM_H264DIV_WIDTH 16
USB_HCCHAR0_LSPD_DEV_SET 0x00020000
CM_CKSM_CFG_CLR 0xfffcffff
GPPUD 0x7e200000 + 0x94:RW
CM_VPUCTL_BUSYD_BITS 8:8
USB_DOEPINT0_BNA_MSB 9
DMA6_CS_PAUSED_CLR 0xffffffef
USB_DCTL_SGOUT_NAK_MSB 9
USB_DIEPDMAB7_MASK 0xffffffff
HD_VID_CTL_FULSYNC_LSB 22
A2W_SMPS_CTLC0_RESET 0000000000
L2_RD_HITS_MASK 0xffffffff
MPHI_C1INDDB_TENDINT_RESET 0x0
PM_PADS3_POWOK_LSB 5
APERF1_GEN_CTRL_MASK 0x00000003
MS_VPUSEMA_0_VPUSEMA_0_LSB 0
DMA10_CONBLK_AD_RESET 0000000000
USB_DIEPCTL0_TYPE_CLR 0xfff3ffff
DMA0_DEBUG_DMA_STATE_MSB 24
SMI_DSR2_RSTROBE_BITS 6:0
USB_GOTGCTL_SES_REQ_SCS_SET 0x00000001
USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_SET 0x03000000
PCM_CS_A_RXTHR_BITS 8:7
CM_H264CTL_BUSY_CLR 0xffffff7f
A2W_SMPS_C_CTL_UPEN_SET 0x00000002
A2W_PLLD_ANA0_WIDTH 24
DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
SD_DQLCRC0_WIDTH 32
DMA15_CS_RESET 0000000000
DMA3_CS_ABORT_CLR 0xbfffffff
SD_SECEND3_ADDR_LS_BITS 12:0
DMA7_CS_PAUSED_BITS 4:4
I2C_SPI_SLV_IMSC_OEIM_SET 0x00000008
DMA6_DEBUG_MASK 0x1ffffff7
PM_DSI0_MASK 0x001fffff
V3D_SQCSTAT_MASK 0xffffffff
PIXELVALVE0_VC_WIDTH 23
PWM_CTL_POLA1_SET 0x00000010
HDMI_PACKET_FIFO_STATUS_RESET 0x03010000
DMA7_CS_DREQ_STOPS_DMA_BITS 5:5
L1_L1_SANDBOX_START3_START_ADDR_SET 0x3fffffe0
A2W_SMPS_C_CTLR_WIDTH 2
USB_GPVNDCTL_MASK 0x8e7f3fff
HD_CSC_CTL_MODE_CLR 0xfffffff3
DMA8_CS_DISDEBUG_SET 0x20000000
SYSAC_PERI_ARBITER_CONTROL_LIMIT_RESET 0x0
A2W_PLLH_AUX_DIV_LSB 0
CM_TSENSCTL_ENAB_CLR 0xffffffef
SD_SC_T_WR_RESET 0x6
AVE_OUT_OFFSET_RED_OFFSET_BITS 23:16
MPHI_OUTDDB_HANDLE_BITS 27:20
HD_MAI_THR_DREQLOW_LSB 0
SLIM_DMA_MC_RX 0x7e210020:RW
HDMI_DVO_TIMING_ADJUST_D 0x7e902134:RW
MS_VPUSEMA_1_VPUSEMA_1_SET 0x00000001
CM_PULSEDIV 0x7e101194:RW
PCM_RXC_A_CH1POS_BITS 29:20
SD_VIN_VIO_LSB 20
L1_IC0_CONTROL_RAS_DISABLE_SET 0x00000010
DMA0_DEBUG_DMA_ID_BITS 15:8
SD_CARCRC_FALL_RESET 0x0
DMA12_CS_MASK 0xf0ff017f
SD_SB_ROWBITS_RESET 0x1
ARM_IE_BELL0 0x00000004
ARM_IE_BELL1 0x00000008
SPI_CS_DONE_BITS 16:16
CM_EVENT_WRFAIL_SET 0x00080000
VPU_ARB_CTRL_UC_ALGORITHM_CLR 0xffffff3f
A2W_PLLD_ANA_SCTL_SEL_SET 0x00000007
USB_GRSTCTL_DMA_REQ_LSB 30
DMA0_DEBUG_DMA_STATE_BITS 24:16
IC1_FORCE1_SET_WIDTH 32
EMMC_CONTROL0_HCTL_DMA_BITS 4:3
A2W_SMPS_C_MULTI_RESET 0000000000
PCM_RXC_A 0x7e20300c:RW
CM_GP1CTL_MASK 0x000007bf
PCM_DREQ_A_MASK 0x7f7f7f7f
L1_IC0_CONTROL_RESET 0000000000
SMI_DSW1_WHOLD_LSB 16
AVE_OUT_STATUS_PXL_OUTPUT_ERROR_BITS 1:1
APERF0_BW2_RTRANS 0x7e0098dc:RO
AUX_MU_LCR_DLAB 0x80
A2W_PLLC_PER_CHENB_SET 0x00000100
CM_GP1DIV_DIV_MSB 23
USB_HPTXSTS_HPTXFSPCAVAIL_MSB 15
CCP2TX_TS_TEI_MSB 18
CM_DSI0EDIV_DIV_MSB 15
CAM1_CAMIBSA1_MASK 0xffffffff
ARM_C0_PRIO_UC 0xF0000000
SH_HCFG_SLOW_CARD_LSB 3
V3D_INTENA 0x7ec00000 +0x0034:RW
DMA11_DEBUG_LITE_LSB 28
A2W_SMPS_L_SCVR_RESET 0000000000
GP_FSEL5_FSEL58_LSB 24
USB_GRXSTSP_DEV_EP_NUM_LSB 0
DMA15_TI_DEST_WIDTH_MSB 5
SD_SB_EIGHTBANK_BITS 4:4
AVE_OUT_STATUS_PXL_OUTPUT_ERROR_MSB 1
EMMC_IRPT_EN_CMD_DONE_CLR 0xfffffffe
A2W_PLLC_CORE2R_MASK 0x000003ff
CAM0_CAMDBCTL_RESET 0000000000
DMA15_CS_PRIORITY_BITS 19:16
DMA9_TI_WAIT_RESP_BITS 3:3
CM_GP1CTL_MASH_MSB 10
DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
HDMI_TX_PHY_TX_PHY_STATUS_RESET 0000000000
DMA13_CS_ERROR_LSB 8
SCALER_DISPSTAT_DSP2_IRQ_MSB 31
DMA4_STRIDE_S_STRIDE_CLR 0xffff0000
PCM_CS_A_RXON_BITS 1:1
APERF0_GEN_CTRL 0x7e009800:RW
SLIM_DMA_MC_TX 0x7e210024:RW
A2W_PLLD_DIG1R_MASK 0x00ffffff
AVE_IN_STATUS_EVEN_FIELD_LSB 11
IC1_MASK2_RESET 0000000000
SD_DQRCRC5_RISE_SET 0xffff0000
HD_CSC_CTL_ENABLE_BITS 0:0
DMA3_SOURCE_AD_S_ADDR_SET 0xffffffff
A2W_PLLA_ANA_VCO 0x7e102610:RW
DMA11_TI_DEST_WIDTH_CLR 0xffffffdf
A2W_PLLB_ANA3R_MASK 0x00ffffff
L1_L1_SANDBOX_PERI_BR_sandbox_peri_LSB 8
DMA4_TI 0x7e007408:RO
SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_BITS 5:4
CM_DPICTL_BUSY_BITS 7:7
SD_DQRCRC5_FALL_RESET 0x0
AVE_OUT_STATUS_VSYNC_LSB 9
OTP_BYTES_PER_ROW 4
EMMC_HWCAP0_TCLKFREQ_CLR 0xffffffc0
EMMC_IRPT_MASK_WRITE_RDY_SET 0x00000010
PM_IMAGE_RESET 0x00001000
CM_UARTCTL_BUSY_MSB 7
SCALER_DISPECTRL_SECURE_MODE_MSB 31
EMMC_INTERRUPT_DCRC_ERR_BITS 21:21
DMA4_TI_WAIT_RESP_SET 0x00000008
DMA6_TI_PERMAP_CLR 0xffe0ffff
SMI_DSR2_MODE68_BITS 23:23
HDMI_RAM_PACKET_3_8_MASK 0xffffffff
HDMI_RAM_GCP_2_WIDTH 32
FPGA_CTRL0_DISP_BUFFER_MSB 11
CM_TIMERDIV_DIV_MSB 17
USB_DIEPDMA2_WIDTH 32
AVE_OUT_STATUS_COEFF_ERROR_CLR 0xfffffffb
EMMC_FORCE_IRPT_WRITE_RDY_MSB 4
SMI_CS_PAD_BITS 7:6
HDMI_CTS_0 0x7e9020ac:RW
HDMI_CTS_1 0x7e9020b0:RW
PCM_INTEN_A_TXERR_BITS 2:2
SD_RWC_RXVAL_RESET 0x0
A2W_PLLH_CTRL_NDIV_SET 0x000000ff
DMA9_CS_ERROR_SET 0x00000100
CM_PLLD_HOLDDSI0_LSB 1
USB_HCTSIZ0_MASK 0xffffffff
SD_DQLCRC0_RISE_CLR 0x0000ffff
VCE_STATUS_OFFSET 0x40000
ARM_1_ALL_IRQS (0x7E00B000 +0x900)+0xF8:RW
DMA0_CS_ACTIVE_BITS 0:0
AVE_OUT_CTRL_REFRESH_RATE_BITS 3:2
DMA15_TI 0x7ee05008:RO
HDMI_CPU_MASK_SET 0x7e902350:RW
PM_GNRIC_ENAB_SET 0x00001000
DMA13_TI_SRC_IGNORE_CLR 0xfffff7ff
SMI_DSW0_WSETUP_BITS 29:24
A2W_PLLD_ANA_SSCSR_RESET 0000000000
CAM1_CAMCMP0 0x7e80102c:RW
VEC_CPS2829_CPS3031_WIDTH 32
USB_GINTMSK_WK_UP_INT_BITS 31:31
CCP2TX_TPC_TNP_LSB 0
USB_GMDIOCSR 0x7e980080:RW
TXP_CTRL_PILOT_RESET 0x54
A2W_PLLA_ANA_SCTL_WIDTH 5
DMA12_TI_WAIT_RESP_BITS 3:3
CM_TECCTL_BUSYD_CLR 0xfffffeff
HDMI_RAM_GCP_8_RESET 0000000000
HDMI_CP_TST_RESET 0000000000
EMMC_INTERRUPT_INT_A_MSB 9
ASB_H264_S_CTRL_RCOUNT_BITS 13:4
SD_SC_T_WTR_BITS 6:4
DMA2_DEBUG_WIDTH 29
SD_DQLCRC14_FALL_SET 0x0000ffff
L1_IC1_PRIORITY_IC1_APRIORITY0_CLR 0xfffffff0
SMI_DSW3_WSETUP_CLR 0xc0ffffff
CM_INTEN_BURSTDONE_LSB 23
USB_GRSTCTL_TXF_NUM_SET 0x000007c0
A2W_PLLB_CTRLR 0x7e1029e0:RW
APERF1_BW0_CTRL 0x7ee08040:RW
CCP2RBC0 CCP2_BASE_ADDRESS + 0x118:RO
CCP2RBC1 CCP2_BASE_ADDRESS + 0x218:RO
A2W_SMPS_L_SPV_MASK 0x0000001f
AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_BITS 31:31
APERF1_BW2_AMAX_WIDTH 24
GP_AJBTMS_RESET 0000000000
SD_DQRCRC10_FALL_LSB 0
HDMI_HOTPLUG_INT_RESET 0x00000006
SYSAC_DMA_ARBITER_CONTROL_UC_MASK 0x0000ffff
A2W_PLLA_ANA_SSCL_RESET 0000000000
HDMI_RAM_PACKET_12_6_RESET 0000000000
SCALER_DISPECTRL_GT8_BURST_BITS 31:24
DMA15_DEBUG_LITE_CLR 0xefffffff
DMA6_STRIDE_WIDTH 32
SMIDCS_DONE 2
SYSAC_L2_ARBITER_CONTROL_WIDTH 16
A2W_PLLA_ANA0_WIDTH 24
SH_RSP2_CID_CSD_LSB 0
MS_SEMA_15_MASK_MSB 0
SH_HCFG_MASK 0x0000073f
GP_FSEL3_FSEL30_MSB 2
USB_GRXFSIZ_WIDTH 16
DMA3_DEBUG_MASK 0x1ffffff7
PCM_CS_A_RXD_SET 0x00100000
USB_GOTGINT_MASK 0x000e0304
A2W_HDMI_CTL_RCAL_SELDIV_LSB 4
MS_SEMA_21_MASK_LSB 0
DMA14_CS_DREQ_STOPS_DMA_MSB 5
APERF0_BW0_CTRL_LATHALT_MSB 28
SLIM_DCC5_PROT_MASK 0xc001ffff
CMI_BASE 0x7e802000
DMA3_DEBUG_LITE_BITS 28:28
UART_MSR_DDSR_BITS 1:1
HDMI_READ_POINTERS_DOMAIN_RESYNC_RD_BITS 26:24
SD_DQRCRC2_RISE_CLR 0x0000ffff
DSI1_HS_CLT0_MASK 0xffffffff
USB_GINTMSK_MODE_MIS_LSB 1
CM_PWMDIV_MASK 0x00ffffff
DMA0_TI_INTEN_LSB 0
DMA12_DEBUG_READ_ERROR_SET 0x00000004
TXP_DIM_WIDTH_LSB 0
ST_CLO_WIDTH 32
CM_EVENT_FLOSSD_MSB 17
ARM_C0_PRIO_PER 0x00F00000
CM_TDCLKEN_PLLADIV2_SET 0x00000010
FPGA_DCM_CTRL_PERI_RST_CLR 0xfff0ffff
SD_SE_T_FAW_RESET 0x19
CM_OTPCTL_KILL_MSB 5
VPU_ARB_CTRL_L2_DELAY_LSB 2
GP_FSEL5_RESET 0000000000
PM_HDMI_LDOPD_CLR 0xfffffffd
IC1_FORCE0_CLR 0x7e002850:RW
EMMC_IRPT_EN_CARD_CLR 0xfffffeff
SMI_DSR0_RWIDTH_SET 0xc0000000
PM_AVS_EVENT_ALERT_SYSTEM_A_LSB 1
CM_TD0CTL_FRAC_CLR 0xfffffdff
CM_TIMERCTL_KILL_BITS 5:5
USB_GAHBCFG_GLBL_INTR_MSK_RESET 0x0
USB_GUSBCFG_HNP_CAP_CLR 0xfffffdff
EMMC_IRPT_MASK_WIDTH 32
SLIM_DMA_DC4_RESET 0000000000
CM_DSI1PCTL_FRAC_MSB 9
PM_GNRIC_CFG_CLR 0xff80ffff
SD_WTC_WIDTH 28
CM_DSI1ECTL_MASK 0x000003bf
PM_IMAGE_POWOK_LSB 1
USB_GUSBCFG_TOUT_CAL_CLR 0xfffffff8
SMI_DC_PANICW_BITS 17:12
HDMI_CTS_PERIOD_1_MASK 0xff0fffff
DMA11_DEBUG_FIFO_ERROR_BITS 1:1
HDMI_RAM_PACKET_6_5_RESET 0000000000
DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
A2W_XOSC_CPR_DIV_SET 0x00000003
SD_SECEND1_MASK 0xffffffff
CM_DSI1ECTL_FRAC_LSB 9
TB_JTB_CONFIG_TRSTN_MSB 14
EMMC_INTERRUPT_DMA_SET 0x00000008
MPHI_HSINDDB_TENDINT_BITS 29:29
PM_AUDIO_CTRLEN_BITS 20:20
GP_FSEL4_FSEL40_SET 0x00000007
A2W_PLLC_ANA_SSCS_MODE_SET 0x00010000
DMA3_TI_SRC_DREQ_BITS 10:10
DMA13_CS_PANIC_PRIORITY_BITS 23:20
A2W_PLLC_CORE2R_RESET 0x00000100
CM_UARTCTL_SRC_LSB 0
PWM_CTL_RPTL4_LSB 26
SLIM_DCC3_PA1_RESET 0000000000
A2W_PLLA_CCP2_MASK 0x000003ff
AVE_IN_STATUS_CURRENT_BUF_MSB 17
SCALER_DISPSTAT_DSP2_STATUS_CLR 0xc0ffffff
L1_D_CONTROL_DC1_FLUSH_MSB 2
SCALER_DISPCTRL_VSCL_DIS_LSB 30
UART_LCR_DTR_MSB 0
SD_PHYC_IOB_TMODE_CLR 0xffffefff
SYSAC_JPEG_PRIORITY_P_PRIORITY_BITS 7:4
DMA_ENABLE_EN8_MSB 8
APERF0_BW2_CTRL_LATHALT_RESET 0x0
APERF1_BW0_CTRL_LATHALT_SET 0x10000000
HDMI_AN0 0x7e902018:RW
HDMI_AN1 0x7e90201c:RW
EMMC_DBG_SEL_RESET 0000000000
DMA12_TI_PERMAP_BITS 20:16
HD_MAI_CTL_EMPTY_LSB 10
CM_GP0DIV_DIV_BITS 23:0
PWM_CTL_POLA3_BITS 20:20
GP_PUDCLK0_RESET 0000000000
PWM_FIF1_MASK 0xffffffff
USB_DCTL_GOUT_NAK_STS_SET 0x00000008
DMA8_DEBUG_LITE_CLR 0xefffffff
MPHI_MINFS 0x7e006038:RW
USB_DOEPTSIZ0_SUP_CNT_MSB 30
MPHI_C1INDDA_START_RESET 0x0
DMA5_TI_WAITS_MSB 25
A2W_PLLA_DIG1R_MASK 0x00ffffff
DMA5_CONBLK_AD_WIDTH 32
DMA2_CS_ACTIVE_LSB 0
MPHI_C1INDS_WORDS_MSB 20
AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_MSB 31
SD_SE_T_FAW_MSB 17
SD_DQLCRC6_FALL_MSB 15
CM_GP0DIV 0x7e101074:RW
ASB_ISP_S_CTRL_CLR_REQ_SET 0x00000001
DMA7_DEBUG_VERSION_LSB 25
DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
A2W_PLLD_ANA3R 0x7e10285c:RW
A2W_PLLH_CTRL_PDIV_CLR 0xffff8fff
L1_D_CONTROL_DC0_FLUSH_LSB 1
USB_GRXSTSP_HST_PKT_STS_RESET 0x0
CM_LOCK_FLOCKD_MSB 11
PIXELVALVE2_VERTB_WIDTH 32
A2W_PLLD_DIG1R_WIDTH 24
PWM_RNG2_WIDTH 32
EMMC_IRPT_EN_CARD_OUT_SET 0x00000080
GP_FSEL4_RESET 0000000000
TB_JTB_CONFIG_INV_CLK_SET 0x00000080
A2W_PLLH_ANA_SCTL_SEL_MSB 2
ASB_ISP_S_CTRL_EMPTY_CLR 0xfffffffb
USB_DOEPCTL0_SET_EVEN_FR_BITS 28:28
USB_GINTMSK_IEP_INT_SET 0x00040000
DMA6_DEBUG_OUTSTANDING_WRITES_MSB 7
CM_VECCTL_BUSYD_MSB 8
DMA13_TI_WIDTH 26
AVE_IN_STATUS_CAPTURING_MSB 31
A2W_PLLB_ANA_SCTLR 0x7e102df0:RW
DMA10_CS_RESET_SET 0x80000000
DMA12_TXFR_LEN_MASK 0x0000ffff
SMI_DSR3_RDREQ_SET 0x00000080
USB_GHWCFG4_EN_SESSIONEND_FILTER_RESET 0x0
SD_SECSRT0_ADDR_MS_BITS 31:13
SD_SE_RL_EN_LSB 28
SD_SECSRT2_ADDR_LS_CLR 0xffffe001
AVE_OUT_CR_COEFF_BLUE_COEFF_LSB 0
APERF1_BW1_WMAX_WIDTH 16
USB_HPRT_OVR_CURR_ACT_MSB 4
DMA7_DEBUG_DMA_ID_LSB 8
I2C_SPI_SLV_HCTRL_WIDTH 8
CM_EVENT_GAINB_MSB 1
IC1_MASK0_WIDTH 31
CM_DSI0PCTL_BUSY_LSB 7
DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
SD_DQRCRC10 0x7ee00134:RO
SD_DQRCRC11 0x7ee00138:RO
SD_DQRCRC12 0x7ee0013c:RO
SD_DQRCRC13 0x7ee00140:RO
SD_DQRCRC14 0x7ee00144:RO
AJB_HOLD0 0x000000
AJB_HOLD1 0x001000
AJB_HOLD2 0x002000
AJB_HOLD3 0x003000
MPHI_HSINDCF_HANDLE_RESET 0x0
CMLCD 0x7C:RW
DMA_INT_STATUS_INT5_CLR 0xffffffdf
DMA11_CONBLK_AD_RESET 0000000000
L1_IC1_CONTROL_DISABLE_MSB 0
CAM1_CAMCLT_WIDTH 32
DSI0_STAT_WIDTH 32
SH_HBCT_BYTECOUNT_MSB 31
USB_DIEPTSIZ0_XFERSIZE_CLR 0xfff80000
SD_DQLCRC7_RISE_CLR 0x0000ffff
EMMC_CMDTM_TM_AUTO_CMD_EN_LSB 2
SMI_DSR3_RPACE_BITS 14:8
DMA7_TI_BURST_LENGTH_MSB 15
TE_1TIMER_MASK 0xffffffff
SMI_CS_ACTIVE_SET 0x00000004
USB_GI2CCTL_ADDR_BITS 22:16
CCP2TX_TIC_TIIE_BITS 0:0
PM_WDOG_MASK 0x000fffff
HDMI_CEC_RX_DATA_2_RESET 0000000000
A2W_XOSC0R 0x7e102890:RW
CM_PULSECTL_FRAC_SET 0x00000200
PM_AVS_STAT_ALERT_ARM_P_CLR 0xffffffef
CM_GP1CTL_KILL_LSB 5
PCM_CS_A_TXON_CLR 0xfffffffb
FPGA_CTRL0_SPARE_OUT_CLR 0x000fffff
EMMC_INTERRUPT_SDOFF_ERR_BITS 23:23
HD_MAI_CTL_FULL_LSB 11
L2_L2_ALIAS_EXCEPTION_ID_RESET 0000000000
EMMC_HWCAP0_SDMA_MSB 22
SD_LAC_MASK 0x0fffffff
AUX_SPI_CNTL0_INRISE 0x00000400
GP_FSEL0_FSEL06_LSB 18
DMA10_DEBUG_VERSION_LSB 25
TB_BOOT_OPT_MASK 0x800007ff
SD_DQRCRC8_FALL_MSB 15
MS_SEMA_5_RESET 0000000000
CM_EVENT_BURSTDONE_CLR 0xff7fffff
FPGA_DCM_CTRL_PERI_WR_EN_LSB 28
DSI1_INT_EN_WIDTH 28
DMA9_CS_DISDEBUG_SET 0x20000000
A2W_PLLD_MULTI_MASK 0000000000
HDMI_CTS_0_WIDTH 20
A2W_PLLA_ANA_STAT_RESET 0000000000
APHY_CSR_DDR_PLL_POST_DIV_RESET 0x7ee06028:RW
CAM1_CAMIDI0_MASK 0xffffffff
DMA8_TI_WAIT_RESP_MSB 3
GRPSCC 0x1A005600 + 0x4C:RW
USB_GSNPSID 0x7e980040:RW
SMI_DSW2_WSETUP_SET 0x3f000000
HDMI_SCHEDULER_CONTROL_ALWS_VERT_KEEPOUT_SET 0x00000008
SMI_CS_INTR_SET 0x00000800
UART_LCR_RTS_CLR 0xfffffffd
USB_HCCHAR0_EP_TYPE_SET 0x000c0000
A2W_XOSC1R 0x7e102894:RW
USB_DIEPDMA13_WIDTH 32
DMA1_CS_PANIC_PRIORITY_MSB 23
UART_LSR_WIDTH 8
DMA0_TI_DEST_DREQ_SET 0x00000040
DMA3_CS_DREQ_STOPS_DMA_SET 0x00000020
HDMI_RAM_GCP_6_WIDTH 32
CM_INTEN_BURSTDONE_BITS 23:23
USB_GVBUSDRV 0x7e980088:RW
CM_TECCTL_RESET 0000000000
A2W_PLLD_PER 0x7e102540:RW
DMA0_DEBUG_MASK 0x1ffffff7
SMI_DC_DMAEN_CLR 0xefffffff
CM_DSI1PCTL_ENAB_LSB 4
DMA5_STRIDE_S_STRIDE_BITS 15:0
IC1_FORCE1 0x7e002844:RW
USB_DOEPDMA9_MASK 0xffffffff
L1_L1_SANDBOX_START7_CTRL_SET 0x00000001
SYSAC_PERI_ARBITER_CONTROL_DELAY_CLR 0xfffffff3
SLIM_DCC5_STAT 0x7e2102ac:RW
SD_VIN_ID_RESET 0x0
USB_DOEPINT0_OUT_TKN_EP_DIS_SET 0x00000010
EMMC_INTERRUPT_OEM_ERR_SET 0xc0000000
UNICAM_MISC(x) MACRO
EMMC_IRPT_EN_INT_B_BITS 10:10
HDMI_RAM_PACKET_12_4_WIDTH 32
MS_SEMA_28_MASK_LSB 0
CM_BURSTCNT_MASK 0x00ffffff
SCALER_DISPSTAT_DSP2_STATUS_BITS 29:24
CM_CCP2CTL_SRC_MSB 2
CM_INTEN_FLOSSA_SET 0x00004000
A2W_PLLH_ANA_SCTL_UPDATE_BITS 3:3
L2_RD_MISSES_MASK 0xffffffff
SD_DQRCRC9_RISE_CLR 0x0000ffff
DMA7_CS_ERROR_LSB 8
HDMI_SCHEDULER_CONTROL_IGN_VSYNC_PREDS_SET 0x00000020
USB_PCGCR_GATE_HCLK_BITS 1:1
DMA13_TI_SRC_DREQ_BITS 10:10
SD_DQLCRC2_FALL_BITS 15:0
SMI_DSR0_RDREQ_CLR 0xffffff7f
A2W_PLLC_PER_DIV_LSB 0
CM_TSENSCTL_FRAC_SET 0x00000200
DMA14_CS_PAUSED_BITS 4:4
USB_DTKNQR2_MASK 0xffffffff
DMA14_TI_DEST_DREQ_BITS 6:6
A2W_SMPS_L_SCAR_WIDTH 12
USB_HCTSIZ0_WIDTH 32
ARM_C0_JTAGOFF 0x00000000
CAM1_CAMIBWP_WIDTH 32
PM_IMAGE_H264RSTN_SET 0x00000080
SCALER_DISPSTAT_PROF_IRQ_CLR 0x00000000
A2W_PLLH_ANA_SCTL_RESET_BITS 4:4
A2W_SMPS_B_STAT_BSTPWMB_SET 0x00000100
USB_DCFG_PER_FR_INT_LSB 11
CM_PLLTCNT0_CNT_LSB 0
USB_GHWCFG4_EN_B_VALID_FILTER_BITS 23:23
L1_IC1_RAS_POPS_WIDTH 0
A2W_XOSC_BIAS_HIGHP_BITS 4:4
ASB_ISP_S_CTRL_MASK 0x00ffffff
HD_MAI_FMT_WIDTH 32
EMMC_HWCAP0_BUS64_LSB 28
L2_WR_MISSES 0x7ee0110c:RO
MPHI_C1INDDB_MORUN_CLR 0x7fffffff
CM_VPUDIV_MASK 0x00fffff0
PWM_CTL_POLA2_LSB 12
SCALER_DISPECTRL_Y_BUSY_SET 0xfffffe00
GP_FSEL3_WIDTH 30
APERF0_BW2_CTRL_BUS_LSB 0
I2C_SPI_SLV_RSR_OE_BITS 0:0
CCP2TX_TAC_PTATADJ_LSB 24
USB_GI2CCTL_RW_MSB 30
HDMI_SCHEDULER_CONTROL_VSYNC_PHYST_EN_LSB 17
HDMI_FIFO_CTL_RECENTER_DONE_CLR 0xffffbfff
CM_ARMDIV_DIV_SET 0x00001000
EMMC_CONTROL0_PWCTL_ON_BITS 8:8
A2W_PLLB_ANA_VCO_WIDTH 1
MPHI_C1INDDB_MASK 0xffffffff
HDMI_RAM_PACKET_10_3_RESET 0000000000
USB_HCCHAR0_MPS_LSB 0
SLIM_DMA_DC2_WIDTH 32
CM_GP0CTL_KILL_SET 0x00000020
I2C_SPI_SLV_IMSC_RXIM_SET 0x00000001
L1_IC0_CONTROL_ENABLE_STATS_MSB 2
APERF1_BW0_CTRL_WIDTH 32
MPHI_INTSTAT_HSTEND_BITS 31:31
TB_BOOT_OPT_ELPIDA_SET 0x00000010
CAM1_CAMMISC_RESET 0000000000
SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_RESET 0x0
PWM_STA_STA3_SET 0x00000800
APERF0_BW2_ATWAIT_MASK 0xffffffff
CM_TD1CTL_BUSY_CLR 0xffffff7f
A2W_PLLD_DSI1_BYPEN_MSB 9
A2W_PLLB_SP1_CHENB_MSB 8
PCM_RXC_A_CH2EN_SET 0x00004000
VCE_PC_RD0_OFFSET 0x40010
USB_DCFG_NZ_STS_OUT_HSHK_CLR 0xfffffffb
I2C1_FIFO 0x7e804010:RW
CCP2TX_TBA_ADDR_LSB 0
L2_CONT_OFF_l2_disable_LSB 0
CM_DSI0ECTL_KILL_LSB 5
USB_GHWCFG3_WIDTH 32
DMA11_TI_WIDTH 26
DMA2_DEBUG 0x7e007220:RW
DMA0_TI_NO_WIDE_BURSTS_SET 0x04000000
PIXELVALVE2_DSI_HACT_ACT_MASK 0x0000ffff
CCP2TX_TTC_ATX_CLR 0x7fffffff
USB_GHWCFG4_EN_PWROPT_LSB 4
DMA15_DEBUG_FIFO_ERROR_BITS 1:1
A2W_PLLB_DIG3R_RESET 0x00000004
GP_LEN1_LENn32_CLR 0x00000000
A2W_PLLC_CORE0_DIV_LSB 0
ASB_CPR_CTRL_CLR_ACK_SET 0x00000002
APERF0_BW1_AMAX_WIDTH 24
DMA13_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
DMA12_DEBUG_FIFO_ERROR_MSB 1
CM_EVENT_FLOSSB_BITS 15:15
PCM_INTSTC_A_RXERR_LSB 3
DPHY_CSR_CRC_CTRL 0x7ee07800:RW
MPHI_HSINDDB_HANDLE_RESET 0x0
VEC_WSE_VPS_CONTROL 0x7e8060d0:RW
EMMC_STATUS_DAT_LEVEL1_SET 0x1e000000
A2W_PLLH_ANA_VCO_RANGE_CLR 0xfffffffe
AUX_SPI_STAT_TXEMPTY 0x00000200
A2W_PLLD_DSI0_BYPEN_LSB 9
SPI_CLK_CDIV_BITS 15:0
SCALER_DISPGAMDAT_MASK 0xffffffff
A2W_PLLB_SP0_CHENB_LSB 8
TB_JTB_CONFIG_BUSY_LSB 31
DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
TB_TASK_MASK 0x0001ffff
EMMC_IRPT_MASK_DMA_ERR_MSB 28
EMMC_STATUS_NEW_WRITE_DATA_CLR 0xfffffbff
IDCCFG 0x10002014:RW
PM_SPAREW_RESET 0000000000
A2W_PLLB_SP1_DIV_BITS 7:0
DMA_INT_STATUS_INT8_LSB 8
USB_DOEPCTL1_WIDTH 32
USB_HCTSIZ0_PKT_CNT_BITS 28:19
DMA7_TI_DEST_WIDTH_CLR 0xffffffdf
SD_SECEND0_ADDR_MS_MSB 31
DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
PIXELVALVE0_VC_MASK 0x007fffff
HDMI_DETECTED_VERTB0_MANUAL_VBP0_CLR 0xfffffeff
USB_GRSTCTL_AHB_IDLE_SET 0x80000000
PM_GRAFX_ISFUNC_BITS 5:5
IC0_FORCE1_SET_RESET 0000000000
EMMC_IRPT_MASK_CEND_ERR_SET 0x00040000
ACISMODE 0x1C004800 + 0x10:RW
CM_DSI0ECTL_BUSY_LSB 7
A2W_PLLD_FRACR_RESET 0000000000
FPGA_CTRL0_WIDTH 36
MS_MBOX_2_MBOX_LSB 0
HDMI_CPU_SET_MASK 0xffffffff
SLIM_EA1_MASK 0x8000ffff
TB_JTB_CONFIG_SPEED_MSB 23
A2W_SMPS_LDO0R_WIDTH 24
PM_USB 0x7e10005c:RW
AVE_IN_STATUS_CURRENT_BUF_SET 0x00020000
TH0ITPC 0x18011000 + 0x0C:RW
SCALER_DISPCTRL_DSP0_PANIC_MSB 25
DSI0_CTRL_CTRL0_LSB 0
DMA10_TI_DEST_DREQ_SET 0x00000040
L1_D1_WR_SNOOPS_MASK 0000000000
AVE_IN_LINE_LENGTH_LINE_LENGTH_LSB 0
MPHI_C0INDCF_HANDLE_LSB 20
DMA4_DEBUG_LITE_BITS 28:28
USB_HCINT5_MASK 0xffffffff
GP_PUDCLK2_PUDCLKn64_BITS 5:0
MPHI_OUTDDB_TENDINT_LSB 29
PM_PADS0_SLEW_LSB 4
EMMC_CONTROL2_UHSMODE_MSB 18
AUX_SPI_CNTL0_OUTFALL 0x00000000
USB_GPVNDCTL_REG_DATA_LSB 0
USB_GINTMSK_SOF_BITS 3:3
DMA2_TI_BURST_LENGTH_CLR 0xffff0fff
A2W_PLLA_MULTI_MASK 0000000000
SMI_DSR2_RWIDTH_MSB 31
SMI_DSR0_RWIDTH_CLR 0x3fffffff
CM_PLLA_HOLDPER_CLR 0xffffff7f
DMA2_TI_DEST_IGNORE_CLR 0xffffff7f
A2W_PLLD_DSI0 0x7e102340:RW
A2W_PLLD_DSI1 0x7e102640:RW
DMA15_TI_NO_WIDE_BURSTS_MSB 26
CM_TDCLKEN_USBDFT_BITS 11:11
CM_PLLTCNT1_CNT_MSB 23
HDMI_CEC_RX_DATA_4_WIDTH 32
GP_FSEL4_FSEL45_MSB 17
PM_AVS_RSTDR_ROSC_MSB 5
TB_BOOT_OPT_FAST_OPT_LSB 0
UNICAM_CAP1(x) MACRO
USB_DIEPINT3_WIDTH 32
GP_FSEL6_FSEL66_CLR 0xffe3ffff
TB_BOOT_ADDR_WIDTH 32
CM_V3DCTL_BUSYD_BITS 8:8
CCP2TX_TSPARE 0x7e001028:RW
DMA0_TI_SRC_WIDTH_CLR 0xfffffdff
VEC_DAC_TEST_WIDTH 32
HDMI_HBR_AUDIO_PACKET_HEADER 0x7e902158:RW
MS_MBOX_1_MBOX_BITS 31:0
CM_VECDIV 0x7e1010fc:RW
APERF1_BW0_CTRL_LATHALT_RESET 0x0
DMA6_DEBUG_VERSION_MSB 27
PCM_GRAY_MASK 0x003ffff7
DMA0_NEXTCONBK_ADDR_CLR 0x0000001f
SMI_DSW1_WDREQ_CLR 0xffffff7f
DMA13_TXFR_LEN_XLENGTH_BITS 15:0
HDMI_RAM_PACKET_2_7_RESET 0000000000
A2W_SMPS_A_GAIN 0x7e1023a0:RW
DMA6_TI_DEST_INC_CLR 0xffffffef
MS_SEMA_12_RESET 0000000000
MS_SEMA_3_WIDTH 1
USB_HCSPLT0_WIDTH 32
ALIAS_NORMAL(x) MACRO
A2W_PLLB_SP1_BYPEN_CLR 0xfffffdff
A2W_PLLA_CORER 0x7e102c00:RW
CM_VPUCTL_SRC_CLR 0xfffffff0
DMA14_BASE 0x7e007e00
A2W_PLLH_CTRL_WIDTH 18
PM_PROC_ISPOW_LSB 2
SD_STALL_CYCLES_RESET 0x0
EMMC_CONTROL0_HCTL_DWIDTH_LSB 1
APERF1_BW2_WTWAIT_WIDTH 32
SD_TMC_TSTPAT_SET 0xffff0000
TE_2VSWIDTH_WIDTH 32
MPHI_C1INDS_VALID_SET 0x40000000
MPHI_C1INDCF_ORUN_BITS 29:29
USB_DIEPDMA11_MASK 0xffffffff
SMI_DSW2_WWIDTH_LSB 30
SMI_DSR3_RPACEALL_SET 0x00008000
ST_C0_MASK 0xffffffff
MS_VPU_STAT_VPU_STAT_MSB 0
DMA7_BASE 0x7e007700
DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
DMA10_DEST_AD_D_ADDR_CLR 0x00000000
SCALER_DISPCTRL_DSP2_IRQ_CTRL_BITS 12:11
TXP_CTRL_POWERDOWN_BITS 21:21
TS_TSENSCTL_THOLD_CLR 0xfffc00ff
APERF0_BW1_WTWAIT_WIDTH 32
EMMC_HWCAP1_DDR50_LSB 2
A2W_PLLC_CORE1_DIV_MSB 7
CM_ISPDIV_DIV_BITS 15:4
USB_GNPTXFSIZ_NP_TXF_ST_ADDR_RESET 0x0
GP_FSEL5_FSEL55_SET 0x00038000
FPGA_CTRL0_CAM_CTL1_SET 0x00000002
DMA8_SOURCE_AD_S_ADDR_CLR 0x00000000
DMA6_CONBLK_AD_WIDTH 32
AVE_IN_MAX_TRANSFER_MAX_TRANSFER_SET 0xffffffff
SCALER_DISPSTAT0 0x7e400048:RW
SCALER_DISPSTAT1 0x7e400058:RW
SCALER_DISPSTAT2 0x7e400068:RW
USB_DTHRCTL_ARB_PRK_EN_RESET 0x0
SLIM_DMA_DC8_MASK 0xffffffff
HDMI_CEC_TX_DATA_3_MASK 0xffffffff
DMA5_CS_PANIC_PRIORITY_MSB 23
CM_CAM0CTL_MASK 0x000003bf
PCM_RXC_A_CH1POS_SET 0x3ff00000
DMA7_CS_DREQ_STOPS_DMA_SET 0x00000020
SD_SECSRT0_ADDR_MS_SET 0xffffe000
DMA4_TI_DEST_DREQ_MSB 6
PM_AVS_STAT_ALERT_V3D_G_LSB 3
CM_PLLD_RESET 0x00000300
DMA_INT_STATUS_INT8_BITS 8:8
USB_DIEPCTL0_SET_ODD_FR_CLR 0xdfffffff
SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_SET 0x00000030
PRM_SCC_MASK 0xffffffff
SLIM_MC_OUT_STAT 0x7e210124:RW
I2C_SPI_SLV_IFLS_RXIFLSEL_MSB 5
PCM_MODE_A_FSI_BITS 20:20
APERF1_BW1_AMAX 0x7ee0808c:RO
A2W_PLLH_PIX_DIV_CLR 0xffffff00
FPGA_CTRL0_MASK 0xfffff3fff
AVE_IN_CTRL_HSYNC_IRQ_EN_MSB 5
HDMI_PERT_LFSR_FEEDBACK_MASK_MASK 0xffffffff
TB_HDMI_MASK 0xffffffff
USB_DIEPDMAB8_WIDTH 32
DMA1_CS_ACTIVE_MSB 0
EMMC_HWCAP0_MAXLEN_BITS 17:16
DMA15_CS_END_LSB 1
EMMC_CONTROL0_WAKE_ONINS_EN_SET 0x02000000
A2W_PLLB_ANA0R_RESET 0000000000
EMMC_IRPT_MASK_BLOCK_GAP_CLR 0xfffffffb
MPHI_MOUTFS_WPTR_CLR 0xfff003ff
EMMC_DATA_WIDTH 32
DMA12_TI_SRC_WIDTH_LSB 9
DMA10_TXFR_LEN_XLENGTH_LSB 0
CM_GNRICCTL_BUSY_LSB 7
DPHY_CSR_BYTE0_SLAVE_DLL_OFFSET 0x7ee0701c:RW
DMA_INT_STATUS_RESET 0000000000
DMA13_DEBUG_FIFO_ERROR_SET 0x00000002
SD_CS_EXCEPTION_LSB 23
MPHI_C0INDFS_DFIFOLVL_LSB 0
I2C1_CLKT_WIDTH 16
TB_BOOT_OPT_BANK_MODE_SET 0x00000300
FPGA_MB_XPERI_BUILD_NUM_MASK 0xffffffff
DMA12_CONBLK_AD_RESET 0000000000
DMA13_CS_INT_SET 0x00000004
SD_VIN_CLEAR_CLR 0x7fffffff
HD_VID_CTL_CLRRGB_MSB 23
APERF1_BW2_RMAX_RESET 0000000000
EMMC_IRPT_EN_DATA_DONE_SET 0x00000002
SPI_CLK_WIDTH 16
DMA5_TI_BURST_LENGTH_BITS 15:12
CM_LOCK_LOCKC_SET 0x00000004
CM_GNRICCTL_BUSYD_SET 0x00000100
USB_HPRT_RES_MSB 6
CAM0_CAMDCS_WIDTH 32
DMA14_TI_SRC_DREQ_SET 0x00000400
HDMI_RAM_PACKET_10_1_WIDTH 32
SMI_DSW2_WPACEALL_CLR 0xffff7fff
V3D_DBCFG_WIDTH 32
GP_FSEL4_FSEL41_LSB 3
DMA15_DEBUG_WIDTH 29
USB_HCINT_off(n) MACRO
CM_VECCTL_SRC_CLR 0xfffffff0
CM_DFTCTL_SRC_MSB 3
DMA15_TI_BURST_LENGTH_MSB 15
GP_GPTEST_SMPS_CLR 0xfffffffe
DMA11_CS_PAUSED_BITS 4:4
CM_H264CTL_KILL_SET 0x00000020
PCM_CS_A_RXR_SET 0x00040000
A2W_HDMI_CTL2R_MASK 0x00ffffff
USB_GI2CCTL_DAT_SE0_SET 0x10000000
ARM_T_CONTROL 0x7E00B000 +0x408:RW
A2W_HDMI_CTL_HFENR_MASK 0x00000001
HDMI_RAM_GCP_0_RESET 0000000000
PIXELVALVE0_APB_ID 0x70697876
CM_ISPCTL_MASK 0x000003ff
A2W_PLLA_CCP2R 0x7e102e00:RW
USB_DIEPINT0_STS_PHSE_RCVD_RESET 0x0
SD_CS_STATEN_LSB 6
CM_PCMCTL_KILL_BITS 5:5
USB_GINTMSK_ISO_OUT_DROP_MSB 14
SD_DQLCRC0_FALL_CLR 0xffff0000
CM_PLLD_ANARST_SET 0x00000100
AUX_MU_CNTL_AUTO_CTS 0x08
A2W_PLLB_SP2_RESET 0x00000100
SD_SE_RL_LSB 20
V3D_CT1CA_WIDTH 32
I2C1_DLEN_RESET 0000000000
SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_RESET 0x0
PCM_TXC_A_CH1POS_BITS 29:20
A2W_PLLC_CORE2_CHENB_BITS 8:8
AVE_IN_CTRL_LINE_IRQ_EN_SET 0x00000010
CM_V3DDIV_DIV_SET 0x0000fff0
DSI0_HS_CLT2_WIDTH 10
PWM_DMAC_ENAB_SET 0x80000000
PCM_CS_A_TXD_SET 0x00080000
SD_DQRCRC15_RISE_SET 0xffff0000
SLIM_DCC1_PROT 0x7e210230:RW
GP_HEN1_HENn32_SET 0xffffffff
A2W_PLLA_CCP2_CHENB_MSB 8
CM_GP1CTL_ENAB_BITS 4:4
SMI_D_RESET 0000000000
V3D_IDENT0_WIDTH 32
USB_GPVNDCTL_STS_BSY_CLR 0xfbffffff
USB_HCSPLT0_HUB_ADDR_SET 0x00003f80
GP_LEN0_LENn0_MSB 31
DMA4_TI_NO_WIDE_BURSTS_SET 0x04000000
TS_TSENSSTAT_INTERUPT_MSB 11
A2W_PLLC_ANA_KAIP_KI_BITS 6:4
DMA2_CS_RESET_SET 0x80000000
V3D_ERRSTAT_MASK 0xffffffff
I2C_SPI_SLV_ICR_OEIC_BITS 3:3
TRANSPOSER_DIMENSIONS 0x7e004008:RW
PCM_GRAY_CLR_BITS 1:1
DMA12_CS_ABORT_SET 0x40000000
CAM0_CAMIDPO_RESET 0000000000
PCM_TXC_A_CH2WID_SET 0x0000000f
A2W_PLLA_ANA_KAIP_KP_CLR 0xfffffff0
CCP2RC0 CCP2_BASE_ADDRESS + 0x100:RW
CCP2RC1 CCP2_BASE_ADDRESS + 0x200:RW
UART_MSR_CTS_CLR 0xffffffef
SD_SECEND2_ADDR_LS_LSB 0
USB_GUSBCFG_FORCE_HST_MODE_RESET 0x0
DMA2_TI_DEST_WIDTH_BITS 5:5
CAM0_CAMIHSTA_MASK 0xffffffff
PM_PADS3_DRIVE_BITS 2:0
MS_SEMA_4_MASK_SET 0x00000001
PM_GRAFX_CFG_CLR 0xff80ffff
USB_GHWCFG2_MODE_RESET 0x0
MPHI_HSINDDA_MASK 0xffffffff
SDRAM_BASE_ADDRESS 0x7ee00000
CM_INTEN_GAINH_LSB 4
MS_ICSET_1_WIDTH 1
USB_DOEPINT0_SETUP_LSB 3
DMA9_DEBUG_LITE_MSB 28
CM_TECCTL_BUSY_SET 0x00000080
SD_VIN_SPLIT_BITS 17:17
CM_TD1CTL_FLIP_LSB 11
HDMI_RAM_PACKET_11_3_RESET 0000000000
USB_DIEPDMA9_MASK 0xffffffff
A2W_SMPS_CTLA2R_MASK 0x00ffffff
SH_TOUT_TIME_OUT_SET 0xffffffff
SD_DQLCRC13_RISE_LSB 16
GP_HEN1_WIDTH 32
CM_DSI0ECTL_BUSY_BITS 7:7
PWM_DMAC_MASK 0x8000ffff
HDMI_VERTB0_MANUAL_VSPO0_LSB 9
A2W_PLLC_CORE1_MASK 0x000003ff
EMMC_INTERRUPT_CMD_DONE_SET 0x00000001
USB_HCSPLT7_MASK 0xffffffff
STC0_1 0xffffffff:RW
USB_DOEPCTL0_TXF_NUM_CLR 0xfc3fffff
EMMC_DBG_SEL_SELECT_SET 0x00000001
MPHI_TXAXICFG_TXNPRIO_MSB 3
CM_SYSDIV_MASK 0x00001000
SD_DQRCRC2_FALL_CLR 0xffff0000
CM_DSI1PCTL 0x7e101160:RW
APERF1_BW0_CTRL_EN_BITS 30:30
GR_FBC_BASE 0x1A005400
L1_D_PRIORITY_c0_l2_priority_SET 0x0000000f
DMA4_CS_PAUSED_BITS 4:4
CMI_CAMTEST 0x7e802008:RW
HDMI_HORZA_MANUAL_HAP_CLR 0xffffe000
CM_SDCDIV_MASK 0x0003f000
CM_LOCK_LOCKD_CLR 0xfffffff7
I2C_SPI_SLV_RSR_TXDMAPREQ_SET 0x00000004
SMI_DSR3_RPACE_MSB 14
IC1_FORCE0_CLR_WIDTH 32
EMMC_IRPT_EN_INT_A_MSB 9
DMA14_TI_DEST_DREQ_MSB 6
ARM_IF_VCMASK 0x0000003F
HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT_LSB 15
SYSAC_JPEG_PRIORITY_P_PRIORITY_MSB 7
SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_BITS 7:6
USB_GINTMSK_EP_MIS_RESET 0x0
SMI_CS_TEEN_CLR 0xfffffeff
IC0_MASK5_MASK 0x77777777
USB_DTHRCTL_ARB_PRK_EN_CLR 0xf7ffffff
USB_HCCHAR4_MASK 0xffffffff
SMI_DSR0_RPACEALL_LSB 15
CCP2TX_TTC_LCN_BITS 3:0
MPHI_C1INDFS_CFIFOLVL_LSB 16
DMA14_CS_DISDEBUG_MSB 29
CCP2RSA0 CCP2_BASE_ADDRESS + 0x10C:RW
MS_SEMA_10_WIDTH 1
USB_GINTMSK_EOPF_CLR 0xffff7fff
CM_PLLC_ANARST_BITS 8:8
CAM0_CAMIPIPE 0x7e80010c:RW
PWM_CTL_SBIT1_LSB 3
INT_CTL_BASE_ADDR1 0xffffffff:RW
PM_PADS0_DRIVE_CLR 0xfffffff8
CM_CAM1CTL_SRC_SET 0x0000000f
A2W_PLLC_DIG0R_RESET 0000000000
USB_HCINT0_ACK_LSB 5
SCALER_DISPECTRL_BUSY_STATUS_MSB 31
CM_GNRICCTL_KILL_MSB 5
MS_SEMA_16_MASK_CLR 0xfffffffe
USB_HCSPLT0_SPLT_ENA_MSB 31
APERF1_BW2_CTRL_MASK 0xf0001f1f
PM_DSI0_LDOLPEN_BITS 1:1
CCP2TX_TS_TII_LSB 17
SMI_DSR2_RPACE_LSB 8
DMA8_DEBUG_VERSION_MSB 27
HDMI_RAM_PACKET_6_8_RESET 0000000000
HDMI_FIFO_CTL_USE_PLL_LOCK_MSB 4
HDMI_FIFO_CTL 0x7e90205c:RW
MS_IREQ_0_IREQ_0_SET 0xffffffff
GR_TU_ADDR_MASK 0x000000FF
HDCP_KEY_CTL_DONE_SET 0x00000002
CAM0_CAMDAT3_RESET 0x00000002
DSI0_PHYC_clane_hsen_sync_MSB 8
A2W_HDMI_CTL_RCAL_RSTB_BITS 16:16
CAM0_CAMSTA_RESET 0000000000
A2W_PLLA_CCP2_BYPEN_CLR 0xfffffdff
PCM_MODE_A_FSLEN_MSB 9
HD_CSC_CTL 0x7e808040:RW
APERF0_BW2_WTWAIT_RESET 0000000000
PWM_STA_GAPO1_CLR 0xffffffef
TXP_CTRL_ALPHA_INVERT_BITS 12:12
PIXELVALVE0_INTEN_WIDTH 10
V3D_DBQGHH_WIDTH 32
EMMC_IRPT_MASK_CARD_OUT_CLR 0xffffff7f
SMI_CS_TXW_SET 0x04000000
GP_FSEL1_FSEL14_CLR 0xffff8fff
CM_ISPCTL 0x7e101030:RW
DMA8_CS_DREQ_CLR 0xfffffff7
SCALER_DISPCTRL_TILE_WID_MSB 17
A2W_PLLB_ARM_DIV_SET 0x000000ff
I2C_SPI_SLV_DR_TXFE_MSB 20
ARM_0_MAIL1_STA (0x7E00B000 +0x800)+0xB8:RW
SLIM_EA1_WIDTH 32
AVE_IN_CTRL_BYTE_ORDER_MSB 13
MPHI_C1INDCF_MTERM_CLR 0xefffffff
HDMI_RAM_PACKET_13_1_MASK 0xffffffff
CM_PLLB_WIDTH 10
A2W_PLLH_ANA1R_RESET 0x00000014
USB_HCCHAR0_CH_ENA_SET 0x80000000
A2W_XOSC_CTRL_USBOK_BITS 14:14
APERF0_BW1_WTRANS_MASK 0xffffffff
A2W_PLLH_DIG0R 0x7e102860:RW
SYSAC_UC_ARBITER_CONTROL_LIMIT_MSB 1
EMMC_CONTROL2_TUNED_MSB 23
DMA3_STRIDE_D_STRIDE_MSB 31
DMA2_TI_WAITS_CLR 0xfc1fffff
I2C2_C_RESET 0000000000
I2CA 0x7e205000 + 0x0C:RW
I2CC 0x7e205000 + 0x00:RW
AVE_IN_LINE_NUM_INT_LINE_NUM_INT_SET 0x00000fff
USB_DOEPCTL6_MASK 0xffffffff
DMA9_CS_PANIC_PRIORITY_MSB 23
AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_SET 0xffffffff
HD_MAI_THR_PANICHIGH_LSB 24
I2CS 0x7e205000 + 0x04:RW
DSI0_INT_STAT 0x7e209024:RW
A2W_PLLB_CTRL_RESET 0x00010000
A2W_PLLC_ANA3_RESET 0x00000180
MPHI_C0INDDB_HANDLE_BITS 27:20
MPHI_C1INDCF_HANDLE_LSB 20
DMA5_DEBUG_LITE_BITS 28:28
PCM_WID2(x) MACRO
CM_INTEN_GAINA_CLR 0xfffffffe
DMA12_TI_INTEN_SET 0x00000001
MPHI_MOUTFS_WPTR_BITS 19:10
A2W_PLLH_DIG1R 0x7e102864:RW
SMI_DSR2_RWIDTH_SET 0xc0000000
ASB_H264_M_CTRL_CLR_REQ_CLR 0xfffffffe
ASB_ISP_S_CTRL_RESET 0x00000007
HD_VID_CTL_BLANKPIX_CLR 0xfffbffff
DMA9_CS_INT_SET 0x00000004
EMMC_IRPT_MASK_INT_B_BITS 10:10
CM_PLLA_ANARST_SET 0x00000100
SPI_CS_TXD_CLR 0xfffbffff
USB_DIEPCTL0_TYPE_BITS 19:18
USB_DIEPCTL0_SNP_LSB 20
HDMI_CPU_MASK_CLEAR_MASK 0xffffffff
DMA5_CS_PAUSED_SET 0x00000010
GP_FSEL0_FSEL03_SET 0x00000e00
AVE_OUT_OFFSET_GREEN_OFFSET_CLR 0xffff00ff
L1_D0_WR_SNOOPS_WIDTH 0
DMA10_TI_BURST_LENGTH_CLR 0xffff0fff
SYSAC_H264_PRIORITY_PRIORITY_CLR 0xfffffff0
USB_GHWCFG3_DFIFO_DEPTH_CLR 0x0000ffff
TB_TASK_PARAM1_WIDTH 32
CM_OTPCTL_ENAB_MSB 4
PIXELVALVE2_INTSTAT_WIDTH 10
PWM_STA_STA4_LSB 12
EMMC_TUNE_STEP_DELAY_CLR 0xfffffff8
SD_DQLCRC10_RISE_CLR 0x0000ffff
JP_MWDATA 0x7e005034:RW
SD_DQLCRC7_FALL_CLR 0xffff0000
USB_HCCHAR0_EP_TYPE_RESET 0x0
APERF1_BW1_WTWAIT_MASK 0xffffffff
CM_PLLC_HOLDCORE2_BITS 5:5
CM_CAM0CTL_BUSYD_CLR 0xfffffeff
L1_L1_SANDBOX_START6_WIDTH 30
PCMDREQ PCM_BASE_ADDRESS + 0x14:RW
CSI2_RDEA_x(x) MACRO
TXP_CTRL_DITHER_MSB 13
SYSAC_USB_PRIORITY_PRIORITY_MSB 3
DMA0_TI_DEST_INC_SET 0x00000010
V3D_CT0EA_MASK 0xffffffff
ASB_ISP_M_CTRL_WCOUNT_MSB 23
FPGA_DCM_WR_DATA_DATA_MSB 15
CM_SMICTL_BUSY_CLR 0xffffff7f
DMA7_TI_DEST_INC_CLR 0xffffffef
SD_SECSRT3_EN_LSB 0
DSI0_STAT_MASK 0xffffffff
ASB_AXI_BRDG_VERSION_WIDTH 8
USB_GINTMSK_EP_MIS_LSB 17
MPHI_TXAXICFG_INTHRESH_CLR 0xfffe00ff
CM_VECCTL_WIDTH 10
DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
DMA_ENABLE_EN1_SET 0x00000002
DMA3_TI_TDMODE_BITS 1:1
APERF0_BW0_RTWAIT 0x7e009860:RO
DMA6_TI_DEST_DREQ_CLR 0xffffffbf
USB_HCDMA4_MASK 0xffffffff
CM_TCNTCTL_RESET 0000000000
HDMI_READ_POINTERS_DRFT_EMPTY_MINUS_MSB 17
SCALER_DISPSTAT_DMA_ERR_BIT1_LSB 15
A2W_SMPS_C_CTL_CTRLEN_LSB 0
CM_SLIMCTL_BUSYD_MSB 8
HDMI_RAM_GCP_0 0x7e902400:RW
HDMI_RAM_GCP_1 0x7e902404:RW
UART_LCR_SP_MSB 5
HDMI_RAM_GCP_3 0x7e90240c:RW
HDMI_RAM_GCP_4 0x7e902410:RW
HDMI_RAM_GCP_5 0x7e902414:RW
HDMI_RAM_GCP_6 0x7e902418:RW
ASB_CPR_CTRL_MASK 0x00ffffff
HDMI_RAM_GCP_8 0x7e902420:RW
CMUARTF 0x7C:RW
USB_DAINT_IN_EP_INT_SET 0x0000ffff
TXP_DST_PITCH 0x7e004004:RW
PWM_BASE_ADDRESS 0x7e20c000
CM_UARTDIV_DIV_MSB 21
HDMI_SCHEDULER_CONTROL_MODE_REQ_MSB 0
DMA11_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
SD_SC_T_RRD_RESET 0x4
CM_CCP2CTL_BUSYD_CLR 0xfffffeff
AJB_IN_RISE 0x000400
USB_GHWCFG3_PACKET_COUNT_WIDTH_RESET 0x0
SMI_FD_FLVL_CLR 0xffffc0ff
SD_DQLCRC11_FALL_BITS 15:0
A2W_PLLH_ANA_KAIP_RESET 0x0000033a
DMA7_CONBLK_AD_WIDTH 32
USB_DOEPINT14_WIDTH 32
A2W_PLLC_PER_MASK 0x000003ff
MPHI_MOUTFS_LEVEL_SET 0x000003ff
A2W_PLLH_FRAC_FRAC_SET 0x000fffff
PM_GRAFX_ISFUNC_CLR 0xffffffdf
EMMC_CMDTM_TM_MULTI_BLOCK_CLR 0xffffffdf
VCE_DATA_MEM_BASE 0x7f000000 + 0x100000:RW
CM_PLLD_DIGRST_BITS 9:9
PIXELVALVE1_DSI_HACT_ACT 0x7e207030:RW
A2W_PLLB_CTRL_WIDTH 18
TH0T0PC 0x18011000 + 0x10:RW
VEC_STATUS0_WIDTH 32
USB_GINTMSK_DISCONN_INT_LSB 29
DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
CM_PLLD_HOLDCORE_BITS 5:5
MPHI_INTSTAT_HSDCFOFLW_SET 0x08000000
SLIM_MC_OUT_CON 0x7e210120:RW
SH_HBLC_BLOCKCOUNT_CLR 0xfffffe00
APERF1_BW1_CTRL_BUS_CLR 0xffffffe0
SMI_CS_EDREQ_CLR 0xffff7fff
A2W_PLLB_ARM 0x7e1023e0:RW
CM_CCP2CTL_ENAB_MSB 4
CM_H264CTL_BUSYD_CLR 0xfffffeff
DMA2_TXFR_LEN_XLENGTH_CLR 0xffff0000
SD_DQRCRC11_RISE_MSB 31
DMA10_DEBUG_READ_ERROR_CLR 0xfffffffb
SD_DQRCRC9_FALL_CLR 0xffff0000
PCM_CS_A_STBY_CLR 0xfdffffff
EMMC_INTERRUPT_CARD_IN_SET 0x00000040
DMA11_SOURCE_AD_MASK 0xffffffff
TXP_XTRA_MASK 0x00000001
SD_DQLCRC12_MASK 0xffffffff
USB_GRSTCTL_RXF_FLSH_MSB 4
CAM0_CAMIBLS_WIDTH 32
ASB_ISP_M_CTRL_RCOUNT_SET 0x00003ff0
PCM_TXC_A_CH1POS_CLR 0xc00fffff
USB_GHWCFG2_ARCHITECTURE_SET 0x00000018
EMMC_INTERRUPT_CARD_SET 0x00000100
I2C1_BASE 0x7e804000
PWM_CTL_PWEN4_SET 0x01000000
PCMCS_TXTHR_FULL (3 << 5)
A2W_PLLD_ANA2R_WIDTH 24
EMMC_FORCE_IRPT_READ_RDY_SET 0x00000020
DSI1_TXPKT_PIXD_FIFO 0x7e700020:RW
CM_EMMCCTL_ENAB_LSB 4
CM_EVENT_LOSSH_MSB 9
CM_HSMCTL_ENAB_SET 0x00000010
DMA13_CONBLK_AD_RESET 0000000000
GP_LEV2_LEVn64_BITS 5:0
FPGA_DCM_CTRL_PERI_WR_EN_MSB 31
HDMI_RAM_PACKET_3_2_MASK 0xffffffff
EMMC_HWCAP1_DRV18_TYPEC_CLR 0xffffffdf
APERF1_BW0_RTRANS_RESET 0000000000
SMI_DSW1_WPACEALL_BITS 15:15
SMI_DSW3_WSWAP_SET 0x00400000
PM_RSTC_WIDTH 22
DMA0_CS_RESET_LSB 31
USB_DSTS_ENUM_SPD_SET 0x00000006
PCM_TXC_A_CH2EN_CLR 0xffffbfff
PM_PADS6_POWOK_BITS 5:5
DMA_ENABLE_EN2_BITS 2:2
USB_DCFG_EP_MIS_CNT_MSB 22
VPU_ARB_CTRL_UC_THRESHOLD_LSB 4
SMI_DCS_WIDTH 4
EMMC_HWCAP1_SDR104_MSB 1
MS_SEMA_16_MASK 0x00000001
FPGA_MB_SDC_V3D_FREQ_WIDTH 32
CM_AVEOCTL_RESET 0000000000
DMA5_TI_PERMAP_SET 0x001f0000
DMA4_STRIDE_D_STRIDE_CLR 0x0000ffff
DMA12_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
AVE_IN_STATUS_OVERRUN_CNT_SET 0x1f000000
ASB_ISP_M_CTRL_FULL_CLR 0xfffffff7
USB_GI2CCTL 0x7e980030:RW
HDMI_DETECTED_VERTB1_MANUAL_VBP1_LSB 8
ASB_CPR_CTRL_WCOUNT_LSB 14
SD_SC_T_WR_MSB 11
HDMI_PERT_DATA_RESET 0000000000
HDMI_TX_PHY_TX_PHY_RESET_CTL 0x7e9022c0:RW
L1_IC1_PRIORITY_IC1_APRIORITY1_BITS 7:4
CCP2TX_TIC_TEIE_SET 0x00000002
USB_HCDMA4_WIDTH 32
A2W_SMPS_A_VOLTS_VOLTS_CLR 0xffffffe0
CM_HSMCTL_SRC_MSB 3
HDMI_RAM_PACKET_4_1_MASK 0xffffffff
HD_VID_CTL_EMPSYNC_BITS 20:20
DMA15_CS_PAUSED_MSB 4
SPI_RX_DMA ( 7*(1<<16))
GP_FSEL5_FSEL56_LSB 18
HDMI_RAM_PACKET_6_6_WIDTH 32
EMMC_RESP0_RESET 0000000000
SLIM_MC_OUT_STAT_MASK 0x00000008
A2W_PLLC_CORE2_BYPEN_MSB 9
DSI0_PHYC_dlane_hsen_0_sync_MSB 0
VCE_REASON_RESET 0x12
SCALER_DISPSTAT_DSP0_STATUS_MSB 13
DMA5_DEBUG_LITE_CLR 0xefffffff
PCM_MODE_A_FLEN_BITS 19:10
CAM0_CAMDAT1_WIDTH 32
SLIM_DCC9_PA1_MASK 0x00ffff3f
DMA13_DEBUG_LITE_CLR 0xefffffff
DMA_CS_PANIC_PRIORITY (1<<20)
MPHI_C0INDDB_HANDLE_CLR 0xf00fffff
I2C2_CLKT_MASK 0x0000ffff
PCM_CS_A_RXERR_MSB 16
SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_LSB 2
DMA4_DEBUG_DMA_STATE_MSB 24
I2CFIFO_0 0x7e205000 + 0x10:RW
DMA4_CS_DISDEBUG_BITS 29:29
USB_GHWCFG3_RM_OPT_FEATURES_SET 0x00000400
PM_GNRIC_ISFUNC_MSB 5
HDMI_MAI_CONFIG_RESET 0x00000003
DMA9_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
IC0_MASK6_MASK 0x77777777
HDMI_RAM_PACKET_2_8_WIDTH 32
USB_GAHBCFG_NP_TXF_EMP_LVL_LSB 7
GP_SET0_SETn0_BITS 31:0
CM_DSI0PDIV_DIV_SET 0x00001000
DSI1_TXPKT_PIXD_FIFO_WIDTH 32
SCALER_DISPSLAVE0 0x7e4000c0:RW
SCALER_DISPSLAVE1 0x7e4000c8:RW
SCALER_DISPSLAVE2 0x7e4000d0:RW
AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_LSB 14
MPHI_HSINDDB_HANDLE_SET 0x0ff00000
EMMC_CONTROL0_HCTL_DWIDTH_BITS 1:1
I2CFIFO_2 0x7e805000 + 0x10:RW
A2W_PLLA_DIG0R_WIDTH 24
DMA6_CS_INT_SET 0x00000004
EMMC_IRPT_MASK_CARD_SET 0x00000100
A2W_PLLA_ANA_SSCLR_WIDTH 17
PM_PADS6_DRIVE_MSB 1
A2W_PLLC_CORE1_BYPEN_LSB 9
SD_SD_T_RPpb_LSB 4
USB_GINTMSK_DISCONN_INT_BITS 29:29
SD_DAT_MASK 0x0fffffff
HDMI_RAM_PACKET_8_3_RESET 0000000000
I2CS_TA (1 << 0)
L1_L1_SANDBOX_START2_CTRL_MSB 0
DMA1_DEBUG_VERSION_CLR 0xf1ffffff
MPHI_C0INDFS_CFIFOLVL_MSB 31
SMI_DSR3_RPACEALL_LSB 15
EMMC_IRPT_EN_WRITE_RDY_MSB 4
CM_ARMCTL_AXIHALF_CLR 0xffffefff
PM_CAM1_LDOLPEN_SET 0x00000002
I2C2_A_WIDTH 7
CAM1_CAMCMP1_RESET 0000000000
A2W_PLLA_PER_DIV_CLR 0xffffff00
VEC_CPS89_CPS1011_WIDTH 32
A2W_PLLB_SP2_BYPEN_SET 0x00000200
CCP2TX_TIC_TEIE_BITS 1:1
USB_GINTMSK_GIN_N_NAK_EFF_MSB 6
CAM0_CAMDBSA0 0x7e800204:RW
CAM0_CAMDBSA1 0x7e800310:RW
USB_DTXFSTS10_WIDTH 32
PM_XOSC 0x7e100070:RW
SMI_CS_PRDY_BITS 24:24
DMA_TI_WAIT_RESP (1<<3)
DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
PM_PROC_MEMREP_BITS 3:3
PM_PADS5_I2CMODE_LSB 6
DMA2_STRIDE_S_STRIDE_CLR 0xffff0000
CM_GP0CTL_ENAB_BITS 4:4
DMA10_CS 0x7e007a00:RW
HDMI_FIFO_CTL_ON_VB_DONE_SET 0x00008000
EMMC_INTERRUPT_DMA_ERR_CLR 0xefffffff
APERF0_BW0_CTRL_RESET_MSB 31
AVE_IN_BUF0_ADDRESS_BUF0_ADDR_BITS 31:0
APERF1_BW1_RTRANS_WIDTH 32
CM_PCMCTL_BUSY_SET 0x00000080
DMA_TI_S_WIDTH (1<<9)
APERF1_BW1_RMAX 0x7ee080a4:RO
SD_DQLCRC4_MASK 0xffffffff
I2C_SPI_SLV_CR_SPI_CLR 0xfffffffd
I2C_SPI_SLV_RIS_RXRIS_MSB 0
DMA14_DEBUG_LITE_MSB 28
ASB_ISP_M_CTRL_CLR_ACK_CLR 0xfffffffd
CM_CCP2CTL_BUSY_SET 0x00000080
AVE_OUT_CTRL_INTERLEAVE_MSB 12
USB_DIEPCTL0_DPID_CLR 0xfffeffff
SLIM_DCC8_PA0_WIDTH 24
GP_AJBCONF_MASK 0x80ffffff
TS_TSENSCTL_CLR_INT_BITS 7:7
H264_BASE 0x7f000000
HDMI_DETECTED_HORZA_MANUAL_VPOL_SET 0x00004000
L1_D_PRIORITY_c1_l2_priority_SET 0x000f0000
DMA15_CS_ACTIVE_SET 0x00000001
ASB_ISP_S_CTRL_WCOUNT_LSB 14
CM_V3DCTL_SRC_LSB 0
APERF0_BW2_CTRL_ID_LSB 8
CM_EVENT_LOSSD_LSB 8
CM_CCP2CTL_SRC_BITS 2:0
PM_SPARER_SPARE_CLR 0xff000000
CM_TCNTCNT_WIDTH 24
A2W_XOSC_BIASR 0x7e102b90:RW
CMI_CAM0_RX0SRC_LSB 2
DMA4_CS_RESET 0000000000
USB_GUSBCFG_IND_PASS_THRU_MSB 24
SYSAC_SRC_ARBITER_CONTROL_RESET 0000000000
DMA15_SOURCE_AD_MASK 0xffffffff
DMA6_DEST_AD_WIDTH 32
DMA2_TI_PERMAP_BITS 20:16
PCM_MODE_A_FTXP_SET 0x01000000
USB_DOEPTSIZ1_MASK 0xffffffff
USB_HPRT_PWR_CLR 0xffffefff
FPGA_CTRL0_SPI0_SEL_B_LSB 12
USB_GHWCFG2_EN_PERIO_HOST_BITS 18:18
CCP2TX_TIC_TQIE_LSB 2
DSI1_RXPKT2_H_WIDTH 32
PCM_GRAY_FLUSH_MSB 2
USB_GINTMSK_CUR_MOD_SET 0x00000001
APERF1_BW0_CTRL_ID_EN_LSB 29
HDMI_RAM_PACKET_11_8_MASK 0xffffffff
CM_VECCTL_BUSY_SET 0x00000080
EMMC_IRPT_MASK_RETUNE_MSB 12
SD_RWC_MARGIN_MSB 23
CM_DESCRIPTION "Clock manager"
PCM_CS_A_TXE_LSB 21
UART_MSR_DSR_LSB 5
AVE_OUT_Y_COEFF_GREEN_COEFF_LSB 10
A2W_PLLH_ANA_SCTLR_MASK 0x0000001f
SD_CS_STBY_RESET 0x0
SMI_DSR1_RHOLD_CLR 0xffc0ffff
CM_V3DCTL_ENAB_CLR 0xffffffef
HDMI_FIFO_CTL_USE_PLL_LOCK_BITS 4:4
DMA3_CS_DISDEBUG_MSB 29
SLIM_MC_IN_CON_WIDTH 12
CSI2_RLS_x(x) MACRO
MS_SEMA_22_MASK_BITS 0:0
DMA10_TI_INTEN_LSB 0
DMA10_DEST_AD 0x7e007a10:RO
EMMC_IRPT_MASK_READ_RDY_LSB 5
TXP_DIM_HEIGHT_BITS 27:16
CM_TD1CTL_KILL_SET 0x00000020
USB_GNPTXFSIZ_WIDTH 32
CM_SMICTL_SRC_MSB 3
A2W_SMPS_L_SIAR_MASK 0x000003ff
SH_HCFG_REL_CMD_LINE_CLR 0xfffffffe
MPHI_INTCTRL_HSDCOFLW_CLR 0xffefffff
CM_EMMCCTL_BUSYD_LSB 8
DMA1_CS_DREQ_STOPS_DMA_LSB 5
DMA15_TI_PERMAP_MSB 20
DMA10_SOURCE_AD_S_ADDR_BITS 31:0
CM_PERIADIV_DIV_MSB 12
FPGA_STATUS0_HW_ID_SET 0x0000000f
SMI_DSW3_WDREQ_SET 0x00000080
CCP2RS0 CCP2_BASE_ADDRESS + 0x108:RW
CCP2RS1 CCP2_BASE_ADDRESS + 0x208:RW
USB_HCINT0_WIDTH 32
VEC_CGMSAE_BOT_CONTROL_MASK 0xffffffff
PWM_CTL_MSEN4_BITS 31:31
EMMC_HWCAP0_V3_3_CLR 0xfeffffff
SCALER_DISPSTAT_WR_IRQ_MSB 31
HDMI_RAM_PACKET_6_5_MASK 0xffffffff
AVE_IN_CTRL_BYTE_ORDER_CLR 0xffffc7ff
USB_DOEPTSIZ15_MASK 0xffffffff
CM_EVENT_FLOSSB_MSB 15
SMI_DC_REQR_SET 0x00000fc0
DMA12_CS_RESET 0000000000
EMMC_IRPT_EN_CCRC_ERR_BITS 17:17
USB_DIEPDMAB0_WIDTH 32
CM_EVENT_LOSSC_SET 0x00000080
EMMC_HWCAP0_BASEMHZ_CLR 0xffff00ff
SPI_LTOH_TOH_CLR 0xfffffff0
A2W_PLLC_DIG2R_MASK 0x00ffffff
DSI0_TA_TO_CNT 0x7e209038:RW
SD_SB_STBY_T_LSB 20
DMA15_TI_SRC_WIDTH_SET 0x00000200
USB_GRXSTSP_HST_DPID_LSB 15
SD_PHYC_PHYRST_CLR 0xfffffffe
SMI_DSR0_RDREQ_BITS 7:7
CM_LOCK_LOCKH_SET 0x00000010
A2W_SMPS_CTLB0_RESET 0000000000
SYSAC_L2_ARBITER_CONTROL_DELAY_BITS 3:2
SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_LSB 0
L1_D_PRIORITY_RESET 0000000000
SD_CS_DEL_KEEP_SET 0x00040000
USB_GUID_MASK 0xffffffff
SMI_DC_DMAEN_LSB 28
A2W_PLLC_FRACR 0x7e102a20:RW
DMA14_TI_SRC_WIDTH_SET 0x00000200
GP_FSEL2_FSEL29_CLR 0xc7ffffff
EMMC_FORCE_IRPT_BLOCK_GAP_LSB 2
CCP2TX_TS_TFP_SET 0x00000040
PCM_INTEN_A_RXR_LSB 1
CM_TDCLKEN_WIDTH 14
CM_UARTDIV_DIV_BITS 21:0
USB_DFIFO9_MASK 0xffffffff
DMA6_DEBUG_LITE_BITS 28:28
VCE_SEMA_COUNT 8
APERF0_BW1_CTRL_MASK 0xf0001f1f
HD_CSC_24_23_RESET 0000000000
APERF0_BW1_WMAX_MASK 0x0000ffff
CM_H264CTL_RESET 0x00000040
ISP_APB_ID 0x20697370
AVE_IN_BUF0_ADDRESS_BUF0_ADDR_SET 0xffffffff
L1_L1_SANDBOX_START0_RESET 0x00000007
DMA8_SOURCE_AD_MASK 0xffffffff
MS_VPU_STAT 0x7e0000c8:RO
PM_DSI1_LDOCTRL_CLR 0xffe00007
A2W_PLLA_DSI0_DIV_LSB 0
CCP2TX_TS_TQL_CLR 0xffffe0ff
A2W_SMPS_B_MULTI 0x7e102fb0:RW
TXP_CTRL_TEST_MODE_MSB 4
INTERRUPT_UART_SPI0_SPI1 ((64) + 29 )
DMA_ENABLE_EN6_MSB 6
L1_D1_WR_SNOOPS_WIDTH 0
VCE_PC_EX0 0x7f000000 + 0x140014:RW
USB_GINTMSK_ENUM_DONE_MSB 13
PCM_CS_A_RXCLR_SET 0x00000010
EMMC_INTERRUPT_DMA_BITS 3:3
DMA11_DEBUG_OUTSTANDING_WRITES_LSB 4
A2W_PLLB_CTRL_PDIV_CLR 0xffff8fff
SMI_DSW0_WPACEALL_MSB 15
USB_DIEPCTL6_MASK 0xffffffff
TS_TSENSSTAT_WIDTH 12
CSI2_RPC1 CSI2_BASE_ADDRESS + 0x204:RW
SD_DQRCRC10_FALL_BITS 15:0
SD_SECEND3_WIDTH 32
DMA5_CS_END_LSB 1
IMASK2_0 0x7e002018:RW
IMASK2_1 0xffffffff:RW
DMA1_TI_DEST_INC_SET 0x00000010
SPI_FIFO_DATA_MSB 7
MS_MBOX_1_MBOX_LSB 0
A2W_SMPS_C_CTL_MASK 0x00000003
USB_DOEPTSIZ5_WIDTH 32
A2W_SMPS_B_STAT_BSTPWMB_MSB 8
GP_FSEL1_FSEL18_SET 0x07000000
TB_BOOT_OPT_DONT_SET_VPU_CLK_CLR 0xfffffbff
CM_LOCK_FLOCKB_MSB 9
CM_DSI1PCTL_BUSYD_BITS 8:8
ASB_ISP_M_CTRL_RESET 0x00000007
CMI_CAMTEST_MASK 0x0000001f
DMA3_CS_INT_SET 0x00000004
CAM0_CAMPRI_WIDTH 32
A2W_PLLA_ANA_SSCL_LIMIT_SET 0x003fffff
DMA12_TI_WAIT_RESP_CLR 0xfffffff7
MS_SEMA_8_MASK_BITS 0:0
OTP_PUBLIC_PARITY_SIZE_IN_ROWS 1
EMMC_INTERRUPT_RESET 0000000000
APERF0_BW1_RTRANS 0x7e00989c:RO
A2W_PLLB_DIG1_MASK 0x00ffffff
APERF0_BW0_ATRANS_RESET 0000000000
HDMI_KSV_FIFO_0_MASK 0xffffffff
V3D_PCTRS8_MASK 0x0000001f
CAM1_CAMIDPO_RESET 0000000000
DMA7_CS_ABORT_CLR 0xbfffffff
USB_DPTXFSIZ4_WIDTH 32
SMIDSR0 0x7e600000 + 0x10:RW
SMIDSR1 0x7e600000 + 0x18:RW
A2W_PLLA_DSI0_BYPEN_LSB 9
SMIDSR3 0x7e600000 + 0x28:RW
PM_CAM0_LDOHPEN_SET 0x00000004
USB_DCTL_RMT_WKUP_SIG_SET 0x00000001
DMA9_TI_SRC_WIDTH_MSB 9
HDMI_TX_PHY_TX_PHY_STATUS 0x7e9022d8:RW
DMA0_TI_SRC_IGNORE_LSB 11
USB_DIEPINT0_BACK2BACK_SETUP_LSB 6
EMMC_HWCAP1_SDR50_TUNE_SET 0x00002000
V3D_DBQSTP 0x7ec00000 +0x0e28:RW
PM_DSI1_LDOHPEN_BITS 2:2
DMA8_CONBLK_AD_WIDTH 32
PWM_CTL_POLA4_MSB 28
USB_GHWCFG3_RM_OPT_FEATURES_CLR 0xfffffbff
USB_GINTMSK_SESS_REQ_INT_BITS 30:30
SD_DQRCRC15_FALL_SET 0x0000ffff
CM_ARMDIV_DIV_MSB 12
CM_VECCTL_BUSY_CLR 0xffffff7f
DMA_INT_STATUS_INT3_CLR 0xfffffff7
EMMC_EXRDFIFO_CFG_RD_THRSH_SET 0x00000007
DMA7_CS_ACTIVE_LSB 0
A2W_PLLD_ANA_MULTI 0x7e102f50:RW
HD_MAI_CTL_RST_MAI_SET 0x00000001
SCALER_DISPECTRL_CB_NE_CTRL_LSB 29
HDMI_RAM_PACKET_8_1_WIDTH 32
SD_RWC_WRTVAL_BITS 12:8
EMMC_HWCAP0_XMEDBUS_BITS 18:18
MPHI_RXAXICFG_INTHRESH_LSB 8
SCALER_DISPCTRL_DSP1_PANIC_BITS 27:26
EMMC_INTERRUPT_DMA_ERR_MSB 28
PM_AVS_INTEN_ALERT_V3D_G_MSB 3
CM_SMICTL_BUSYD_MSB 8
HDMI_HORZB_MANUAL_HBP_SET 0x3ff00000
JP_OWDATA 0x7e00503c:RW
USB_GRXFSIZ_MASK 0x0000ffff
PWMCTL_POLA2 12
A2W_SMPS_L_SIA 0x7e1026d0:RW
PM_PROC_POWOK_SET 0x00000002
VEC_CPS2829_CPS3031_MASK 0xffffffff
A2W_XOSC1R_RESET 0x00000006
DSI0_CTRL_CTRL2_CLR 0xfffffffb
DMA14_TI 0x7e007e08:RO
ARM_EH_ARMHALT 0x00000020
V3D_DBCFG_MASK 0xffffffff
MS_SEMA_26_MASK_SET 0x00000001
L1_IC1_CONTROL_DISABLE_VLINE_CLR 0xffffff9f
PWM_STA_GAPO3_BITS 6:6
SD_CS_ASHDN_T_BITS 22:19
PCM_GRAY_RXFIFOLEVEL_CLR 0xffc0ffff
CM_CAM0CTL_BUSY_MSB 7
GP_FSEL0_FSEL04_LSB 12
A2W_PLLA_ANA_SCTL_SEL_MSB 2
OTP_PUBLIC_KEY_SIZE_IN_ROWS 4
DMA7_CONBLK_AD_MASK 0xffffffe0
SLIM_DCC8_PA0_MASK 0x00ffff1f
DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
HDMI_RAM_PACKET_2_8_MASK 0xffffffff
DMA5_DEBUG_READ_ERROR_LSB 2
A2W_SMPS_C_CLKR_RESET 0000000000
SCALER_DISPSTAT_PROF_IRQ_MSB 31
A2W_XOSC_BIAS_BIAS_LSB 0
L2START 0x7ee01004:RW
VEC_DAC_CONFIG_WIDTH 32
A2W_PLLH_PIX_RESET 0x00000100
UART_MCR_RESET 0000000000
HDMI_DETECTED_HORZA_WIDTH 15
DMA0_DEBUG_DMA_ID_LSB 8
DMA6_TI_TDMODE_LSB 1
DMA6_TI_DEST_WIDTH_SET 0x00000020
AVE_IN_CURRENT_LINE_NUM_INTERLACED_CLR 0xbfffffff
A2W_PLLB_ANA2_MASK 0x00ffffff
ARM_C0_SIZ128M 0x00000000
EMMC_CONTROL2_MASK 0xc0ff009f
FPGA_DCM_CTRL_REMOTE_EN_CLR 0xffffe0ff
A2W_PLLB_SP0_DIV_CLR 0xffffff00
SMI_CS_AFERR_RESET 0x0
A2W_XOSC_CTRL_USBOK_LSB 14
DMA_ENABLE_EN2_LSB 2
CM_H264CTL_GATE_SET 0x00000040
HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL (HDMI_BASE_ADDRESS + 0x2c0) + 0:RW
SD_CS_SDTST_CLR 0xffffffdf
EMMC_IRPT_EN_DATA_DONE_BITS 1:1
SPI_CS_TA_LSB 7
HDMI_AN0_MASK 0xffffffff
CM_AVEOCTL_SRC_MSB 3
SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_SET 0x000000c0
DMA_CS_ACTIVE (1<<0)
HDMI_SCHEDULER_CONTROL_IGN_VSYNC_PREDS_MSB 5
L1_L1_SANDBOX_PERI_BR_WIDTH 13
MPHI_C0INDDB_MORUN_MSB 31
IDCCMD 0x10002010:RW
A2W_PLLC_ANA_SSCS_MODE_BITS 16:16
SMI_CS_PVMODE_BITS 12:12
TXP_CTRL_BWE_LSB 16
DPHY_CSR_BYTE2_MASTER_DLL_OUTPUT 0x7ee07034:RW
GP_LEV0_LEVn0_SET 0xffffffff
MPHI_HSINDCF_MASK 0xdfffffff
DMA0_STRIDE_S_STRIDE_SET 0x0000ffff
CM_PWMCTL_MASH_CLR 0xfffff9ff
UNICAM_IVSTA(x) MACRO
HDMI_TX_PHY_SPREAD_SPECTRUM_MASK 0xffffffff
DSI0_PHYC_unused_LSB 4
DSI0_CTRL_CTRL2_MSB 2
GP_SEN1_SEN_MSB 21
L1_D_PRIORITY_c0_per_priority_MSB 11
AUX_MU_MSR_REG (0x7E215000 +0x058)
SH_RSP2_WIDTH 32
V3D_PCTR4_MASK 0xffffffff
DMA_TI_S_INC (1<<8)
SYSAC_V3D_LIMITER_INCREMENT_SET 0x00000001
DSI0_PHYC_MASK 0x0003f777
SD_CARCRC 0x7ee00100:RO
DMA1_TI_WAIT_RESP_MSB 3
TE_2VSWIDTH 0x7e20e01c:RW
A2W_PLLB_ARMR_MASK 0x000003ff
APERF1_BW2_CTRL_RESET_LSB 31
USB_DOEPDMAB7_MASK 0xffffffff
SCALER_DISPSTAT0_WIDTH 32
PM_IMAGE_ISFUNC_SET 0x00000020
DMA3_CS_PANIC_PRIORITY_MSB 23
DMA12_DEBUG_DMA_STATE_MSB 24
ASB_V3D_M_CTRL_WCOUNT_BITS 23:14
CM_ARMCTL 0x7e1011b0:RW
TXP_CTRL_BUSY_SET 0x00000002
EMMC_IRPT_EN_CMD_DONE_LSB 0
DMA6_TI_INTEN_SET 0x00000001
A2W_XOSC_CTRL 0x7e102190:RW
CCP2TX_TS_TUE_BITS 3:3
L2_TAG_STALLS 0x7ee01120:RO
A2W_PLLB_ANA_SSCLR_WIDTH 17
ASB_ISP_M_CTRL_EMPTY_BITS 2:2
A2W_PLLC_ANA_KAIP_KP_CLR 0xfffffff0
DSI0_HSTX_TO_C 0x7e209030:RW
SMIDSW0 0x7e600000 + 0x14:RW
SMIDSW1 0x7e600000 + 0x1C:RW
SMIDSW2 0x7e600000 + 0x24:RW
SMIDSW3 0x7e600000 + 0x2C:RW
SD_DQRCRC10_RISE_MSB 31
INTERRUPT_CDP ((64) + 46 )
DMA5_CS_DREQ_STOPS_DMA_LSB 5
SD_SECEND0_ADDR_LS_CLR 0xffffe000
SH_CMD_NEW_FLAG_BITS 15:15
DMA13_CS_PANIC_PRIORITY_SET 0x00f00000
SH_RSP0_MASK 0xffffffff
USB_HCINTMSK0_WIDTH 32
HDMI_CP_CONFIG_RESET 0x00130080
MPHI_HSINDCF_MTERM_LSB 28
DMA12_CS_DREQ_CLR 0xfffffff7
HDMI_READ_POINTERS_WIDTH 31
L1_L1_SANDBOX_END1_RESET 0000000000
TS_TSENSCTL_CLR_INT_SET 0x00000080
DMA7_CS_PAUSED_CLR 0xffffffef
MPHI_C0INDCF_EMPTY_RESET 0x0
USB_VBUS_DRV_SESSEND (1<<0)
DMA2_CS_END_LSB 1
CM_TD1CTL_GATE_BITS 6:6
PCM_DREQ_A_RX_SET 0x0000007f
GP_FSEL5_FSEL53_BITS 11:9
SYSAC_UC_ARBITER_CONTROL_THRESHOLD_MSB 5
OTP_BITSEL_REG_MASK 0x0000001f
EMMC_CONTROL2_ACCRC_ERR_CLR 0xfffffffb
PWM_STA_STA1_SET 0x00000200
DMA0_CS_PANIC_PRIORITY_BITS 23:20
SH_EDM_MASK 0x0007ffff
DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
PM_RSTC_HRCFG_BITS 21:20
EMMC_DMA_STATUS_LEN_NOMATCH_LSB 2
CSI2_RDS0 CSI2_BASE_ADDRESS + 0x128:RW
CSI2_RDS1 CSI2_BASE_ADDRESS + 0x228:RW
USB_GUSBCFG_ULPI_FS_LS_BITS 17:17
TXP_CTRL_TRANSPOSE_MSB 6
MS_MBOX_0_MBOX_SET 0xffffffff
DMA0_CS_INT_SET 0x00000004
A2W_PLLA_ANA_SSCS_STEP_SET 0x0000ffff
PM_GRAFX_POWOK_LSB 1
JCTRL 0x7e005000 + 0:RW
TB_BOOT_STATUS 0x7e20b50c:RW
DMA14_SOURCE_AD_S_ADDR_CLR 0x00000000
HDMI_KSV_FIFO_1_RESET 0000000000
DMA10_CS_ACTIVE_SET 0x00000001
MPHI_RXAXICFG_RXNPRIO_SET 0x0000000f
HD_VID_CTL_UFEN_MSB 30
USB_GINTMSK_ULPI_CK_INT_BITS 8:8
MPHI_HSINDFS_DFIFOLVL_RESET 0x0
CCP2TX_TS_WIDTH 20
APHY_CSR_DDR_PLL_SPRDSPECT_CTRL0 0x7ee06040:RW
APHY_CSR_DDR_PLL_SPRDSPECT_CTRL1 0x7ee06044:RW
TB_JTB_TDO_WIDTH 32
HDMI_RAM_PACKET_4_8_WIDTH 32
CM_DSI0PCTL_SRC_LSB 0
A2W_SMPS_L_SCVR_WIDTH 5
TIMER_CTRL_DIV16 (1 << 2)
CM_SDCCTL_ENAB_MSB 4
GP_HEN2_HENn64_CLR 0xffffffc0
SMI_CS_RXF_MSB 31
SD_DQLCRC10_FALL_CLR 0xffff0000
CM_DSI1ECTL_SRC_SET 0x0000000f
CM_CAM1CTL_ENAB_BITS 4:4
CM_GNRICCTL_GATE_MSB 6
MPHI_HSINDDB_TENDINT_RESET 0x0
HD_CSC_CTL_USERGB2YCC_SET 0x00000002
GP_FSEL4_FSEL40_BITS 2:0
USB_DOEPINT0_STS_PHSE_RCVD_MSB 5
PCM_MODE_A_FSM_CLR 0xffdfffff
SD_STALL_CYCLES_SET 0x000003ff
DMA4_TI_INTEN_LSB 0
A2W_XOSC_CTRL_PLLAOK_MSB 18
A2W_XOSC_CPRR_RESET 0000000000
DSI0_CTRL_RESET 0000000000
GP_AJBTDI_MASK 0xffffffff
CM_PLLTCTL_BUSY_CLR 0xffffff7f
CM_BURSTCTL_MASK 0x000000b0
AUX_SPI_CNTL0_SPEED 0xFFF00000
GP_FSEL3_FSEL32_BITS 8:6
HDMI_DETECTED_VERTB0_MANUAL_VSPO0_LSB 9
PWMDMAC_DREQ_LEN 8
MS_MBOX_1_MASK 0xffffffff
A2W_XOSC_CTRL_SMPSOK_SET 0x00008000
DMA8_TXFR_LEN_XLENGTH_CLR 0xffff0000
CAM1_CAMPRI_RESET 0000000000
SCALER_DISPECTRL_POSTED_CTRL_SET 0x003f0000
EMMC_SLOTISR_VER_RESET 0x99020000
HDMI_BKSV0_WIDTH 32
CM_PLLD_HOLDPER_BITS 7:7
USB_DIEPINT1_WIDTH 32
SMI_DSW3_MASK 0xffffffff
ARM_STATUS 0x7E00B000 +0x444:RW
GP_FSEL2_FSEL24_BITS 14:12
DMA10_DEBUG_DMA_ID_LSB 8
JP_MCTRL 0x7e005008:RW
CM_DPIDIV_DIV_SET 0x0000fff0
GP_REN0_RESET 0000000000
USB_DCTL_SGNP_IN_NAK_LSB 7
A2W_PLLD_PER_CHENB_SET 0x00000100
CMI_CAMTEST_SRC_SET 0x0000000f
I2C_SPI_SLV_MIS_MASK 0x0000000f
GP_LEV1_LEVn32_CLR 0x00000000
CM_INTEN_WRFAIL_SET 0x00080000
CM_PWMCTL_ENAB_LSB 4
CM_GP2CTL_KILL_BITS 5:5
CM_UARTCTL_BUSYD_SET 0x00000100
GP_FSEL1_FSEL16_BITS 20:18
A2W_SMPS_L_SIA_ANA_LSB 0
CM_PLLH_LOADAUX_MSB 1
DMA11_TI_BURST_LENGTH_BITS 15:12
GP_LEV1_MASK 0xffffffff
APERF0_BW0_WTRANS_WIDTH 32
HDMI_CEC_TX_DATA_1 0x7e9020fc:RW
HDMI_CEC_TX_DATA_2 0x7e902100:RW
HDMI_CEC_TX_DATA_3 0x7e902104:RW
HDMI_CEC_TX_DATA_4 0x7e902108:RW
MULTICORE_SYNC_IREQ_1 MULTICORE_SYNC_BASE_ADDRESS + 0x88:RW
SMI_DCS_WRITE_MSB 3
SLIM_DCC9_PA0 0x7e210320:RW
SLIM_DCC9_PA1 0x7e210324:RW
GP_FSEL0_FSEL08_BITS 26:24
HDMI_TST_AN1_MASK 0xffffffff
HDMI_HORZB_MANUAL_HFP_CLR 0xfffffdff
DSI1_HS_DLT4_MASK 0xffffffff
DMA13_DEBUG_OUTSTANDING_WRITES_BITS 7:4
GP_FSEL6_FSEL64_CLR 0xffff8fff
MS_ICSET_0 0x7e000090:RW
MS_ICSET_1 0x7e000094:RW
SMI_DSW2_WSWAP_SET 0x00400000
HDMI_DETECTED_HORZB_MANUAL_HFP_SET 0x00000200
SPI_CS_CPOL_SET 0x00000008
USB_DOEPDMA2_WIDTH 32
DMA0_CS_ERROR_CLR 0xfffffeff
CMI_PASSWORD 0x5a000000
DMA6_DEBUG_READ_ERROR_LSB 2
DMA3_TI_MASK 0x07fffffb
A2W_SMPS_A_MODE_RESET 0000000000
L1_D1_RD_MISSES_MASK 0000000000
MPHI_OUTDDB_MASK 0x3fffffff
CAM0_CAMIBLS_MASK 0xffffffff
AVE_OUT_CTRL_INVERT_CSYNC_BITS 17:17
L1_IC1_PRIORITY_IC1_APRIORITY2_SET 0x00000f00
ARM_BASE 0x7E00B000
A2W_SMPS_A_GAIN_MASK 0x00000007
USB_DIEPCTL15_WIDTH 32
DMA9_TI_WAITS_MSB 25
V3D_SRQUA_MASK 0xffffffff
PM_PROC_ARMRSTN_SET 0x00000040
I2C_BASE_1 0x7e804000
USB_DTHRCTL_NON_ISO_THR_EN_RESET 0x0
DMA11_TI_WAIT_RESP_MSB 3
DMA10_TI 0x7e007a08:RO
PM_RSTS_HADWRF_MSB 5
VEC_WSE_WSS_DATA 0x7e8060c8:RW
DMA1_NEXTCONBK_ADDR_MSB 31
DMA7_TI_PERMAP_CLR 0xffe0ffff
EMMC_CONTROL0_PWCTL_HWRST_CLR 0xffffefff
MPHI_INTSTAT_TXEND_MSB 16
AVE_OUT_CB_COEFF_BLUE_COEFF_CLR 0xfffffc00
SMI_DSW0_WFORMAT_LSB 23
PM_AVS_INTEN_ALERT_ARM_P_SET 0x00000010
DSI0_INT_STAT_MASK 0xffffffff
USB_GUSBCFG_OTG_I2C_SEL_CLR 0xfffeffff
GP_HEN0_MASK 0xffffffff
USB_DIEPCTL0_ENA_SET 0x80000000
SD_CS_RESTRT_BITS 0:0
DMA8_DEBUG_WIDTH 29
IC1_FORCE0_RESET 0000000000
SD_DMRCRC0_HIGH_SET 0xffff0000
USB_GINTMSK_PRT_INT_RESET 0x0
SD_MR_DONE_RESET 0x1
FPGA_DCM_CTRL_PERI_EN_LSB 24
DMA11_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
EMMC_CONTROL1_CLK_FREQ_MS2_SET 0x000000c0
SLIM_APB_ID 0x736c696d
ASB_CPR_CTRL_FULL_LSB 3
DMA15_DEBUG_OUTSTANDING_WRITES_LSB 4
A2W_PLLC_DIG0 0x7e102020:RW
A2W_PLLC_DIG1 0x7e102024:RW
A2W_PLLC_DIG2 0x7e102028:RW
PM_DFT_STOPALLCLOCKS_SET 0x00000002
GP_FSEL5_FSEL53_SET 0x00000e00
PM_DSI0_LDOLPEN_MSB 1
DMA2_TI_DEST_INC_SET 0x00000010
DMA3_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
SCALER_DISPECTRL_BUSY_STATUS_BITS 31:8
VCSIGNAL0 0x7f000000 + 0x4408b4:RW
CM_PCMDIV_MASK 0x00ffffff
DMA3_TI_DEST_IGNORE_BITS 7:7
DMA9_TI_DEST_INC_CLR 0xffffffef
HDMI_FIFO_CTL_FIFO_RESET_CLR 0xffffffdf
A2W_XOSC_PWRR 0x7e102c90:RW
PCM_DREQ_A_TX_BITS 14:8
DMA10_SOURCE_AD_S_ADDR_MSB 31
GP_AREN1_RESET 0000000000
SMI_CS_TXW_RESET 0x1
VCSIGNAL1 0x7f000000 + 0x4408bc:RW
SD_SC_T_RRD_LSB 20
CM_ARMCTL_MASK 0x000013bf
SD_RDC_WIDTH 28
HD_CSC_CTL_MASK 0x000000ff
A2W_PLLB_ANA_KAIP_WIDTH 11
I2C2_FIFO_WIDTH 8
AVE_OUT_CB_COEFF_WIDTH 30
PCM_DREQ_A_RX_BITS 6:0
DMA7_TI_DEST_IGNORE_MSB 7
CM_SDCCTL_KILL_CLR 0xffffffdf
SH_HSTS_CMD_TIME_OUT_SET 0x00000040
FPGA_MB_XV3D_BUILD_NUM_MASK 0xffffffff
AM_HVSM_PRI 0x1800d01c:RW
SMI_DSW1_WPACE_BITS 14:8
DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
CM_SMICTL_KILL_SET 0x00000020
HD_HDM_CTL_SW_RST_MSB 2
SD_CS_DLLCAL_LSB 10
DMA6_TI_BURST_LENGTH_CLR 0xffff0fff
USB_DIEPCTL0_NEXT_EP_RESET 0x0
MS_SEMA_5_MASK 0x00000001
DMA_INT_STATUS_INT14_CLR 0xffffbfff
SD_PHYC_PHYRST_MSB 0
CM_PLLD_LOADPER_SET 0x00000040
EMMC_IRPT_MASK 0x7e300034:RW
CM_OTPDIV_DIV_MSB 16
SMI_DSR3_RHOLD_LSB 16
USB_GHWCFG3_I2C_INTERFACE_CLR 0xfffffeff
HDMI_RAM_PACKET_2_2_WIDTH 32
CM_SDCCTL_SRC_BITS 3:0
DMA5_NEXTCONBK_ADDR_MSB 31
CM_OSCFREQF_FRAC_CLR 0xfff00000
A2W_PLLC_ANA_SCTL_SEL_CLR 0xfffffff8
DMA9_CONBLK_AD_WIDTH 32
USB_GRXSTSP_WIDTH 25
V3D_FDBGS_MASK 0xffffffff
DMA0_CS_ERROR_MSB 8
DMA4_TXFR_LEN_XLENGTH_MSB 15
EMMC_STATUS_CMD_INHIBIT_MSB 0
HD_VID_CTL_EMPSYNC_RESET 0x0
SD_DQRCRC11_RISE_RESET 0x0
USB_GHWCFG3_MODE_CLR 0xffffff7f
DMA3_DEST_AD_D_ADDR_MSB 31
USB_GOTGCTL_B_SES_VLD_MSB 19
CM_TDCLKEN_PLLBBYP_BITS 1:1
SD_DQRCRC4_RISE_LSB 16
SYSAC_TRANS_PRIORITY_P_PRIORITY_SET 0x000000f0
HDMI_POSTING_MASTER_MASK 0x000000ff
DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
MS_SEMA_6_MASK_MSB 0
AJB_BASE 0x7e2000c0
VEC_WSE_VPS_CONTROL_WIDTH 32
MS_MBOX_7_MBOX_SET 0xffffffff
PWM_CTL_SBIT3_MSB 19
HD_MAI_CTL_CHNUM_RESET 0x2
DMA15_DEST_AD_D_ADDR_MSB 31
CM_DPICTL_KILL_LSB 5
PM_RSTC_FRCFG_SET 0x00030000
AVE_OUT_OFFSET_RESET 0x80109090
SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_RESET 0x0
SCALER_DISPSTAT_DSP0_IRQ_LSB 1
SMI_DSR1_RPACEALL_MSB 15
SMI_DSR2_RHOLD_SET 0x003f0000
PM_IMAGE_POWUP_LSB 0
CM_BURSTCNT 0x7e10114c:RW
CM_EVENT_LOSSA_SET 0x00000020
CM_SLIMCTL_MASH_MSB 10
DMA3_CONBLK_AD_SCB_ADDR_BITS 31:5
DMA9_CS_DREQ_STOPS_DMA_LSB 5
USB_DOEPINT0_XFER_COMPL_SET 0x00000001
A2W_XOSC_CTRL_PLLBEN_LSB 7
USB_DIEPDMAB14_WIDTH 32
A2W_PLLC_ANA_KAIP_KA_SET 0x00000700
EMMC_FORCE_IRPT_CCRC_ERR_SET 0x00020000
DSI0_PHYC_dlane_hsen_1_sync_CLR 0xffffffdf
DMA14_TI_SRC_IGNORE_CLR 0xfffff7ff
A2W_PLLC_ANA3R_RESET 0x00000180
IC0_VADDR 0x7e002030:RW
SD_CARCRC_RISE_SET 0xffff0000
APERF1_BW0_CTRL_RESET_BITS 31:31
DMA8_DEST_AD 0x7e007810:RO
APERF0_GEN_CTRL_RESET 0000000000
SD_MRT_T_MRW_BITS 8:0
MS_SEMA_12_MASK_MSB 0
USB_PCGCR_PWR_CLMP_BITS 2:2
PWM_CTL_SBIT4_SET 0x08000000
DMA15_CONBLK_AD_RESET 0000000000
DMA2_CS_DISDEBUG_MSB 29
DMA13_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
AVE_OUT_STATUS_HBACK_PORCH_BITS 5:5
SH_ARG 0x7e202004:RW
CCP2TX_TIC_TIIE_LSB 0
CM_INTEN_FLOSSD_MSB 17
USB_DPTXFSIZ15_MASK 0xffffffff
HD_CSC_CTL_USERGB2YCC_RESET 0x0
DMA15_TXFR_LEN_YLENGTH_LSB 16
A2W_PLLA_ANA_SCTL_UPDATE_BITS 3:3
DMA13_TI_WAIT_RESP_BITS 3:3
DMA12_CS_RESET_SET 0x80000000
PCM_MODE_A_WIDTH 29
CSI2_RSA0 CSI2_BASE_ADDRESS + 0x10C:RW
MPHI_OUTDDA_START_CLR 0x00000000
USB_HCCHAR0_DEV_ADDR_SET 0x1fc00000
USB_DOEPMSK 0x7e980814:RW
GP_FSEL1_FSEL19_LSB 27
FPGA_DCM_CTRL_REMOTE_RST_MSB 4
EMMC_HWCAP1_SDR50_LSB 0
CM_PLLC_HOLDPER_MSB 7
DMA3_TI_WAIT_RESP_CLR 0xfffffff7
EMMC_STATUS_WRT_PROTECT_SET 0x00080000
AVE_IN_STATUS_BUF_NOT_SERV_BITS 3:3
GP_SET2_MASK 0x0000003f
TB_BOOT_OPT_BOOT_HALT_MSB 7
AVE_OUT_CTRL_INTERLEAVE_CLR 0xffffefff
DMA0_TI_TDMODE_BITS 1:1
CM_CAM0CTL 0x7e101040:RW
DMA10_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
SD_DQRCRC6_FALL_BITS 15:0
AVE_IN_CTRL_LENGTH_IN_PXLS_CLR 0xfffffeff
L1_L1_SANDBOX_START3_CTRL_CLR 0xfffffffe
USB_GUSBCFG_ULPI_UTMI_SEL_CLR 0xffffffef
USB_DSTS_SUSP_STS_RESET 0x0
DMA5_TI_TDMODE_MSB 1
DMA_INT_STATUS_INT7_SET 0x00000080
DMA_ENABLE_RESET 0x00007fff
USB_GRXSTSP_DEV_PKT_STS_LSB 17
ASB_H264_S_CTRL_CLR_ACK_MSB 1
PCM_CS_A_TXTHR_CLR 0xffffff9f
CM_PLLD_LOADCORE_SET 0x00000010
CPG_Param3_MASK 0xffffffff
CAM1_CAMIDS_MASK 0xffffffff
CM_PLLA_HOLDCCP2_CLR 0xfffffff7
PWM_DAT1_RESET 0000000000
HDMI_VERTB1_MANUAL_VBP1_SET 0x00000100
SD_PHYC_VREF_ENB_SET 0x00000010
CMI_CAM0_WIDTH 6
DMA3_CS_ACTIVE_LSB 0
UNICAM_IHWIN(x) MACRO
APERF1_BW1_CTRL_EN_SET 0x40000000
MPHI_C1INDS_DISCARD_SET 0x80000000
JMCTRL 0x7e005000 + 0x8:RW
A2W_PLLC_CORE0_RESET 0x00000100
USB_GRXSTSP_HST_PKT_STS_SET 0x001e0000
CM_PLLTCTL_SRC_LSB 0
GP_FEN0_RESET 0000000000
AVE_OUT_CB_COEFF_RED_COEFF_LSB 20
DMA11_CS_MASK 0xf0ff017f
INTERRUPT_CPG ((64) + 60 )
CM_DSI0ECTL 0x7e101058:RW
DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
I2C_SPI_SLV_FR_RXBUSY_BITS 5:5
INTERRUPT_CPR ((64) + 47 )
APERF0_BW2_ATWAIT_RESET 0000000000
CAM1_CAMDBEA1_MASK 0xffffffff
FPGA_CTRL0_SPI0_SEL_A_SET 0x00000200
CM_GP0CTL_MASK 0x000007bf
OTP_ADDR_REG_MASK 0x0000001f
A2W_SMPS_L_SCA_ANA_BITS 11:0
USB_DPTXFSIZ5_WIDTH 32
CM_DSI1ECTL_ENAB_LSB 4
EMMC_CMDTM_TM_BLKCNT_EN_CLR 0xfffffffd
A2W_PLLD_ANA_KAIP_KP_CLR 0xfffffff0
GP_SET0_SETn0_LSB 0
DMA1_STRIDE_D_STRIDE_BITS 31:16
AUX_MU_MCR_REG (0x7E215000 +0x050)
SMI_DSR3_FSETUP_SET 0x00400000
DMA13_TXFR_LEN_MASK 0x0000ffff
CAM1_CAMDBEA0_RESET 0000000000
GP_PUDCLK2 0x7e2000a0:RW
EMMC_HWMAXAMP0_AMP_33V_BITS 7:0
USB_DCFG_DEV_SPD_SET 0x00000003
USB_HCTSIZ0_DO_PNG_MSB 31
A2W_SMPS_L_SPA_ANA_BITS 9:0
USB_HFNUM_REM_SET 0xffff0000
I2C0_DEL_RESET 0x00300030
USB_DOEPINT0_IN_EP_NAK_EFF_RESET 0x0
SD_DQRCRC4_FALL_LSB 0
A2W_PLLC_FRAC_WIDTH 20
SD_DQLCRC9_RISE_LSB 16
EMMC_IRPT_EN_ADMA_ERR_MSB 25
USB_HCINTMSK0 0x7e98050c:RW
SD_CS_ASHDNE_LSB 17
DMA8_NEXTCONBK_ADDR_SET 0xffffffe0
SH_EDM_FIFO_COUNT_SET 0x000001f0
CLR_GPIO(g) MACRO
USB_VBUS_DRV_BVALID (1<<2)
DMA14_CS_RESET 0000000000
EMMC_STATUS_CMD_INHIBIT_CLR 0xfffffffe
A2W_XOSC_CTRL_PLLAEN_CLR 0xffffffbf
MPHI_C0INDCF_MTERM_MSB 28
AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_SET 0x00000fff
SMIDA_DEVICE 8
A2W_PLLD_ANA_SSCS_MODE_SET 0x00010000
DMA1_CS_END_BITS 1:1
SCALER_DISPSTAT_DSP1_IRQ_MSB 31
MPHI_CTRL_INVERT_MSB 8
PM_AVS_RSTDR_H264_I_MSB 2
USB_DIEPINT0_XFER_COMPL_LSB 0
DMA2_CS_DREQ_SET 0x00000008
FPGA_DCM_RD_DATA_DATA_BITS 15:0
GP_LEN0 0x7e200070:RW
USB_DCFG_PER_SCH_INTV_SET 0x03000000
L1_IC0_CONTROL_START_FLUSH_MSB 1
PM_HDMI_RESET 0x00080002
DMA7_TI_DEST_IGNORE_BITS 7:7
APERF1_BW1_RMAX_RESET 0000000000
SD_SE_T_XSR_SET 0x0000003f
EMMC_CONTROL0_HCTL_HS_EN_MSB 2
I2C1_DEL_WIDTH 32
APHY_CSR_DDR_PLL_PWRDWN 0x7ee06058:RW
VCE_STATUS_RUNNING_POS 24
DMA_INT_STATUS_INT9_SET 0x00000200
TB_BOOT_SECURE_MODE 0x7e20b508:RW
CM_DFTCTL_FRAC_SET 0x00000200
USB_DTHRCTL_RX_THR_EN_BITS 16:16
GP_CLR1_RESET 0000000000
PM_PADS3_POWOK_MSB 5
USB_HCINTMSK5 0x7e9805ac:RW
MS_VPUSEMA_0_VPUSEMA_0_MSB 0
DMA9_SOURCE_AD_S_ADDR_LSB 0
GP_GPTEST_MASK 0x0000000f
SMI_DSW1_WWIDTH_CLR 0x3fffffff
CM_GP1CTL_RESET 0x00000200
MPHI_HSINDCF_HANDLE_BITS 27:20
CM_GP0DIV_DIV_SET 0x00ffffff
GP_FSEL1_FSEL12_CLR 0xfffffe3f
DMA12_TI_WAITS_CLR 0xfc1fffff
SYSAC_DBG_PRIORITY_PRIORITY_MSB 3
EMMC_CONTROL1_SRST_DATA_BITS 26:26
HDMI_RAM_PACKET_13_7_WIDTH 32
FPGA_MB_XSYS_BUILD_NUM_WIDTH 32
DMA8_DEBUG_VERSION_LSB 25
USB_DIEPDMA11_WIDTH 32
USB_HCTSIZ0_PKT_CNT_SET 0x1ff80000
DMA11_TXFR_LEN_WIDTH 16
EMMC_HWCAP0_MAXLEN_SET 0x00030000
L1_L1_SANDBOX_START3_WIDTH 30
EMMC_CONTROL0_HCTL_CRDDET_S_LSB 7
CM_BURSTCTL 0x7e101148:RW
A2W_PLLH_ANA2_WIDTH 24
CM_PLLA_LOADPER_LSB 6
USB_DIEPINT0_BNA_SET 0x00000200
TXP_DIM_HEIGHT_SET 0x0fff0000
A2W_PLLD_DIG3R_RESET 0x00000004
TXP_PROGRESS_WIDTH 12
HDMI_SCHEDULER_CONTROL_MODE_ACTIVE_LSB 1
HDMI_FIFO_CTL_ON_VB_DONE_BITS 15:15
CM_V3DCTL_KILL_LSB 5
CM_TD1CTL_GATE_SET 0x00000040
EMMC_IRPT_MASK_CCRC_ERR_LSB 17
HDMI_HORZB_MANUAL_HSP_BITS 19:10
AVE_OUT_CR_COEFF_BLUE_COEFF_CLR 0xfffffc00
USB_HCINT0_BBL_ERR_RESET 0x0
PIXELVALVE1_HORZA_MASK 0xffffffff
AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_CLR 0xffffbfff
PCM_DREQ_A_RX_PANIC_SET 0x007f0000
USB_PCGCR_GATE_HCLK_CLR 0xfffffffd
CAM0_CAMCMP1 0x7e800030:RW
SPI_DLEN_MASK 0x0000ffff
PCM_CS_A_SYNC_BITS 24:24
TXP_CTRL_VERSION_SET 0x00c00000
DMA15_SOURCE_AD_S_ADDR_BITS 31:0
CM_OTPCTL_BUSYD_LSB 8
A2W_PLLH_AUX_DIV_MSB 7
FPGA_CTRL0_SD_PSU_EN_MSB 4
CM_PWMCTL_BUSYD_SET 0x00000100
OTP_INIT_STATUS_REG_WIDTH 32
CM_PLLTCNT2_CNT_BITS 23:0
EMMC_STATUS_READ_TRANSFER_SET 0x00000200
SD_SF_PHYHOLD_SET 0x20000000
APHY_CSR_DDR_PLL_ENABLE_CH 0x7ee06050:RW
SYSAC_UC_ARBITER_CONTROL_THRESHOLD_LSB 4
ASB_ISP_M_CTRL_EMPTY_CLR 0xfffffffb
DMA0_CS_PANIC_PRIORITY_CLR 0xff0fffff
APERF0_BW2_CTRL_EN_CLR 0xbfffffff
GP_FSEL6_FSEL67_MSB 23
USB_GOTGCTL_DBNC_TIME_MSB 17
DMA13_TI_WAIT_RESP_CLR 0xfffffff7
VCE_VERSION 0x7f000000 + 0x140004:RW
SD_VIN_VIO_MSB 20
SMI_DC_REQR_BITS 11:6
HDMI_CP_STATUS 0x7e902048:RW
A2W_PLLD_CORE_BYPEN_LSB 9
DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
CCP2TX_TS_IS_SET 0x00010000
DMA14_CS_END_CLR 0xfffffffd
APERF1_BW1_CTRL_ID_EN_BITS 29:29
GP_FSEL0_FSEL01_SET 0x00000038
A2W_PLLD_FRAC_MASK 0x000fffff
SD_CS_SREF2RUN_RESET 0x0
DMA7_CS_PANIC_PRIORITY_MSB 23
SCALER_DISPALPHA2_WIDTH 32
USB_GI2CCTL_DEV_ADR_CLR 0xf3ffffff
HDMI_RAM_PACKET_11_6_RESET 0000000000
PWM_STA_STA2_LSB 10
SD_DQRCRC10_MASK 0xffffffff
PWM_STA_STA1_BITS 9:9
PWM_STA_EMPT1_SET 0x00000002
A2W_SMPS_C_CLK_OSCDIV_SET 0x00000003
SCALER_DISPECTRL_PANIC_CTRL_LSB 0
USB_DIEPCTL0_SET_ODD_FR_SET 0x20000000
DMA14_CS_PANIC_PRIORITY_SET 0x00f00000
DMA3_DEBUG_DMA_ID_SET 0x0000ff00
USB_DCTL_GNP_IN_NAK_STS_LSB 2
CM_PLLC_LOADCORE1_MSB 2
DMA_ENABLE_EN7_MSB 7
CM_OTPCTL_BUSY_MSB 7
IC0_MASK6_WIDTH 31
USB_HCCHAR5_WIDTH 32
CM_ISPDIV_RESET 0000000000
DMA11_DEBUG_LITE_MSB 28
DMA11_DEBUG_VERSION_LSB 25
DSI1_LPRX_TO_CNT_RESET 0000000000
EMMC_SPI_INT_SPT_RESET 0000000000
GP_FSEL5_FSEL58_MSB 26
A2W_SMPS_LDO0_MASK 0x00ffffff
DUMMYREG 0x7C:RW
GP_FSEL6_FSEL67_BITS 23:21
USB_GRXSTSP_DEV_EP_NUM_MSB 3
DMA14_TI_WAITS_BITS 25:21
DMA1_SOURCE_AD_S_ADDR_CLR 0x00000000
SD_MRT_WIDTH 9
SLIM_DCC2_CON_RESET 0000000000
IC1_FORCE0_SET_WIDTH 32
I2C_SPI_SLV_VCSTAT_DATA_LSB 0
DMA5_TI_SRC_DREQ_BITS 10:10
DMA14_TXFR_LEN_WIDTH 16
CM_TD0CTL_BUSYD_BITS 8:8
PM_IMAGE_ISPRSTN_BITS 8:8
A2W_PLLC_ANA_VCO_WIDTH 1
CAM0_CAMIBSA0_RESET 0000000000
MPHI_C0INDS_WORDS_BITS 20:0
SMI_DSW0_WHOLD_LSB 16
SD_DQRCRC4_WIDTH 32
L1_D_PRIORITY_c1_per_priority_CLR 0xf0ffffff
CM_TDCLKEN_HDMIBYP_SET 0x00000100
DMA2_TI_SRC_WIDTH_SET 0x00000200
DMA0_DEBUG_VERSION_SET 0x0e000000
AVE_IN_STATUS_EVEN_FIELD_MSB 11
A2W_PLLA_MULTI_WIDTH 0
CM_DPICTL_SRC_LSB 0
HDMI_DVO_TIMING_ADJUST_A_MASK 0x000fffff
USB_GUSBCFG_PHY_SEL_CLR 0xffffffbf
USB_HPRT_CONN_DET_SET 0x00000002
UART_MSR_WIDTH 8
EMMC_IRPT_EN_DMA_ERR_CLR 0xefffffff
A2W_PLLH_DIG3R_MASK 0x00ffffff
USB_DOEPCTL0_DPID_SET 0x00010000
CM_TIMERDIV_DIV_CLR 0xfffc0000
SMICS_ENABLE 0
USB_GAHBCFG_NP_TXF_EMP_LVL_RESET 0x0
CCP2TX_TAC_WIDTH 32
EMMC_CONTROL1_SRST_DATA_LSB 26
USB_DIEPCTL0_TXF_NUM_LSB 22
CAM0_CAMICTL_MASK 0xffffffff
DMA3_TI_DEST_INC_SET 0x00000010
SYSAC_TRANS_PRIORITY_N_PRIORITY_LSB 0
I2C0_A 0x7e20500c:RW
I2C0_C 0x7e205000:RW
CM_SLIMCTL_KILL_LSB 5
MPHI_C1INDCF_LENGTH_BITS 19:0
DMA7_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
USB_DIEPINT0_STS_PHSE_RCVD_SET 0x00000020
MPHI_INTCTRL_HSDISC_LSB 16
EMMC_IRPT_MASK_CEND_ERR_MSB 18
I2C0_S 0x7e205004:RW
PIXELVALVE2_VERTA 0x7e807014:RW
PIXELVALVE2_VERTB 0x7e807018:RW
V3D_BFC 0x7ec00000 +0x0134:RW
EMMC_STATUS_CARD_INSERT_MSB 16
USB_GINTMSK_HCH_INT_CLR 0xfdffffff
HDMI_ASYNC_RM_INTEGRATOR (HDMI_BASE_ADDRESS + 0x300) + 16:RW
AVE_OUT_CTRL_BYTE_SWAP_SET 0x00f80000
EMMC_STATUS_NEW_READ_DATA_LSB 11
CM_GNRICDIV 0x7e101004:RW
CM_INTEN_WIDTH 24
SPI_CS_CLEAR_SET 0x00000030
USB_GINTMSK_RXF_LVL_SET 0x00000010
MPHI_OUTDS_VALID_RESET 0x0
CM_PLLD_HOLDDSI0_MSB 1
GP_FSEL6_FSEL68_SET 0x07000000
CM_ISPCTL_BUSYD_LSB 8
DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
EMMC_FORCE_IRPT_CMD_DONE_LSB 0
DMA15_TI_DEST_DREQ_BITS 6:6
I2C_SPI_SLV_CR_TESTFIFO_LSB 11
PCM_TXC_A_CH1WID_SET 0x000f0000
USB_GINTMSK_ULPI_CK_INT_LSB 8
TB_TASK_WIDTH 17
A2W_PLLC_ANA_SSCL_WIDTH 22
SMI_DSR1_RSETUP_CLR 0xc0ffffff
PM_CCP2TX 0x7e10004c:RW
PIARBCTL_CAM_DELAY_SET 0x0000000c
USB_GINTMSK_I2C_INT_SET 0x00000200
DMA14_TI_BURST_LENGTH_CLR 0xffff0fff
V3D_BPCS_MASK 0xffffffff
MPHI_HSINDS_VALID_CLR 0xbfffffff
PWM_CTL_PWEN2_SET 0x00000100
USB_GUSBCFG_ULPI_UTMI_SEL_BITS 4:4
CM_GNRICCTL_KILL_BITS 5:5
CM_GNRICCTL_SRC_CLR 0xfffffff0
SCALER_DISPEOLN_MASK 0xffffffff
USB_HCFG_LS_PHY_CLK_SEL_BITS 1:0
EMMC_CMDTM_TM_DMA_EN_SET 0x00000001
CAM0_CAMDBWP 0x7e80020c:RW
VPU_ARB_CTRL_L2_CHANNEL_INIBIT_SET 0x0000ff00
MPHI_HSINDCF_LENERR_SET 0x40000000
USB_DOEPINT3_WIDTH 32
HD_HDM_CTL_ENDIAN_SET 0x00000002
PM_WDOG_TIME_BITS 19:0
L1_IC1_PRIORITY_IC1_APRIORITY3_LSB 12
DMA4_SOURCE_AD_S_ADDR_MSB 31
EMMC_HWCAP1_DRV18_TYPEA_CLR 0xffffffef
PWMCTL_MSEN3 23
DMA4_DEBUG_LITE_MSB 28
HDMI_V 0x7e902038:RW
TXP_CTRL_VERSION_BITS 23:22
CM_DSI1ECTL_RESET 0000000000
CM_DSI0PCTL_BUSYD_CLR 0xfffffeff
ARM_C1_BELL1 0x00000008
V3D_SRQUL_MASK 0x00000fff
V3D_PCTR1_WIDTH 32
MPHI_INTSTAT_HSDISC_SET 0x40000000
DMA9_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
SD_SD_T_RPpb_CLR 0xffffff0f
SD_DQRCRC10_FALL_MSB 15
MPHI_C1INDFS_WIDTH 32
CM_VECCTL_KILL_SET 0x00000020
DMA14_DEBUG_DMA_ID_BITS 15:8
USB_HCTSIZ6_WIDTH 32
UART_LCR_EPS_CLR 0xffffffef
SD_DQRCRC7_FALL_RESET 0x0
SCALER_DISPECTRL_CB_BUSY_MSB 31
HD_HDM_CTL_CECRXD_RESET 0x0
SYSAC_L2_ARBITER_CONTROL_LIMIT_BITS 1:0
V3D_BASE 0x7ec00000
USB_HCINT0_NYET_SET 0x00000040
DMA5_SOURCE_AD_MASK 0xffffffff
L2_CONT_OFF_l2_enable_stats_LSB 5
SH_RSP2_CID_CSD_MSB 31
V3D_SRQPC_WIDTH 32
IC1END 0xffffffff:RW
DMA6_CS_RESET_SET 0x80000000
CM_GP1CTL_BUSY_LSB 7
HDMI_CEC_CNTRL_4_RESET 0xead4c3be
CM_TECCTL_MASK 0x000003b3
USB_DOEPDMA11_MASK 0xffffffff
DMA11_CONBLK_AD_MASK 0xffffffe0
CCP2TX_TBA_RESET 0000000000
MPHI_MINFS_WIDTH 32
GP_FSEL5_FSEL54_LSB 12
MS_SEMA_21_MASK_MSB 0
FPGA_CTRL0_CAM_CTL0_LSB 0
A2W_HDMI_CTL_RCAL_RSTB_MSB 16
USB_HCSPLT0_SPLT_ENA_BITS 31:31
UART_LCR_LOOP_CLR 0xffffffef
FPGA_CTRL0_TERMEN_DO_LSB 16
I2C_SPI_SLV_IFLS_RXIFPSEL_BITS 11:9
A2W_PLLC_ANA_SCTL_RESET_LSB 4
USB_GINTMSK_MODE_MIS_MSB 1
AVE_IN_STATUS_EVEN_FIELD_SET 0x00000800
SD_CS_IDLE_CLR 0xfffffdff
DMA0_TI_INTEN_MSB 0
CCP2TX_TTC_BI_BITS 23:16
L1_L1_SANDBOX_START0_MASK 0x3fffffff
CM_PLLH_DIGRST_LSB 9
TXP_DIM_WIDTH_MSB 11
GP_AFEN2_AFENn64_BITS 5:0
USB_HCINT0_FRM_OVRUN_LSB 9
APERF1_BW1_CTRL_ID_EN_CLR 0xdfffffff
A2W_PLLC_CORE2R 0x7e102b20:RW
EMMC_STATUS_DAT_LEVEL1_LSB 25
SYSAC_DUMMY_STATUS 0x7e009060:RW
GROPCTRS11 0x1A005100 + 0x0DC:RW
VPU_ARB_CTRL_L2_DELAY_MSB 3
SD_RWC_MAXCNT_RESET 0x0
SD_DQRCRC11_RISE_CLR 0x0000ffff
UART_LSR_TEMT_BITS 6:6
DMA13_DEBUG_DMA_ID_SET 0x0000ff00
GP_EDS0_EDSn0_MSB 31
PM_AVS_EVENT_ALERT_SYSTEM_A_MSB 1
CAM1_CAMDBSA0_RESET 0000000000
DMA1_DEBUG_RESET 0000000000
APERF0_BW1_RPEND 0x7e009868:RO
SCALER_DISPPROF 0x7e400010:RW
MS_SEMA_11_MASK_LSB 0
A2W_PLLA_CTRL_PWRDN_BITS 16:16
APERF0_BW1_RTWAIT_MASK 0xffffffff
SLIM_DCC4_PROT_MASK 0xc001ffff
DMA8_TI_DEST_WIDTH_CLR 0xffffffdf
SH_CMD 0x7e202000:RW
L1_IC0_PRIORITY_IC0_APRIORITY2_CLR 0xfffff0ff
PM_IMAGE_POWOK_MSB 1
USB_DIEPTXF10 0x7e980128:RW
USB_DIEPTXF11 0x7e98012c:RW
USB_DIEPTXF12 0x7e980130:RW
USB_DIEPTXF13 0x7e980134:RW
USB_DIEPTXF14 0x7e980138:RW
USB_DIEPTXF15 0x7e98013c:RW
MPHI_TXAXICFG_MASK 0x0001ffff
GP_LEN1_MASK 0xffffffff
PM_IMAGE_MEMREP_CLR 0xfffffff7
SD_CS_SDUP_MSB 15
MPHI_C1INDS_DISCARD_BITS 31:31
PM_SPAREW_SPARE_CLR 0xff000000
CM_DSI1ECTL_FRAC_MSB 9
SMI_DC_PANICR_SET 0x00fc0000
SLIM_DCC1_CON_MASK 0xffff0070
HDMI_RAM_PACKET_12_1_MASK 0xffffffff
I2C0_C_MASK 0x00008701
A2W_PLLH_ANA0R_RESET 0x00d80000
MS_SEMA_0_MASK_CLR 0xfffffffe
CM_UARTCTL_SRC_MSB 3
SCALER_CONTEXT_MEM_SIZE ( 1024 * 16 )
CM_AVEOCTL_BUSYD_SET 0x00000100
PM_CAM1_LDOCTRL_LSB 3
HDMI_READ_POINTERS_DOMAIN_HALF_FULL_BITS 30:30
PM_DFT_ALLOWAUDIOCKSTOP_BITS 0:0
HD_MAI_CTL_EMPTY_MSB 10
INTERRUPT_TIMER0 ((64) + 0 )
HDMI_FIFO_CTL_USE_FULL_SET 0x00000002
PM_DSI0_LDOHPEN_SET 0x00000004
INTERRUPT_TIMER3 ((64) + 3 )
A2W_PLLD_ANA_SSCLR_WIDTH 17
CCP2TX_TD_IES_SET 0x00000060
A2W_SMPS_A_GAIN_DIGGAIN_SET 0x00000007
DMA14_TI_WAITS_MSB 25
HDMI_RAM_PACKET_11_4_WIDTH 32
AVE_IN_CTRL_BUF1_IRQ_EN_LSB 2
DMA2_CS_ACTIVE_MSB 0
UART_LCR_DLAB_BITS 7:7
V3D_PCS_WIDTH 9
DMA4_TI_DEST_WIDTH_BITS 5:5
AUX_SPI0_CNTL1_REG (0x7E215000 +0x084)
USB_GHWCFG4_NUM_CRL_EPS_SET 0x000f0000
A2W_SMPS_LDO0 0x7e1020d0:RW
A2W_SMPS_LDO1 0x7e1020d4:RW
MS_MBOX_2_RESET 0000000000
PIXELVALVE0_VSYNCD_EVEN_MASK 0x0001ffff
DPI_BASE 0x7e208000
DMA4_CONBLK_AD_MASK 0xffffffe0
DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
SD_SB_INHIBIT_LA_RESET 0x0
L1_D_CONTROL_DC0_FLUSH_MSB 1
DSI0_PHYC_dlane_hsen_1_sync_BITS 5:5
EMMC_INTERRUPT_ADMA_ERR_SET 0x02000000
A2W_PLLD_DSI1_RESET 0x00000100
OTP_VPU_CACHE_KEY_SIZE_IN_ROWS 4
A2W_PLLA_ANA0 0x7e102010:RW
A2W_PLLA_ANA1 0x7e102014:RW
A2W_PLLA_ANA2 0x7e102018:RW
A2W_PLLA_ANA3 0x7e10201c:RW
DMA8_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
SDRAM_START_ADDRESS 0
CAM0_CAMDAT1_MASK 0xffffffff
VEC_CPS2425_CPS2627_WIDTH 32
ASB_AXI_BRDG_VERSION_MASK 0x000000ff
DMA8_DEBUG_DMA_STATE_MSB 24
SYSAC_TRANS_PRIORITY_N_PRIORITY_RESET 0x0
USB_DIEPDMAB0_MASK 0xffffffff
TB_TASK_TXTCLR_MASK 0xffffffff
HDMI_CEC_CNTRL_2_WIDTH 31
AVE_OUT_CB_COEFF_BLUE_COEFF_MSB 9
CPG_Trigger 0x7e211008:RW
A2W_SMPS_LDO1_RESET 0000000000
UART_LSR_FE_LSB 3
USB_GINTMSK_WIDTH 32
SD_SE_RL_EN_MSB 28
V3D_DBGE_MASK 0xffffffff
SD_SECSRT2_EN_LSB 0
VEC_WSE_VPS_CONTROL_MASK 0xffffffff
DMA7_DEBUG_DMA_ID_MSB 15
PWM_DMAC_PANIC_CLR 0xffff00ff
HDMI_RAM_PACKET_13_1_RESET 0000000000
USB_DOEPINT3_MASK 0xffffffff
CM_DSI0PCTL_BUSY_MSB 7
CAM0_CAMIPIPE_RESET 0000000000
MPHI_OUTDDB_HANDLE_LSB 20
DMA6_TI_WAITS_CLR 0xfc1fffff
SYSAC_V3D_LIMITER_ENABLE_MSB 0
SD_DQLCRC2_FALL_LSB 0
DMA15_TI_DEST_IGNORE_BITS 7:7
PCMCS_TXON (1 << 2)
SCALER_DISPCTL_0 0x7e400000 + 0x40:RW
SCALER_DISPCTL_1 0x7e400000 + 0x50:RW
SCALER_DISPCTL_2 0x7e400000 + 0x60:RW
PCM_GRAY_CLR_LSB 1
DMA14_DEBUG_VERSION_MSB 27
A2W_PLLC_ANA_STAT_WIDTH 12
CAM0_CAMDBSA1_WIDTH 32
DMA13_CONBLK_AD_SCB_ADDR_BITS 31:5
A2W_PLLB_SP0R 0x7e102ce0:RW
EMMC_CMDTM_TM_AUTO_CMD_EN_MSB 3
OTP_BOOTMODE_REG_WIDTH 32
PWMFIF1 0x7e20c000 + 0x18:RW
I2CDEL_FEDL (16)
A2W_PLLA_ANA_SCTLR 0x7e102d10:RW
EMMC_RESP2_MASK 0xffffffff
USB_GHWCFG2_FSPHY_INTERFACE_CLR 0xfffffcff
L1_D_PRIORITY 0x7ee0210c:RW
I2C_SPI_SLV_CR_RXE_BITS 9:9
A2W_PLLC_ANA_SSCS_STEP_CLR 0xffff0000
VPU_ARB_CTRL_L2_ALGORITHM_RESET 0x0
SYSAC_JPEG_PRIORITY_P_PRIORITY_RESET 0x0
I2C_SPI_SLV_FR_RXBUSY_LSB 5
CM_GP1CTL_KILL_MSB 5
USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_MSB 23
HD_MAI_CTL_FULL_MSB 11
DSI1_HS_CLT2_WIDTH 32
DMA1_NEXTCONBK_ADDR_BITS 31:5
USB_GRSTCTL_TXF_FLSH_CLR 0xffffffdf
INTERRUPT_ASDIO ((64) + 62 )
USB_DIEPDMAB12_MASK 0xffffffff
ASB_H264_S_CTRL_EMPTY_MSB 2
GP_FSEL0_FSEL06_MSB 20
DMA10_DEBUG_VERSION_MSB 27
HDCP_KEY_CTL_START_LSB 0
DMA11_DEBUG_READ_ERROR_LSB 2
EMMC_CONTROL1_CLK_INTLEN_LSB 0
A2W_PLLB_SP1R 0x7e102de0:RW
GP_FSEL2_FSEL27_CLR 0xff1fffff
HDMI_POSTING_MASTER_RESET 0x000000ff
SD_DQLCRC9_RISE_BITS 31:16
AVE_IN_MAX_TRANSFER_RESET 0000000000
USB_DIEPCTL10_MASK 0xffffffff
CM_PLLTCTL_KILL_SET 0x00000020
CAM0_CAMDBEA0 0x7e800208:RW
CAM0_CAMDBEA1 0x7e800314:RW
SD_DQRCRC4_FALL_RESET 0x0
MPHI_HSINDS_WORDS_LSB 0
EMMC_CONTROL2_SIGTYPE_SET 0x00080000
TE_0TIMER_MASK 0xffffffff
EMMC_SLOTISR_VER_SDVERSION_CLR 0xff00ffff
EMMC_CONTROL2_DRVTYPE_BITS 21:20
MS_VPU_STAT_WIDTH 24
CCP2TX_TTC 0x7e001018:RW
MPHI_CTRL_REQ_SOFT_RST_CLR 0xfffeffff
PM_PADS4_POWOK_CLR 0xffffffdf
MPHI_OUTDDB_CHANNEL_SET 0x10000000
DMA11_CS_WIDTH 32
DSI1_BASE 0x7e700000
EMMC_IRPT_EN_CARD_IN_SET 0x00000040
I2C_SPI_SLV_DR_RXDMABREQ_LSB 13
APERF1_BW0_WMAX_WIDTH 24
CM_TD0CTL_ENAB_CLR 0xffffffef
EMMC_CONTROL0_PWCTL_ON_SET 0x00000100
HDMI_RAM_PACKET_9_7_MASK 0xffffffff
A2W_PLLD_CTRL_PWRDN_MSB 16
CAM1_CAMIHSTA_MASK 0xffffffff
I2C_SPI_SLV_IFLS_TXIFLSEL_SET 0x00000007
PIARBCTL_CAM_ALGORITHM_SET 0x000000c0
A2W_PLLB_ANA2_WIDTH 24
HDMI_DETECTED_HORZB_MANUAL_HBP_MSB 29
ARM_IE_MAIL 0x00000002
HDMI_DETECTED_VERTA1_MANUAL_VSP1_SET 0x01f00000
CM_DSI1PCTL_ENAB_MSB 4
IC0_MASK0_RESET 0000000000
A2W_PLLB_SP2R 0x7e102ee0:RW
AVE_IN_CURRENT_ADDRESS_CUR_ADDR_MSB 31
SH_HCFG_WIDE_INT_BUS_LSB 1
EMMC_HWMAXAMP0_AMP_30V_CLR 0xffff00ff
DMA6_TI_NO_WIDE_BURSTS_BITS 26:26
SCALER_DISPGAMADR 0x7e400078:RW
A2W_PLLD_ANA1R_WIDTH 24
CM_DSI1ECTL_BUSY_BITS 7:7
USB_DIEPCTL4_WIDTH 32
DMA11_CS_PANIC_PRIORITY_LSB 20
APERF1_BW0_CTRL_LATHALT_BITS 28:28
EMMC_IRPT_MASK_DCRC_ERR_CLR 0xffdfffff
DSI0_HS_CLT0_RESET 0000000000
CM_GP0CTL_SRC_LSB 0
MS_SEMA_28_MASK_MSB 0
PM_PADS2_DRIVE_BITS 2:0
SPICLK SPI_BASE_ADDRESS + 0x08:RW
DMA14_CONBLK_AD 0x7e007e04:RW
EMMC_FORCE_IRPT_CARD_IN_SET 0x00000040
PWM_STA_GAPO3_SET 0x00000040
DMA7_CS_ERROR_MSB 8
MPHI_C0INDFS_CFIFOLVL_RESET 0x0
DMA9_DEBUG_LITE_BITS 28:28
HDMI_TX_PHY_TX_PHY_TMDS_CFG 0x7e9022d4:RW
GP_FSEL1_FSEL16_SET 0x001c0000
AVE_OUT_CTRL_INVERT_VSYNC_CLR 0xffff7fff
A2W_PLLC_PER_DIV_MSB 7
TB_BOOT_OPT_NO_PRINT_MSB 6
A2W_PLLH_ANA0_MASK 0x00ffffff
USB_DAINTMSK 0x7e98081c:RW
USB_GUSBCFG_PHY_LPWR_CLK_SEL_SET 0x00008000
CM_SMIDIV_MASK 0x0000fff0
SLIM_MC_IN_CON 0x7e210100:RW
CM_CAM1DIV_DIV_LSB 4
AVE_IN_STATUS 0x7e910004:RW
USB_DCTL_PWRON_PRG_DONE_RESET 0x0
SD_CARCRC_FALL_SET 0x0000ffff
I2C_SPI_SLV_RIS_RXRIS_LSB 0
AVE_OUT_STATUS_HFRONT_PORCH_BITS 4:4
HDMI_RAM_PACKET_9_2_MASK 0xffffffff
SD_MR_TIMEOUT_RESET 0x0
USB_DCFG_PER_FR_INT_MSB 12
MS_SEMA_18_MASK_LSB 0
CM_PWMCTL_BUSYD_BITS 8:8
CM_PLLTCNT0_CNT_MSB 23
CM_SDCCTL_ACCPT_LSB 16
CM_INTEN_RESUS_LSB 22
HDMI_RAM_PACKET_3_1_MASK 0xffffffff
FPGA_CTRL0_SW_SPI_SCL_SET 0x00000040
PWM_STA_WERR1_MSB 2
DPI_C 0x7e208000:RW
I2C_SPI_SLV_VCSTAT_DATA_MSB 3
PM_GNRIC_MEMREP_LSB 3
HDMI_HORZB_WIDTH 30
CAM1_CAMANA 0x7e801008:RW
V3D_CT0CA 0x7ec00000 +0x0110:RW
EMMC_HWCAP0_BUS64_MSB 28
SMIFD_FCNT 0
SMI_DCS_DONE_LSB 2
MPHI_HSINDCF_LENGTH_LSB 0
CM_TSENSCTL_BUSYD_SET 0x00000100
SD_DQLCRC1_FALL_BITS 15:0
PWM_CTL_POLA2_MSB 12
GP_AJBCONF 0x7e2000c0:RW
USB_DOEPINT0_AHB_ERR_SET 0x00000004
FPGA_MB_XC0_BUILD_NUM_WIDTH 32
APERF0_BW2_CTRL_BUS_MSB 4
V3D_CT0CS 0x7ec00000 +0x0100:RW
SLIM_DCC8_CON_MASK 0xffff0070
CCP2TX_TAC_PTATADJ_MSB 27
CM_TD0CTL_STEP_BITS 12:12
HDMI_SCHEDULER_CONTROL_VSYNC_PHYST_EN_MSB 17
DMA_INT_STATUS_INT1_CLR 0xfffffffd
SMI_DSW2_WHOLD_BITS 21:16
MS_SEMA_7_MASK_CLR 0xfffffffe
USB_DIEPDMA15_WIDTH 32
GP_SEN1_SEN_BITS 21:0
SD_CS_SREF2RUN_SET 0x00000100
APERF0_BW2_CTRL_WIDTH 32
CAM1_CAMDAT3_RESET 0x00000002
IC1_S_MASK 0x073f073f
EMMC_IRPT_EN_READ_RDY_SET 0x00000020
PM_GNRIC_RSTN_BITS 11:6
L2_SD_STALLS_MASK 0xffffffff
SD_SD_T_RPpb_RESET 0x8
H264_APB_ID 0x68323634
A2W_PLLC_ANA_SCTL 0x7e102530:RW
APERF0_GEN_CTRL_RESET_CLR 0xfffffffd
USB_HPRT_PWR_BITS 12:12
USB_GNPTXFSIZ 0x7e980028:RW
PM_PADS4_HYST_SET 0x00000008
DMA4_CS_RESET_LSB 31
SLIM_DMA_MC_RX_RESET 0000000000
A2W_PLLB_DIG3R_MASK 0x00ffffff
APERF0_BW1_CTRL_RESET_RESET 0x0
USB_DIEPTSIZ5_MASK 0xffffffff
DSI_CTRL 0x7e209000 + 0x00:RW
CAM1_CAMISTA_MASK 0xffffffff
GP_FSEL4_FSEL45_SET 0x00038000
A2W_XOSC_CTRL_HDMIOK_CLR 0xffffdfff
GP_FSEL0_FSEL02_LSB 6
CCP2TX_TBA_ADDR_MSB 29
L2_CONT_OFF_l2_disable_MSB 0
A2W_PLLA_CCP2_DIV_CLR 0xffffff00
CM_DSI0ECTL_KILL_MSB 5
IC1_MASK4_MASK 0x77777777
CM_DSI1PDIV 0x7e101164:RO
DMA3_TI_WAITS_LSB 21
MPHI_C0INDDB_MASK 0xffffffff
USB_GHWCFG4_EN_PWROPT_MSB 4
DMA14_CS_END_BITS 1:1
A2W_PLLC_CORE0_DIV_MSB 7
EMMC_STATUS_READ_TRANSFER_BITS 9:9
DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
DMA15_CS_DREQ_SET 0x00000008
V3D_CT0EA 0x7ec00000 +0x0108:RW
PCM_INTSTC_A_RXERR_MSB 3
EMMC_INTERRUPT_INT_B_SET 0x00000400
AUX_SPI0_STAT_REG (0x7E215000 +0x088)
CM_PULSECTL_ENAB_SET 0x00000010
DMA0_STRIDE_D_STRIDE_SET 0xffff0000
SD_SA_RFSH_T_CLR 0x0000ffff
TXP_DIM_WIDTH_SET 0x00000fff
SMI_DSR0_RPACE_LSB 8
I2C_SPI_SLV_FR_RESET 0x00000012
USB_DOEPINT0_OUT_PKT_ERR_CLR 0xfffffeff
A2W_PLLD_DSI0_BYPEN_MSB 9
A2W_PLLB_SP0_CHENB_MSB 8
DMA_ENABLE_EN13_LSB 13
MS_MBOX_0_WIDTH 32
PM_DSI1_WIDTH 21
APERF0_BW2_WMAX_WIDTH 28
DMA13_SOURCE_AD 0x7e007d0c:RO
PCMCS_TXD (1 << 19)
PCMCS_TXE (1 << 21)
DMA3_DEBUG_DMA_STATE_CLR 0xfe00ffff
HD_HDM_CTL_SW_RST_BITS 2:2
DMA14_CS_DISDEBUG_BITS 29:29
A2W_HDMI_CTL2_MASK 0x00ffffff
DMA14_TXFR_LEN_XLENGTH_CLR 0xffff0000
A2W_HDMI_CTL_HFEN_MASK 0x00000001
CM_CKSM_CFG_SET 0x00030000
PCMCS_TXW (1 << 17)
SD_DQLCRC12_RISE_LSB 16
DMA6_CS_PAUSED_SET 0x00000010
SD_DQLCRC9_FALL_LSB 0
DPHY_CSR_DQ_PHY_READ_CTRL 0x7ee07064:RW
A2W_HDMI_CTL0_RESET 0x00470238
MS_MBOX_2_MBOX_MSB 31
PCM_CH1EN (1 << 30)
TXP_DST_PITCH_MASK 0xfffffff0
CM_DSI1PCTL_SRC_BITS 3:0
GP_FEN1_FENn32_BITS 31:0
CM_H264CTL_BUSY_SET 0x00000080
DSI0_CTRL_CTRL0_MSB 0
AVE_IN_LINE_LENGTH_LINE_LENGTH_MSB 11
HDMI_RAM_PACKET_10_8_MASK 0xffffffff
A2W_SMPS_C_CLK_RESET 0000000000
PM_PADS0_SLEW_MSB 4
EMMC_STATUS_DAT_INHIBIT_CLR 0xfffffffd
MPHI_MOUTFS_RPTR_RESET 0x0
USB_GUSBCFG_ULPI_FS_LS_RESET 0x0
USB_GPVNDCTL_REG_DATA_MSB 7
SD_SD_T_RC_LSB 20
A2W_PLLA_ANA_SSCS_STEP_BITS 15:0
OTP_CONTROL_ROW ((8 +4)+4)
AVE_IN_CTRL_PRIV_MODE_LSB 7
AVE_IN_CTRL_FRAME_RATE_IRQ_EN_BITS 6:6
PWMDMAC_ENAB 31
USB_GNPTXSTS_TXF_SPC_AVAIL_CLR 0xffff0000
CM_GP1CTL_BUSYD_LSB 8
PM_AVS_INTEN_ALERT_H264_I_BITS 2:2
L1_IC0_BP_MISSES_WIDTH 0
SD_DQRCRC1_FALL_RESET 0x0
A2W_PLLA_CORE_DIV_LSB 0
HDMI_CP_INTEGRITY_WIDTH 32
EMMC_BUS_CTRL_IRQ_PINS_LSB 3
TB_PRINTER_CTRL_TASKNO_CLR 0xffff000f
V3D_CT0CA_WIDTH 32
PM_CCP2TX_LDOCTRL_LSB 2
GP_FSEL6_FSEL69_LSB 27
APERF0_BW0_CTRL_EN_LSB 30
SD_DQRCRC10_WIDTH 32
CM_TSENSCTL_ENAB_SET 0x00000010
A2W_PLLB_CTRL_PWRDN_BITS 16:16
USB_PCGCR_STOP_PCLK_RESET 0x0
USB_DIEPCTL0_SET_D1_PID_RESET 0x0
PIXELVALVE2_STAT_MASK 0x000003ff
USB_DOEPCTL7_MASK 0xffffffff
A2W_SMPS_B_STAT_BSTPWMB_BITS 8:8
EMMC_IRPT_MASK_RETUNE_SET 0x00001000
CM_LOCK_LOCKC_BITS 2:2
HDMI_RAM_PACKET_5_5_MASK 0xffffffff
HD_CSC_12_11_MASK 0xffffffff
I2C_SPI_SLV_MIS_OEMIS_MSB 3
EMMC_HWCAP1_DDR50_SET 0x00000004
SYSAC_SRC_ARBITER_CONTROL_DELAY_MSB 3
GP_EDS2_WIDTH 6
A2W_HDMI_CTL_MULTI_MASK 0000000000
GP_FEN1_FENn32_MSB 31
USB_DIEPTXF8_MASK 0xffffffff
VPU_ARB_CTRL_UC_ALGORITHM_SET 0x000000c0
CPG_Trigger_MASK 0x00000003
EMMC_INTERRUPT_CARD_OUT_BITS 7:7
A2W_PLLD_ANA_KAIPR 0x7e102b50:RW
CM_PLLB_DIGRST_LSB 9
SYSAC_V3D_LIMITER_RESET 0000000000
A2W_XOSC_PWR_RSTB_CLR 0xfffffffb
PCM_CS_A_TXW_CLR 0xfffdffff
DMA9_CS_MASK 0xf0ff017f
DMA6_TI_SRC_WIDTH_BITS 9:9
DMA12_CS_PAUSED_LSB 4
USB_GPVNDCTL_NEW_REG_REQ_RESET 0x0
INTERRUPT_RNG ((64) + 61 )
A2W_SMPS_CTLA0_RESET 0000000000
ARM_3_BELL0 (0x7E00B000 +0xB00)+0x40:RW
ARM_3_BELL1 (0x7E00B000 +0xB00)+0x44:RW
MS_MBOX_0_MBOX_BITS 31:0
ARM_3_BELL3 (0x7E00B000 +0xB00)+0x4C:RW
CM_H264CTL 0x7e101028:RW
USB_GI2CCTL_BSY_DNE_RESET 0x0
DMA7_TI_SRC_IGNORE_SET 0x00000800
SMI_DSW1_WSTROBE_SET 0x0000007f
GROCS 0x1A005000:RW
SD_CS_ASHDNE_BITS 17:17
ARM_IE_TIMER 0x00000001
A2W_PLLC_CORE1_CHENB_BITS 8:8
CM_CAM0DIV_DIV_BITS 15:4
USB_DIEPINT13_WIDTH 32
UNICAM_IDC(x) MACRO
APERF0_BW1_WTRANS_RESET 0000000000
DMA12_DEBUG 0x7e007c20:RW
A2W_PLLB_SP0_BYPEN_CLR 0xfffffdff
DMA14_TI_INTEN_LSB 0
EMMC_IRPT_EN_CMD_DONE_SET 0x00000001
SLIM_DCC8_STAT_RESET 0000000000
A2W_PLLH_ANA_STAT_RCALDONE_MSB 12
A2W_PLLH_ANA_KAIP_KA_BITS 10:8
USB_GI2CCTL_RW_RESET 0x0
SMI_DC_DMAP_CLR 0xfeffffff
HDMI_VERTA0_MASK 0x01ffffff
IC0CS 0x7ee02000:RW
DMA4_STRIDE_S_STRIDE_SET 0x0000ffff
L2_DESCRIPTION "VC4-L2 control"
A2W_PLLH_PIX_CHENB_CLR 0xfffffeff
PM_AVS_STAT_ALERT_V3D_G_MSB 3
SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_LSB 4
USB_HPRT_SUSP_CLR 0xffffff7f
MPHI_C0INDDB_MENDINT_RESET 0x0
HDMI_RAM_PACKET_13_6_WIDTH 32
SD_DQRCRC13_RISE_CLR 0x0000ffff
MPHI_C1INDDB_HANDLE_BITS 27:20
SMI_DSW2_WPACEALL_BITS 15:15
HD_FRAME_CNT 0x7e808068:RW
DMA4_CS_END_CLR 0xfffffffd
L1_D0_RD_SNOOPS_WIDTH 0
CAM0_CAMIBEA1_WIDTH 32
DMA15_CS_PANIC_PRIORITY_LSB 20
DMA12_TI_SRC_INC_LSB 8
VEC_CONFIG3_WIDTH 32
DMA15_CS_END_MSB 1
PM_CCP2TX_RESET 0000000000
DMA6_TI_PERMAP_SET 0x001f0000
CM_PLLA_MASK 0x000003ff
HD_MAI_THR_PANICHIGH_RESET 0x1
EMMC_CMDTM_CMD_RSPNS_TYPE_BITS 17:16
DMA12_TI_SRC_WIDTH_MSB 9
DMA10_TXFR_LEN_XLENGTH_MSB 15
CM_GNRICCTL_BUSY_MSB 7
HDMI_PERT_TEST_LENGTH_WIDTH 32
SD_SC_T_WR_LSB 8
SD_CS_EXCEPTION_MSB 23
HDMI_TX_PHY_TX_PHY_CTL_2_RESET 0x00a63004
MS_SEMA_25_RESET 0000000000
USB_GHWCFG2_DFIFO_DYNAMIC_CLR 0xfff7ffff
FPGA_CTRL0_TERMEN_CLK_SET 0x00020000
UART_MSR_DCTS_SET 0x00000001
DMA0_TI_DEST_WIDTH_MSB 5
SD_CS_STBY_LSB 3
TRANSPOSER_DST_PTR 0x7e004000:RW
TXP_CTRL_TRANSPOSE_CLR 0xffffffbf
PM_DSI1_LDOHPEN_MSB 2
APERF0_BW0_RTRANS 0x7e00985c:RO
DMA7_TI_WAIT_RESP_LSB 3
SD_MR_MASK 0xf0ffffff
SD_DQLCRC0_RISE_SET 0xffff0000
DMA9_TXFR_LEN_WIDTH 16
HDMI_READ_POINTERS_DOMAIN_WR_ADDR_CLR 0xc7ffffff
DMA10_CS_ERROR_CLR 0xfffffeff
USB_DOEPCTL0_TYPE_SET 0x000c0000
AVE_IN_OVERRUN_ADDRESS 0x7e910028:RW
DMA6_DEBUG_FIFO_ERROR_LSB 1
AVE_IN_CTRL 0x7e910000:RW
MPHI_INTCTRL_OMFUFLW_LSB 12
SLIM_DCC7_PA0 0x7e2102e0:RW
SLIM_DCC7_PA1 0x7e2102e4:RW
DMA13_TI_SRC_IGNORE_SET 0x00000800
CM_V3DCTL_GATE_LSB 6
PWMSTA 0x7e20c000 + 0x04:RW
GP_FSEL4_FSEL41_MSB 5
PM_CCP2TX_CTRLEN_SET 0x00000001
HDMI_PERT_INSERT_ERR 0x7e902080:RW
HDMI_RAM_PACKET_9_6_RESET 0000000000
CAM1_CAMDAT1_WIDTH 32
ARM_C0_SWDBGREQ 0x00040000
V3D_CT0LC 0x7ec00000 +0x0120:RW
CM_CAM1CTL_KILL_LSB 5
EMMC_STATUS_CMD_LEVEL_BITS 24:24
HDMI_SCHEDULER_CONTROL_HSYNC_PHYST_EN_LSB 16
PM_DFT_STOPALLCLOCKS_BITS 1:1
SMI_DSR2_RHOLD_CLR 0xffc0ffff
INTERRUPT_SPI ((64) + 54 )
A2W_PLLB_ANA_VCO_MASK 0x00000001
CM_TECCTL_BUSYD_SET 0x00000100
USB_PCGCR_RST_PDWN_MODULE_LSB 3
USB_DOEPCTL9_WIDTH 32
GR_UNIFORM_ADDR_MASK 0x00000fff
L1_IC1_PRIORITY_IC1_APRIORITY0_SET 0x0000000f
SD_SECEND1_ADDR_MS_BITS 31:13
SD_CS_STATEN_MSB 6
V3D_BPCA 0x7ec00000 +0x0300:RW
USB_DPTXFSIZ2 0x7e980108:RW
USB_DPTXFSIZ3 0x7e98010c:RW
USB_DPTXFSIZ4 0x7e980110:RW
USB_DPTXFSIZ5 0x7e980114:RW
USB_DPTXFSIZ6 0x7e980118:RW
USB_DPTXFSIZ7 0x7e98011c:RW
USB_DPTXFSIZ8 0x7e980120:RW
USB_DOEPDMA2_MASK 0xffffffff
PCM_MODE_A_CLKI_BITS 22:22
SD_SE_RL_MSB 25
ARM_3_MAIL1_WRT (0x7E00B000 +0xB00)+0xA0:RW
V3D_BPCS 0x7ec00000 +0x0304:RW
USB_DIEPINT0_SETUP_RESET 0x0
CSI2_RS_x(x) MACRO
APERF0_BW1_CTRL_RESET_SET 0x80000000
DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
CM_PLLA_HOLDDSI0_CLR 0xfffffffd
A2W_SMPS_C_CTL_RESET 0000000000
SLIM_STAT_WIDTH 26
DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
A2W_PLLB_ANA_KAIP_KP_BITS 3:0
SLIM_DCC4_PROT_WIDTH 32
APERF0_BW0_RMAX_RESET 0000000000
L1_D0_RD_SNOOPS_MASK 0000000000
VEC_ENC_PrimaryControl_WIDTH 32
HDCP_KEY_CTL_START_RESET 0x0
SLIM_DRX_DMA ( 9*(1<<16))
I2C2_DLEN_MASK 0x0000ffff
GROPCTR_FBC_EZ_PBE_HITS 0x37
HDMI_RAM_PACKET_1_8_MASK 0xffffffff
CM_SDCCTL_BUSYD_BITS 8:8
EMMC_INTERRUPT_ADMA_ERR_MSB 25
CCP2TX_TC_WIDTH 32
EMMC_CONTROL0_GAP_RESTART_BITS 17:17
DMA0_CS_INT_BITS 2:2
SCALER_DISPCTRL2_MASK 0xffffffff
HD_HDM_CTL_CECOVR_CLR 0xfffffeff
GP_FSEL5_FSEL51_SET 0x00000038
CM_TD0CTL_BUSYD_LSB 8
PM_IMAGE_ISPRSTN_LSB 8
SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_RESET 0x0
SD_SECEND2_ADDR_LS_MSB 12
I2C1_C_RESET 0000000000
SD_DQRCRC2_RISE_SET 0xffff0000
HDMI_PCI_STATUS (HDMI_BASE_ADDRESS + 0x340) + 0x18:RW
I2C_SPI_SLV_FR_RXFLEVEL_SET 0x0000f800
DMA14_DEBUG_RESET 0000000000
CAM0_CAMDBSA0_MASK 0xffffffff
I2C_SPI_SLV_IMSC_TXIM_BITS 1:1
TB_TASK_NUM_CLR 0xffff0000
CM_DFTDIV_MASK 0x0001f000
SD_CS_STOP_RESET 0x0
CM_INTEN_GAINH_MSB 4
VPU_ARB_CTRL_UC_THRESHOLD_CLR 0xffffffcf
GP_CLR2_MASK 0x0000003f
FPGA_DCM_CTRL_PERI_RST_SET 0x000f0000
CM_TD1CTL_FLIP_MSB 11
AVE_IN_BUF1_ADDRESS_BUF1_ADDR_CLR 0x00000000
CM_AVEOCTL_KILL_LSB 5
PM_HDMI_LDOPD_SET 0x00000002
IC1_FORCE0_SET 0x7e002848:RW
EMMC_IRPT_EN_CARD_SET 0x00000100
CMMSP 0x7C:RW
HDMI_VERTB0_MANUAL_VSPO0_MSB 21
CM_TDCLKEN_SLIMDFT_LSB 12
DMA11_DEBUG_READ_ERROR_BITS 2:2
DMA7_TI_INTEN_SET 0x00000001
DMA_INT_STATUS_INT12_CLR 0xffffefff
USB_GUSBCFG_HNP_CAP_SET 0x00000200
SYSAC_UC_ARBITER_CONTROL_ALGORITHM_LSB 6
CM_UARTCTL_FRAC_MSB 9
PM_GNRIC_CFG_SET 0x007f0000
USB_GHWCFG4_EN_B_VALID_FILTER_CLR 0xff7fffff
SD_RWC_LASTCNT_LSB 16
USB_GUSBCFG_TOUT_CAL_SET 0x00000007
SMI_DSR2_RPACEALL_CLR 0xffff7fff
PM_AVS_RSTDR_WIDTH 6
CM_ISPDIV_DIV_MSB 15
I2C0_CLKT 0x7e20501c:RW
DMA5_TI_DEST_INC_SET 0x00000010
FPGA_MB_XC1_BUILD_NUM_WIDTH 32
CAM1_CAMDBEA1_WIDTH 32
MPHI_MINFS_RPTR_CLR 0xc00fffff
USB_HCINT0_DATA_TGL_ERR_LSB 10
GR_PSE_ADDR_MASK 0x0000007f
TE_1VSWIDTH 0x7e20e010:RW
SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_RESET 0x0
UART_MSR_TERI_BITS 2:2
A2W_XOSC_CTRL_DDROK_BITS 16:16
SD_MR_ADDR_CLR 0xffffff00
V3D_CT0PC 0x7ec00000 +0x0128:RW
DMA4_TI_SRC_WIDTH_CLR 0xfffffdff
SD_DQRCRC11_FALL_CLR 0xffff0000
CM_CAM1CTL_ENAB_SET 0x00000010
DMA2_DEBUG_VERSION_CLR 0xf1ffffff
MPHI_C1INDFS_CFIFOLVL_MSB 31
HDMI_CTS_PERIOD_1_WIDTH 32
MPHI_C0INDS_DISCARD_LSB 31
PWM_CTL_SBIT1_MSB 3
SLIM_DCC5_STAT_RESET 0000000000
FPGA_STATUS0_SD_CD_LSB 5
DMA4_TI_DEST_INC_SET 0x00000010
L1_IC0_CONTROL_DISABLE_VLINE_CLR 0xffffff9f
USB_HCINT0_ACK_MSB 5
A2W_XOSC_CTRL_USBOK_CLR 0xffffbfff
CM_V3DCTL_BUSYD_CLR 0xfffffeff
DMA8_DEBUG_LITE_SET 0x10000000
HDCP_KEY_KY1_RESET 0000000000
PIXELVALVE0_VC 0x7e206004:RW
RNG_STATUS_WIDTH 32
AVE_IN_CURRENT_LINE_BUF0_MASK 0x80000fff
VEC_WSE_VPS_DATA_1_MASK 0xffffffff
CCP2TX_TS_TII_MSB 17
PM_AVS_RSTDR_ARM_P_BITS 4:4
SMI_DSR2_RPACE_MSB 14
CM_TD1CTL_FRAC_LSB 9
HDCP_KEY_CTL_START_BITS 0:0
A2W_PLLA_CORE_BYPEN_LSB 9
MS_SEMA_22_MASK_CLR 0xfffffffe
DMA1_CS_ABORT_LSB 30
DSI0_TST_SEL_RESET 0000000000
DEBUG_MASTER_BASE 0x7e008000
AJB_ENABLE 0x000800
A2W_PLLH_CTRL_PDIV_SET 0x00007000
A2W_PLLB_ANA_SSCLR_MASK 0x0001ffff
SD_MRT_T_MRW_CLR 0xfffffe00
DMA15_STRIDE_D_STRIDE_BITS 31:16
DMA0_TI_TDMODE_CLR 0xfffffffd
DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
MPHI_HSINDCF_HANDLE_CLR 0xf00fffff
ARM_MYIRQ_MAIL 0x00000002
CM_INTEN_FLOSSB_MSB 15
DMA15_SOURCE_AD_S_ADDR_LSB 0
ASB_ISP_S_CTRL_EMPTY_SET 0x00000004
DMA15_DEST_AD_D_ADDR_CLR 0x00000000
PWM_STA_GAPO4_LSB 7
USB_HPTXSTS_HPTXQTOP_RESET 0x0
TE_APB_ID 0x00746563
DSI1_HSTX_TO_CNT_RESET 0000000000
GP_FSEL1_FSEL17_LSB 21
SMI_DSR3_RDREQ_BITS 7:7
DMA14_TI_DEST_IGNORE_MSB 7
APERF1_BW1_CTRL_MASK 0xf0001f1f
SD_SECSRT3_ADDR_MS_LSB 13
A2W_PLLC_PER_WIDTH 10
I2C_SPI_SLV_DMACR_RXDMAE_CLR 0xfffffffe
PCM_CS_A_TXCLR_SET 0x00000008
SMI_DSR1_RPACE_LSB 8
SD_SECSRT2_ADDR_LS_SET 0x00001ffe
MPHI_OUTDFS_MASK 0xffffffff
PIARBCTL_CAM_CHANNEL_INIBIT_SET 0x0000ff00
AUX_MU_STAT_RXFILL 0x00FF0000
DMA13_TI_SRC_INC_MSB 8
CAM1_CAMIBSA1_RESET 0000000000
SDTMC 0x7ee0007c:RW
DMA_INT_STATUS_INT5_SET 0x00000020
PIXELVALVE2_VSYNCD_EVEN_WIDTH 17
SYSAC_PERI_ARBITER_CONTROL_LIMIT_LSB 0
SPI_LTOH_RESET 0x00000001
USB_GI2CCTL_DEV_ADR_BITS 27:26
USB_DIEPTSIZ0_XFERSIZE_SET 0x0007ffff
HD_MAI_THR_PANICHIGH_MSB 29
CM_BURSTCTL_KILL_LSB 5
PIXELVALVE1_DSI_HACT_ACT_WIDTH 16
APERF1_BW1_CTRL_BUS_RESET 0x0
EMMC_TUNE_STEP_DELAY_MSB 2
GP_LEV1_LEVn32_BITS 31:0
USB_DCTL_CGNP_IN_NAK_MSB 8
USB_DIEPTSIZ10_MASK 0xffffffff
MPHI_C1INDCF_HANDLE_MSB 27
EMMC_CONTROL0_MASK 0x07ff1fff
PCM_RXC_A_RESET 0000000000
HD_HDM_CTL_PDSTBY_LSB 4
PM_RSTC_DRCFG_CLR 0xfffffffc
PCM_MODE_A_CLKM_CLR 0xff7fffff
CM_INTEN_GAINC_SET 0x00000004
USB_HCTSIZ4_MASK 0xffffffff
SCALER_DISPPROF_WIDTH 32
PM_AVS_STAT_ALERT_ARM_P_SET 0x00000010
HDMI_TX_PHY_TX_PHY_CTL_0_WIDTH 32
EMMC_HWCAP1_SPI_MODE_MSB 24
MS_SEMA_23_WIDTH 1
PM_PROC_ISPOW_BITS 2:2
USB_DOEPCTL0_MPS_SET 0x000007ff
USB_DAINT_OUT_EP_INT_CLR 0x0000ffff
CM_UARTCTL_FRAC_LSB 9
SDVDD SDCARD_BASE + 0x30:RW
A2W_PLLB_ANA_SCTLR_MASK 0x0000001f
USB_DIEPCTL0_SNP_MSB 20
CM_ISPCTL_SRC_CLR 0xfffffff0
USB_GINTMSK_PRT_INT_LSB 24
I2C_SPI_SLV_DR_TXBUSY_MSB 16
DMA15_DEBUG_VERSION_MSB 27
EMMC_IRPT_MASK_INT_B_SET 0x00000400
CM_EVENT_BURSTDONE_SET 0x00800000
APERF1_BW1_WTRANS_WIDTH 32
USB_HAINT_WIDTH 32
SLIM_DCC7_PROT_RESET 0x000093a0
PWM_STA_STA4_MSB 12
DMA3_DEBUG_FIFO_ERROR_CLR 0xfffffffd
I2C_SPI_SLV_RIS_OERIS_MSB 3
EMMC_IRPT_MASK_ENDBOOT_SET 0x00004000
A2W_PLLC_CTRL_PWRDN_BITS 16:16
HD_CSC_CTL_ENABLE_MSB 0
DMA5_BASE 0x7e007500
UART_LCR_RTS_SET 0x00000002
MPHI_INTSTAT_OMFUFLW_MSB 28
A2W_PLLH_CTRL_PDIV_BITS 14:12
CPG_Debug2_MASK 0xffffffff
DMA12_CS_PANIC_PRIORITY_BITS 23:20
DMA12_TI_DEST_IGNORE_MSB 7
SD_SECSRT3_EN_MSB 0
SCALER_DISPECTRL_CR_NE_CTRL_BITS 31:30
GP_AFEN0_RESET 0000000000
USB_GINTMSK_EP_MIS_MSB 17
DSI0_PHYC_clane_hsen_sync_SET 0x00000100
DMA0_BASE 0x7e007000
HDMI_RAM_PACKET_5_6_WIDTH 32
SMI_DSW3_WSWAP_LSB 22
PM_PROC_POWUP_SET 0x00000001
PM_PXBG_CTRL_CLR 0xffff0000
SYSAC_PERI_ARBITER_CONTROL_DELAY_SET 0x0000000c
I2C_SPI_SLV_FR_RXFLEVEL_CLR 0xffff07ff
DMA3_TI_DEST_DREQ_LSB 6
USB_GUSBCFG_SRP_CAP_CLR 0xfffffeff
A2W_PLLC_ANA_KAIP_KI_MSB 6
DMA14_NEXTCONBK_MASK 0xffffffe0
SCALER_DISPSTAT_DMA_ERR_BIT1_MSB 31
USB_DTHRCTL_NON_ISO_THR_EN_LSB 0
DMA_TI_D_IGNORE (1<<7)
USB_GHWCFG2_MASK 0x7fcfffff
DMA1_DEBUG_LITE_MSB 28
USB_DIEPINT0_SETUP_CLR 0xfffffff7
L2_CONT_OFF_l2_standby_MSB 11
DMA8_TI_INTEN_LSB 0
EMMC_FORCE_IRPT_DMA_ERR_LSB 28
TS_TSENSCTL_RSTB_BITS 1:1
USB_DOEPINT0_TIMEOUT_RESET 0x0
USB_DOEPTSIZ0 0x7e980b10:RW
USB_DOEPTSIZ1 0x7e980b30:RW
USB_DOEPTSIZ2 0x7e980b50:RW
USB_DOEPTSIZ3 0x7e980b70:RW
USB_DOEPTSIZ4 0x7e980b90:RW
USB_DOEPTSIZ5 0x7e980bb0:RW
USB_DOEPTSIZ6 0x7e980bd0:RW
USB_DOEPTSIZ7 0x7e980bf0:RW
USB_DOEPTSIZ8 0x7e980c10:RW
USB_DOEPTSIZ9 0x7e980c30:RW
SD_DQRCRC9_RISE_SET 0xffff0000
OTP_ADDR_REG_WIDTH 5
DMA_INT_STATUS_INT1_BITS 1:1
A2W_XOSC_CTRL_PLLDEN_LSB 5
CM_CCP2CTL_BUSY_CLR 0xffffff7f
EMMC_CMDTM_TM_BLKCNT_EN_MSB 1
GP_HEN2_HENn64_BITS 5:0
DMA1_TXFR_LEN_XLENGTH_CLR 0xffff0000
CSI2_REA0 CSI2_BASE_ADDRESS + 0x110:RW
MULTICORE_SYNC_SEMA_MASK_11 MULTICORE_SYNC_BASE_ADDRESS + 0x2C:RW
MULTICORE_SYNC_SEMA_MASK_12 MULTICORE_SYNC_BASE_ADDRESS + 0x30:RW
MULTICORE_SYNC_SEMA_MASK_13 MULTICORE_SYNC_BASE_ADDRESS + 0x34:RW
MULTICORE_SYNC_SEMA_MASK_14 MULTICORE_SYNC_BASE_ADDRESS + 0x38:RW
MULTICORE_SYNC_SEMA_MASK_15 MULTICORE_SYNC_BASE_ADDRESS + 0x3C:RW
MULTICORE_SYNC_SEMA_MASK_16 MULTICORE_SYNC_BASE_ADDRESS + 0x40:RW
MULTICORE_SYNC_SEMA_MASK_17 MULTICORE_SYNC_BASE_ADDRESS + 0x44:RW
MULTICORE_SYNC_SEMA_MASK_18 MULTICORE_SYNC_BASE_ADDRESS + 0x48:RW
MULTICORE_SYNC_SEMA_MASK_19 MULTICORE_SYNC_BASE_ADDRESS + 0x4C:RW
I2C1_C 0x7e804000:RW
DMA2_SOURCE_AD_MASK 0xffffffff
A2W_XOSC_CTRL_PLLDOK_LSB 17
TH0T1PC 0x18011000 + 0x18:RW
USB_GINTMSK_DISCONN_INT_MSB 29
DMA9_TI_SRC_INC_LSB 8
FPGA_CTRL0_DIS_CTL0_BITS 0:0
GP_FSEL1_FSEL10_CLR 0xfffffff8
I2C1_A_WIDTH 7
I2C_SPI_SLV_DR_RXDMAPREQ_BITS 12:12
FPGA_CTRL0_DIS_CTL2_LSB 2
HDMI_VERTB0_MANUAL_VBP0_LSB 8
AVE_OUT_Y_COEFF_RED_COEFF_SET 0x3ff00000
CAM0_CAMCMP1_MASK 0xffffffff
MPHI_CTRL_DIRECT_LSB 4
EMMC_CONTROL1_CLK_FREQ_MS2_CLR 0xffffff3f
SD_PHYC_PHYRST_BITS 0:0
I2C_SPI_SLV_MIS_TXMIS_LSB 1
HDMI_RAM_PACKET_3_5_RESET 0000000000
USB_DOEPDMAB10_MASK 0xffffffff
USB_DTKNQR1 0x7e980820:RW
MPHI_C1INDDB_MORUN_SET 0x80000000
SD_DQLCRC10_FALL_BITS 15:0
CM_UARTCTL_KILL_BITS 5:5
PWMCTL_POLA(n) MACRO
L1_IC1_CONTROL_START_FLUSH_CLR 0xfffffffd
MULTICORE_SYNC_SEMA_MASK_21 MULTICORE_SYNC_BASE_ADDRESS + 0x54:RW
CAM1_CAMIVSTA_WIDTH 32
MULTICORE_SYNC_SEMA_MASK_23 MULTICORE_SYNC_BASE_ADDRESS + 0x5C:RW
MULTICORE_SYNC_SEMA_MASK_24 MULTICORE_SYNC_BASE_ADDRESS + 0x60:RW
USB_GRSTCTL_INT_TKN_Q_FLSH_CLR 0xfffffff7
MULTICORE_SYNC_SEMA_MASK_26 MULTICORE_SYNC_BASE_ADDRESS + 0x68:RW
MULTICORE_SYNC_SEMA_MASK_27 MULTICORE_SYNC_BASE_ADDRESS + 0x6C:RW
CM_TCNTCNT_CNT_LSB 0
MULTICORE_SYNC_SEMA_MASK_29 MULTICORE_SYNC_BASE_ADDRESS + 0x74:RW
DSI0_PHYC_unused_BITS 4:4
DMA7_CS_END_CLR 0xfffffffd
A2W_SMPS_L_SPV_WIDTH 5
MPHI_C1INDFS_DFIFOLVL_RESET 0x0
DMA4_CS_ERROR_CLR 0xfffffeff
SLIM_DCC2_STAT_RESET 0000000000
USB_DTKNQR3 0x7e980830:RW
CM_TECCTL_FRAC_CLR 0xfffffdff
USB_GHWCFG2_TOKEN_QUEUE_DEPTH_RESET 0x0
DMA1_TI_SRC_IGNORE_LSB 11
SMI_DSW2_WSTROBE_MSB 6
CM_GP0CTL_WIDTH 11
SMI_DC_WIDTH 29
SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_RESET 0x0
DMA2_DEBUG_DMA_STATE_CLR 0xfe00ffff
SD_SB_BANKLOW_LSB 5
HDMI_CPU_STATUS_RESET 0000000000
APERF1_BW1_CTRL_BUS_LSB 0
DSI0_HS_DLT5_RESET 0000000000
GRPZBCG 0x1A005600 + 0x40:RW
TB_JTB_CONFIG_BITCNT_SET 0x3f800000
CM_TD1CTL_BUSY_SET 0x00000080
SLIM_MC_IN_CON_RESET 0000000000
I2C_SPI_SLV_FR_TXFE_MSB 4
MULTICORE_SYNC_SEMA_MASK_30 MULTICORE_SYNC_BASE_ADDRESS + 0x78:RW
MULTICORE_SYNC_SEMA_MASK_31 MULTICORE_SYNC_BASE_ADDRESS + 0x7C:RW
DMA0_CS_RESET_MSB 31
MS_ICCLR_0_ICCLR_0_SET 0x00000001
CM_CKSM_OSC_CLR 0xfff3ffff
DMA15_DEBUG_READ_ERROR_BITS 2:2
USB_DOEPINT0_AHB_ERR_CLR 0xfffffffb
HDMI_PERT_INSERT_ERR_SEPARATION HDMI_BASE_ADDRESS + 132:RW
USB_DCFG_NZ_STS_OUT_HSHK_SET 0x00000004
HD_HDM_CTL_CECRXD_SET 0x00000200
SYSAC_ISP_PRIORITY_PRIORITY_CLR 0xfffffff0
A2W_XOSC_CPR_CPR1_CLR 0xffffffef
I2C_SPI_SLV_DR_RXBUSY_CLR 0xffdfffff
SMI_DC_MASK 0x11ffffff
MS_SEMA_29_MASK_CLR 0xfffffffe
CCP2TX_TTC_ATX_SET 0x80000000
DMA_CB_2DSTR(n) MACRO
A2W_PLLC_DIG0_RESET 0000000000
DMA7_NEXTCONBK_MASK 0xffffffe0
GP_LEN1_LENn32_SET 0xffffffff
EMMC_HWCAP0_V3_0_CLR 0xfdffffff
V3D_BPOA 0x7ec00000 +0x0308:RW
A2W_PLLB_ARMR_WIDTH 10
USB_HPTXSTS_HPTXFSPCAVAIL_SET 0x0000ffff
ASB_CPR_CTRL_WCOUNT_MSB 23
EMMC_BLKSIZECNT_WIDTH 32
GRMCFG 0x1A005C00 + 0x04:RW
V3D_BPOS 0x7ec00000 +0x030c:RW
SYSAC_V3D_LIMITER_MAX_PRIORITY_BITS 7:3
DMA10_DEBUG_OUTSTANDING_WRITES_BITS 7:4
DMA9_TI_DEST_IGNORE_CLR 0xffffff7f
USB_GI2CCTL_SUSP_CTL_CLR 0xfdffffff
DSI1_TST_SEL_MASK 0xffffffff
A2W_PLLH_ANA_VCO_RANGE_SET 0x00000001
A2W_PLLC_PERR_RESET 0x00000100
EMMC_TUNE_STEPS_DDR_WIDTH 6
GP_FSEL5_FSEL56_MSB 20
L1_IC0_CONTROL_DISABLE_MSB 0
FPGA_CTRL0_CAM_CTL2_MSB 2
MS_ICCLR_0_ICCLR_0_CLR 0xfffffffe
CM_EVENT_GAINA_MSB 0
SH_HSTS_CRC7_ERROR_CLR 0xffffffef
EMMC_STATUS_NEW_WRITE_DATA_SET 0x00000400
PM_PROC_MEMREP_MSB 3
DMA15_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
PWM_CTL_RPTL3_BITS 18:18
USB_DIEPTXF13_MASK 0xffffffff
USB_HCCHAR0_CH_ENA_LSB 31
UART_LCR_WLS_BITS 1:0
SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_MSB 3
JHADDR 0x7e005000 + 0x28:RW
SYSAC_V3D_LIMITER 0x7e009068:RW
A2W_PLLH_CTRL_PRSTN_BITS 17:17
DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
CM_AVEODIV_MASK 0x0000f000
A2W_PLLC_ANA0R_MASK 0x00ffffff
EMMC_BLKSIZECNT_BLKSIZE_CLR 0xfffff000
DMA1_CONBLK_AD_MASK 0xffffffe0
DMA8_CS_PAUSED_CLR 0xffffffef
USB_GAHBCFG_NP_TXF_EMP_LVL_MSB 7
DMA14_TI_SRC_WIDTH_MSB 9
A2W_PLLC_ANA2R_RESET 0000000000
TB_TASK_RXDATA1_WIDTH 32
SD_SF_MDLL_CAL_LSB 0
AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_MSB 14
USB_GINTMSK_ERLY_SUSP_CLR 0xfffffbff
ARM_SBM_OWN0 (0x7E00B000 +0x800)
ARM_SBM_OWN1 (0x7E00B000 +0x900)
ARM_SBM_OWN2 (0x7E00B000 +0xA00)
ARM_SBM_OWN3 (0x7E00B000 +0xB00)
CCP2TX_TSPARE_MASK 0xffffffff
A2W_XOSC_CTRL_PLLCOK_CLR 0xffffefff
SH_CMD_NEW_FLAG_LSB 15
I2C_SPI_SLV_CR_INV_RXF_BITS 10:10
DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
A2W_PLLC_CORE1_BYPEN_MSB 9
SD_SD_T_RPpb_MSB 7
I2C1_S 0x7e804004:RW
USB_DIEPDMA2_MASK 0xffffffff
PM_PADS2_HYST_BITS 3:3
EMMC_IRPT_MASK_MASK 0xffffffff
APERF0_BW2_CTRL_EN_SET 0x40000000
GP_FSEL3_MASK 0x3fffffff
PWM_CTL_CLRF1_LSB 6
HDMI_PERT_TEST_LENGTH_RESET 0000000000
USB_DIEPCTL0_TXF_NUM_BITS 25:22
I2C_SPI_SLV_DR_DATA_MSB 7
USB_HCSPLT0_MASK 0xffffffff
I2C1_CLKT_MASK 0x0000ffff
SLIM_DCC4_PROT_RESET 0x000093a0
DSI0_STAT 0x7e20902c:RW
CM_PLLA_HOLDPER_SET 0x00000080
PM_CAM1_CTRLEN_CLR 0xfffffffe
DPHY_CSR_BYTE3_MASTER_DLL_OUTPUT 0x7ee07038:RW
DMA13_TI_DEST_DREQ_LSB 6
USB_DOEPCTL0_CNAK_LSB 26
A2W_PLLB_CTRL_MASK 0x000373ff
SD_DQLCRC12_FALL_LSB 0
TH0T1UD 0x18011000 + 0x1C:RW
GP_FSEL6_FSEL66_SET 0x001c0000
CM_TD1DIV_DIV_CLR 0xff000000
I2C_SPI_SLV_ICR_TXIC_MSB 1
APERF1_BW0_RMAX_RESET 0000000000
SMI_DC_RESET 0x00c10820
ST_CLO 0x7e003004:RO
SYSAC_DMA_ARBITER_CONTROL_UC_WIDTH 16
SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_BITS 3:2
EMMC_CONTROL2_DRVTYPE_LSB 20
CM_TDCLKEN_PLLCBYP_LSB 2
USB_GHWCFG3_TRANS_COUNT_WIDTH_CLR 0xfffffff0
A2W_PLLC_CORE0_BYPEN_LSB 9
APERF0_BW0_RTRANS_WIDTH 32
DMA0_NEXTCONBK_ADDR_SET 0xffffffe0
GRFCS 0x1A005400 + 0x00:RW
SMI_DSW1_WDREQ_SET 0x00000080
L2_CONT_OFF_l2_no_wr_allocate_LSB 1
HDMI_SCHEDULER_CONTROL_USE_POSTLN_AVOID_LSB 14
PCMDREQ_RXPANICTHR_LSB 16
GP_PUDCLK2_PUDCLKn64_LSB 0
DMA6_TI_DEST_INC_SET 0x00000010
I2C_SPI_SLV_ICR_TXIC_SET 0x00000002
ASB_ISP_S_CTRL_WCOUNT_MSB 23
CM_V3DCTL_SRC_MSB 3
L1_IC1_CONTROL_RESET 0000000000
A2W_PLLB_SP1_BYPEN_SET 0x00000200
DMA11_CS_DISDEBUG_LSB 29
APERF0_BW2_CTRL_ID_MSB 12
CM_EVENT_LOSSD_MSB 8
CM_TD1DIV_MASK 0x00ffffff
EMMC_FORCE_IRPT_DMA_CLR 0xfffffff7
DMA10_TI_DEST_WIDTH_SET 0x00000020
I2C2_DLEN_WIDTH 16
L1_IC1_PRIORITY_IC1_APRIORITY1_LSB 4
I2C_SPI_SLV_DMACR_RXDMAE_BITS 0:0
DMA2_DEBUG_RESET 0000000000
DMA13_CS_END_SET 0x00000002
EMMC_CONTROL0_PWCTL_SDVOLTS_CLR 0xfffff1ff
DMA12_NEXTCONBK_ADDR_SET 0xffffffe0
USB_HCINT0_DATA_TGL_ERR_CLR 0xfffffbff
MPHI_C1INDS_DISCARD_LSB 31
SMI_CS_RXD_RESET 0x0
SH_CMD_NO_RESPONSE_BITS 10:10
SLIM_DCC9_STAT 0x7e21032c:RW
DMA10_DEST_AD_D_ADDR_SET 0xffffffff
SLIM_DCC7_PA0_WIDTH 24
TS_TSENSCTL_THOLD_SET 0x0003ff00
DMA_CS_DIS_DBS_PAUSE (1<<29)
SD_SC_WIDTH 31
CM_LOCK 0x7e101114:RW
PCM_CS_A_TXE_MSB 21
UART_MSR_DSR_MSB 5
SYSAC_L2_ARBITER_CONTROL_THRESHOLD_RESET 0x0
DMA8_SOURCE_AD_S_ADDR_SET 0xffffffff
CM_TIMERDIV_WIDTH 18
GRMOADR 0x1A005C00 + 0x14:RW
USB_DCTL_GOUT_NAK_STS_BITS 3:3
PWM_CTL_PWEN1_BITS 0:0
I2C_SPI_SLV_CR_HOSTCTRLEN_LSB 12
CM_GP2CTL_BUSYD_CLR 0xfffffeff
DMA10_TI_INTEN_MSB 0
L1_D0_WR_HITS_MASK 0000000000
USB_DOEPTSIZ0_PKT_CNT_RESET 0x0
PCMMODE_PDMRXN (1 << 27)
FPGA_CTRL0_SW_SPI_SCL_BITS 6:6
HDMI_READ_POINTERS 0x7e902060:RW
DSI1_TXPKT2_H_MASK 0xffffffff
MPHI_OUTDDA 0x7e006028:RW
EMMC_CMDTM_CMD_CRCCHK_EN_MSB 19
A2W_PLLB_ANA_SSCS_STEP_SET 0x0000ffff
CM_OTPDIV_DIV_BITS 16:12
GP_FSEL5_FSEL52_LSB 6
CM_EMMCCTL_BUSYD_MSB 8
DMA1_CS_DREQ_STOPS_DMA_MSB 5
EMMC_HWCAP0_BASEMHZ_LSB 8
TB_PRINTER_CTRL_OFFSET_MSB 1
USB_HFIR_IN_CLR 0xffff0000
SMI_L_RESET 0000000000
SYSAC_V3D_LIMITER_HOLDOFF_BITS 0:0
ASB_ISP_M_CTRL_FULL_LSB 3
ASB_H264_M_CTRL_RCOUNT_LSB 4
HDMI_RAM_PACKET_7_1_WIDTH 32
PM_PXBG_RESET 0000000000
A2W_APB_ID 0x00613277
SMI_DSR0_RHOLD_CLR 0xffc0ffff
I2C_SPI_SLV_ICR_RXIC_CLR 0xfffffffe
UART_MSR_DDCD_LSB 3
USB_GUSBCFG_FORCE_HST_MODE_BITS 29:29
SD_SB_STBY_T_MSB 31
EMMC_IRPT_MASK_BLOCK_GAP_SET 0x00000004
DMA8_TI_PERMAP_CLR 0xffe0ffff
DMA9_DEBUG_READ_ERROR_CLR 0xfffffffb
MPHI_MOUTFS_WPTR_SET 0x000ffc00
JP_C0BA 0x7e00504c:RW
CAM0_CAMCLK_MASK 0xffffffff
DMA0_CS_PAUSED_MSB 4
EMMC_RESP1 0x7e300014:RW
DMA11_TI_DEST_DREQ_MSB 6
DMA4_TXFR_LEN 0x7e007414:RO
SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_MSB 2
PM_RSTC_SRCFG_CLR 0xfffffcff
USB_DIEPCTL0_NEXT_EP_BITS 14:11
HDMI_RAM_PACKET_3_3_WIDTH 32
DMA1_DEBUG_VERSION_BITS 27:25
VEC_CFG_WIDTH 32
EMMC_RESP2 0x7e300018:RW
EMMC_FORCE_IRPT_BLOCK_GAP_MSB 2
SD_VIN_CLEAR_SET 0x80000000
PCM_INTEN_A_RXR_MSB 1
POWERMAN_BASE_ADDRESS 0x7e100000
MAX_DMA_SUB 1
A2W_HDMI_CTL_RCAL_RSTB_CLR 0xfffeffff
SMI_DSW2_WPACEALL_SET 0x00008000
UART_LCR_RESET 0000000000
USB_GNPTXSTS_TX_Q_SPC_AVAIL_LSB 16
HDMI_READ_POINTERS_DRFT_ALMOST_MT_MSB 18
A2W_PLLD_DIG2R_RESET 0x00100401
SD_MR_RW_LSB 28
EMMC_HWCAP0_ADMA2_SET 0x00080000
A2W_PLLA_ANA_MULTI 0x7e102f10:RW
SD_PT1_T_INIT1_BITS 7:0
DMA13_DEBUG_VERSION_BITS 27:25
A2W_PLLA_DSI0_DIV_MSB 7
GP_GPTEST_SMPS_SET 0x00000001
DSI0_HS_DLT3_WIDTH 10
EMMC_IRPT_EN_CARD_OUT_LSB 7
MPHI_INTSTAT_WIDTH 32
DMA14_CONBLK_AD_MASK 0xffffffe0
EMMC_HWCAP0_AINT_LSB 29
EMMC_CONTROL0_GAP_IEN_BITS 19:19
DMA11_DEBUG_OUTSTANDING_WRITES_MSB 7
DSI0_PHYC_txhsclk_cont_sync_BITS 10:10
DMA5_TI_DEST_IGNORE_LSB 7
HDMI_RAM_PACKET_5_0_RESET 0000000000
DC0END 0x7ee02108:RW
A2W_PLLD_CTRL_PWRDN_BITS 16:16
GRFEBA 0x1A005400 + 0x34:RW
SMI_A_ADDR_BITS 5:0
SH_HCFG_REL_CMD_LINE_SET 0x00000001
DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
EMMC_HWCAP0_BASEMHZ_SET 0x0000ff00
A2W_PLLD_CTRL_PRSTN_LSB 17
HD_MAI_CTL_CHNUM_LSB 4
DMA5_CS_END_MSB 1
IMASK3_0 0x7e00201c:RW
IMASK3_1 0xffffffff:RW
CM_DPICTL_BUSYD_BITS 8:8
FPGA_CTRL0_DIS_CTL0_LSB 0
GROPCTR_FBC_CZ_CLRFLG_FETCHES 0x22
CCP2TX_TC_TEN_BITS 0:0
DMA12_TXFR_LEN 0x7e007c14:RO
DMA13_CS_INT_BITS 2:2
EMMC_DBG_SEL_SELECT_LSB 0
HDMI_RAM_PACKET_1_2_RESET 0000000000
HD_HDM_CTL_RFSTBY_RESET 0x3
PIXELVALVE_VC_1 0x7e207004:RW
DMA10_TI_SRC_IGNORE_BITS 11:11
CAM1_CAMDAT2_MASK 0xffffffff
EMMC_HWCAP0_HS_CLR 0xffdfffff
APERF0_BW2_CTRL_ID_EN_CLR 0xdfffffff
FPGA_STATUS0_SPARE_IN_CLR 0x0007ffff
DMA2_STRIDE_D_STRIDE_BITS 31:16
USB_GPVNDCTL_STS_BSY_SET 0x04000000
AVE_IN_BUF0_ADDRESS_BUF0_ADDR_LSB 0
CM_CKSM_FRCE_LSB 8
PM_HDMI_LDOCTRL_CLR 0xfff80003
DMA2_SOURCE_AD_S_ADDR_LSB 0
SMI_CS_INTD_CLR 0xfffffdff
DMA14_CS_END_LSB 1
TB_JTB_CONFIG_D_HOLD_CLR 0xffffcfff
SLIM_DCC1_PROT_RESET 0x000093a0
A2W_SMPS_CTLC0_WIDTH 24
CAM1_CAMCAP1_RESET 0000000000
V3D_DBSCFG 0x7ec00000 +0x0e08:RW
A2W_PLLA_ANA_KAIP_KP_SET 0x0000000f
CM_VPUCTL_FRAC_BITS 9:9
A2W_PLLA_DSI0_BYPEN_MSB 9
USB_GI2CCTL_EN_MSB 23
SMI_DSR1_RSETUP_SET 0x3f000000
SD_TMC_MASK 0xffffff73
I2C_SPI_SLV_RIS_TXRIS_MSB 1
A2W_PLLH_ANA_KAIP_KP_CLR 0xfffffff0
A2W_XOSC1 0x7e102094:RW
A2W_SMPS_CTLC3_RESET 0000000000
DMA0_TI_SRC_IGNORE_MSB 11
OTP_INIT_STATUS_REG_MASK 0xffffffff
USB_DIEPINT0_XFER_COMPL_BITS 0:0
DMA2_DEBUG_DMA_ID_BITS 15:8
SD_TMC_TS_BITS 1:1
I2C_SPI_SLV_CR_INV_RXF_SET 0x00000400
AVE_IN_CTRL_PRIORITY_LIMIT_CLR 0xf8ffffff
PM_GRAFX_CFG_SET 0x007f0000
EMMC_CONTROL2_ACNOX_ERR_LSB 0
SMI_DSW3_WHOLD_MSB 21
AVE_IN_CTRL_ENABLE_BITS 31:31
A2W_PLLD_ANA3_WIDTH 24
DMA_INT_STATUS_INT6_LSB 6
MS_SEMA_7_MASK_BITS 0:0
DMA4_CS_PANIC_PRIORITY_MSB 23
SH_HCFG_BUSY_IRPT_EN_SET 0x00000400
EMMC_INTERRUPT_CEND_ERR_MSB 18
USB_DOEPINT0_TIMEOUT_LSB 3
SCALER_DISPECTRL_CB_NE_CTRL_MSB 31
A2W_PLLA_DIG1_MASK 0x00ffffff
SD_DQRCRC15_RISE_BITS 31:16
GP_CLR1_CLRn32_LSB 0
SD_PHYC_CRC_EN_BITS 20:20
A2W_PLLD_DIG0R 0x7e102840:RW
USB_DOEPCTL0_TXF_NUM_SET 0x03c00000
PM_SPARER_SPARE_MSB 23
USB_DOEPTSIZ0_PKT_CNT_CLR 0xe007ffff
VPU_ARB_CTRL_L2_CHANNEL_INIBIT_RESET 0x0
SD_DQRCRC2_FALL_SET 0x0000ffff
A2W_PLLD_PER_WIDTH 10
PM_BASE 0x7e100000
ASB_ISP_S_CTRL_FULL_BITS 3:3
AUX_SPI_CNTL0_INVCLK 0x00000080
CPG_Param0 0x7e211010:RW
PCM_MODE_A_CLK_DIS_BITS 28:28
CPG_Param2 0x7e211018:RW
HDMI_HORZA_MANUAL_HAP_SET 0x00001fff
CM_LOCK_LOCKD_SET 0x00000008
VPU_ARB_CTRL_L2_CHANNEL_INIBIT_LSB 8
L1_L1_SANDBOX_START5_CTRL_LSB 0
GP_FSEL0_FSEL04_MSB 14
USB_DSTS_ERRTIC_ERR_LSB 3
ASB_AXI_BRDG_VERSION 0x7e00a000:RW
MPHI_C1INDDB 0x7e00600c:RW
USB_GI2CCTL_SUSP_CTL_BITS 25:25
DSI0_TA_TO_CNT_RESET 0000000000
GP_FSEL2_FSEL25_CLR 0xfffc7fff
DMA3_DEBUG_FIFO_ERROR_SET 0x00000002
A2W_PLLC_ANA_MULTI 0x7e102f30:RW
SMI_CS_TEEN_SET 0x00000100
DMA_ENABLE_EN12_BITS 12:12
USB_DTHRCTL_ARB_PRK_EN_SET 0x08000000
USB_DIEPTXF15_WIDTH 32
APERF0_BW0_CTRL_LATHALT_RESET 0x0
HDMI_SCHEDULER_CONTROL_RESET 0x000cb008
CM_ISPCTL_BUSYD_MSB 8
DMA9_TI_SRC_DREQ_BITS 10:10
DMA0_DEBUG_DMA_ID_MSB 15
ALIAS_L1L2_NONALLOCATING_READ(x) MACRO
USB_GINTMSK_EOPF_SET 0x00008000
AVE_OUT_STATUS_HSYNC_LSB 6
VCE_BAD_ADDR_OFFSET 0x40030
PM_PADS0_DRIVE_SET 0x00000007
PWM_CTL_RPTL3_MSB 18
SCALER_DISPSTAT_MASK 0xffffffff
USB_DIEPDMA15_MASK 0xffffffff
L1_D_PRIORITY_c0_per_priority_BITS 11:8
EMMC_BLKSIZECNT_BLKCNT_CLR 0x0000ffff
MS_SEMA_16_MASK_SET 0x00000001
MPHI_C1INDDB_MENDINT_CLR 0xbfffffff
SD_CS_RDH_IDLE_CLR 0xfffeffff
A2W_XOSC_CTRL_USBOK_MSB 14
DMA_ENABLE_EN2_MSB 2
USB_GAHBCFG_GLBL_INTR_MSK_LSB 0
DMA4_CS_ACTIVE_LSB 0
DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
I2C0_S_RESET 0x00000050
A2W_PLLH_CTRL_PRSTN_CLR 0xfffdffff
DMA8_TXFR_LEN 0x7e007814:RO
DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
SPI_CS_TA_MSB 7
A2W_XOSC_PWR_BYPASS_BITS 0:0
SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_LSB 6
HDMI_VERTA0_MANUAL_VFP0_CLR 0xfff01fff
SMIA_DEVICE 8
USB_GRXSTSP_HST_BCNT_CLR 0xffff800f
USB_HPRT_SPD_LSB 17
A2W_PLLA_CCP2_BYPEN_SET 0x00000200
TXP_CTRL_BWE_MSB 19
A2W_PLLC_ANA_SSCSR_MASK 0x0001ffff
A2W_PLLA_ANA2_MASK 0x00ffffff
DSI0_RX2_PKTH_MASK 0xffffffff
PWM_STA_GAPO1_SET 0x00000010
DMA7_CS_END_BITS 1:1
DMA10_CS_DREQ_CLR 0xfffffff7
EMMC_IRPT_MASK_CARD_OUT_SET 0x00000080
GP_FSEL1_FSEL14_SET 0x00007000
DMA13_CONBLK_AD_SCB_ADDR_MSB 31
TB_TASK_PARAM3 0x7e20b00c:RW
DSI0_PHYC_unused_MSB 4
DMA8_CS_DREQ_SET 0x00000008
IC0_S 0x7e002004:RO
USB_HCSPLT0_COMP_SPLT_LSB 16
PM_GRAFX_RESET 0x00001000
I2C_SPI_SLV_DR_OE_SET 0x00000100
DMA15_NEXTCONBK 0x7ee0501c:RO
TB_BOOT_OPT_EIGHT_BANK_CLR 0xfffffffd
DMA14_DEBUG_OUTSTANDING_WRITES_BITS 7:4
IC1_MASK5_RESET 0000000000
PCM_MODE_A_FSM_BITS 21:21
MPHI_C1INDCF_MTERM_SET 0x10000000
USB_HPRT_LN_STS_MSB 11
CM_DPICTL_ENAB_BITS 4:4
CM_ARMCTL_AXIHALF_BITS 12:12
DMA5_NEXTCONBK 0x7e00751c:RO
MPHI_CTRL_EIGHTBIT_CLR 0xffffefff
GP_GPTEST_SMPS_BITS 0:0
APERF1_BW1_WTWAIT_RESET 0000000000
HDMI_DVO_TIMING_ADJUST_B_RESET 0x88888888
DMA14_TI_WAIT_RESP_BITS 3:3
I2C_SPI_SLV_FR_TXFF_SET 0x00000004
USB_DIEPCTL6_WIDTH 32
DMA2_TI_WAITS_SET 0x03e00000
CCP2TX_TC_MASK 0x8000ff07
SPI_CS_RXR_SET 0x00080000
TB_BOOT_STATUS_CPRMAN_PROGRAMMED_CLR 0xfffffffe
EMMC_IRPT_EN_DEND_ERR_BITS 22:22
EMMC_HWCAP0_TCLKFREQ_BITS 5:0
EMMC_SPI_INT_SPT_MASK 0x000000ff
USB_DIEPINT0_BACK2BACK_SETUP_RESET 0x0
CM_CAM0DIV 0x7e101044:RW
OTP_CONFIG_REG_WIDTH 3
CAM1_CAMIDPO_MASK 0xffffffff
SCALER_LINE_BUFFER_MEM_SIZE ( 1024 * 64 )
A2W_XOSC_PWR_RSTB_LSB 2
CCP2TX_TS_TUE_CLR 0xfffffff7
DMA5_NEXTCONBK_ADDR_BITS 31:5
DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
CM_DSI0PDIV_DIV_BITS 12:12
DMA2_TI_MASK 0x07fffffb
CM_INTEN_GAINA_SET 0x00000001
CMI_CAMTEST_RESET 0000000000
TH1T1PC 0x1A008000 + 0x18:RW
DMA14_CS_RESET_LSB 31
HDMI_CEC_TX_DATA_2_RESET 0000000000
USB_DCTL_CGOUT_NAK_LSB 10
CM_GP2CTL_SRC_CLR 0xfffffff0
A2W_PLLB_ANA_VCO_RANGE_MSB 0
ASB_H264_M_CTRL_CLR_REQ_SET 0x00000001
HDMI_RAM_PACKET_7_6_WIDTH 32
L1_IC1_CONTROL_ENABLE_STATS_BITS 2:2
MPHI_HSINDCF_MTERM_MSB 28
DMA10_TI_PERMAP_MSB 20
DMA6_TI_DEST_IGNORE_LSB 7
SPI_CS_TXD_SET 0x00040000
USB_DOEPTSIZ0_RX_DPID_RESET 0x0
A2W_PLLH_AUX_CHENB_MSB 8
AVE_OUT_OFFSET_GREEN_OFFSET_SET 0x0000ff00
HDMI_TX_PHY_TX_PHY_CTL_1_MASK 0xffffffff
SYSAC_H264_PRIORITY_PRIORITY_SET 0x0000000f
USB_GHWCFG3_DFIFO_DEPTH_SET 0xffff0000
A2W_PLLH_ANA0R 0x7e102870:RW
AVE_OUT_OFFSET_WIDTH 32
APERF0_BW0_CTRL_LATHALT_LSB 28
TIMER_CTRL_ENAFREE (1 << 9)
DMA7_TI_DEST_DREQ_SET 0x00000040
SD_DQLCRC10_RISE_SET 0xffff0000
FPGA_MB_XC0_BUILD_NUM 0x7e20b704:RO
SD_DQLCRC7_FALL_SET 0x0000ffff
A2W_PLLD_FRAC 0x7e102240:RW
CM_DSI0EDIV 0x7e10105c:RW
SYSAC_V3D_PRIORITY_PRIORITY_BITS 3:0
CM_CAM0CTL_BUSYD_SET 0x00000100
CM_PLLTCNT2_MASK 0x00ffffff
HDMI_DETECTED_VERTA0_MANUAL_VSP0_LSB 20
CM_SDCCTL_BUSY_CLR 0xffffff7f
GP_FSEL0_FSEL00_LSB 0
DMA4_NEXTCONBK_ADDR_LSB 5
PCM_CS_A_TXERR_BITS 15:15
USB_GUSBCFG_ULPI_IF_PROT_DIS_LSB 25
HD_MAI_CTL_DLATE_SET 0x00008000
ST_CHI_MASK 0xffffffff
CM_SMICTL_BUSY_SET 0x00000080
DMA6_CS_DISDEBUG_SET 0x20000000
DMA7_TI_DEST_INC_SET 0x00000010
I2C_SPI_SLV_DR_RXFE_MSB 17
USB_GUSBCFG_PHY_SEL_BITS 6:6
DMA2_DEBUG_FIFO_ERROR_BITS 1:1
MPHI_TXAXICFG_INTHRESH_SET 0x0001ff00
APERF1_BW2_CTRL_ID_MSB 12
A2W_PLLC_CORE1_DIV_SET 0x000000ff
HDMI_RAM_PACKET_11_1_MASK 0xffffffff
A2W_PLLH_ANA1R 0x7e102874:RW
DMA1_TXFR_LEN_YLENGTH_SET 0x3fff0000
A2W_PLLA_PER_BYPEN_LSB 9
USB_GHWCFG4_NUM_IN_EPS_CLR 0xf3ffffff
MPHI_OUTDS_WORDS_LSB 0
DMA6_TI_DEST_DREQ_SET 0x00000040
MPHI_INTSTAT_IMFOFLW_CLR 0xdfffffff
CM_DSI0PCTL_SRC_MSB 3
SD_SECSRT0_EN_BITS 0:0
DMA0_TI_BURST_LENGTH_LSB 12
HDMI_RAM_PACKET_13_4_RESET 0000000000
A2W_HDMI_CTL0 0x7e102080:RW
A2W_HDMI_CTL1 0x7e102084:RW
A2W_HDMI_CTL2 0x7e102088:RW
A2W_HDMI_CTL3 0x7e10208c:RW
A2W_HDMI_CTL_HFEN 0x7e102280:RW
CM_TD1DIV_WIDTH 24
SLIM_DCC5_PROT 0x7e2102b0:RW
EMMC_SLOTISR_VER_SDVERSION_SET 0x00ff0000
PRM_SCC 0x7e20d008:RW
I2C_SPI_SLV_IMSC_RXIM_MSB 0
HD_MAI_THR_DREQLOW_BITS 5:0
EMMC_FORCE_IRPT_READ_RDY_BITS 5:5
A2W_PLLA_ANA3_WIDTH 24
HDMI_RAM_PACKET_1_0_WIDTH 32
DMA14_DEST_AD_D_ADDR_LSB 0
APERF0_BW1_WTWAIT_MASK 0xffffffff
MPHI_INTSTAT_RX1TEND_BITS 12:12
USB_HCFG_LS_SUPP_MSB 2
CM_CCP2CTL_BUSYD_SET 0x00000100
AVE_IN_CTRL_BUF0_IRQ_EN_CLR 0xfffffffd
SMI_FD_FLVL_SET 0x00003f00
A2W_PLLH_ANA2R 0x7e102878:RW
USB_DTXFSTS10_MASK 0xffffffff
HDMI_DETECTED_VERTB0_MANUAL_VSPO0_MSB 21
OTP_BOOT_EXTRAS_ROW ((((((((((((((((((((((8 +4)+4)+1)+1)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+1)+2)
AVE_OUT_CR_COEFF_WIDTH 30
SD_PT2_WIDTH 32
VPU_ARB_CTRL_UC_LIMIT_CLR 0xfffffffc
MPHI_OUTDDB_LENGTH_RESET 0x0
DMA13_CS_ABORT_SET 0x40000000
SMI_DSW0_WPACEALL_LSB 15
DMA12_DEBUG_LITE_SET 0x10000000
PM_GRAFX_ISFUNC_SET 0x00000020
CM_ARMCTL_KILL_LSB 5
SD_CS_DEL_KEEP_RESET 0x0
AVE_IN_CALC_LINE_STEP_WIDTH 12
DMA10_DEBUG_DMA_ID_MSB 15
CM_DPICTL_BUSY_LSB 7
DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
A2W_SMPS_CTLC1_WIDTH 24
HDMI_RAM_PACKET_8_5 0x7e902534:RW
L1_IC0_BP_MISSES_MASK 0000000000
CM_PWMCTL_ENAB_MSB 4
A2W_SMPS_L_SCA_RESET 0000000000
CM_H264CTL_BUSYD_SET 0x00000100
CM_CAM0DIV_DIV_LSB 4
A2W_PLLH_ANA3R 0x7e10287c:RW
DMA10_DEBUG_READ_ERROR_SET 0x00000004
SH_BASE 0x7e202000
SD_DQRCRC9_FALL_SET 0x0000ffff
CM_TDCLKEN_PLLABYP_BITS 0:0
PCM_CS_A_STBY_SET 0x02000000
USB_GINTMSK_ULPI_CK_INT_RESET 0x0
DMA15_STRIDE 0x7ee05018:RO
CM_DSI0HSCK_RESET 0000000000
DMA15_TI_WAITS_BITS 25:21
DMA2_TI_NO_WIDE_BURSTS_MSB 26
PWM_FIF1 0x7e20c018:RW
TXP_CTRL_TEST_MODE_BITS 4:4
SD_SECSRT1_EN_LSB 0
A2W_PLLD_DIG3_MASK 0x00ffffff
SLIM_DMA_DC7_RESET 0000000000
DSI1_CTRL_MASK 0xffffffff
SMI_FD_MASK 0x00003f3f
HDMI_CRP_CFG_MASK 0x0fffffff
USB_PCGCR_PWR_CLMP_LSB 2
CM_TD1CTL_BUSYD_BITS 8:8
USB_DFIFO2_MASK 0xffffffff
MPHI_TXAXICFG_INTHRESH_BITS 16:8
USB_HPRT_LN_STS_BITS 11:10
DMA9_DEBUG_VERSION_LSB 25
AJB_CLKSHFT 16
ASB_V3D_M_CTRL_CLR_ACK_SET 0x00000002
FPGA_CTRL0_DIS_BL_MSB 1
L2_IN_FLIGHT_MASK 0x0000000f
CM_PLLB_ANARST_SET 0x00000100
SD_PHYC_BIST_MODE_SET 0x00000100
SD_SECEND1_ADDR_MS_LSB 13
A2W_PLLH_AUX_BYPEN_CLR 0xfffffdff
EMMC_HWCAP1_DRV18_TYPEC_SET 0x00000020
USB_DFIFO15_WIDTH 32
IC1_SRC1_WIDTH 32
CM_AVEOCTL_KILL_BITS 5:5
PWM_CTL_PWEN1_LSB 0
CM_DSI1PDIV_DIV_CLR 0xffffefff
A2W_PLLD_CTRL_PWRDN_LSB 16
MPHI_HSINDS_WORDS_BITS 20:0
DMA7_DEST_AD 0x7e007710:RO
PCM_TXC_A_CH2EN_SET 0x00004000
APHY_CSR_ADDR_PVT_COMP_CTRL 0x7ee06070:RW
DMA1_CONBLK_AD 0x7e007104:RW
GRSVADR 0x1A005800 + 0x08:RW
USB_DIEPCTL0_USB_ACT_EP_CLR 0xffff7fff
HDMI_FIFO_CTL_INV_CLK_XFR_SET 0x00000008
CM_DFTCTL_BUSYD_LSB 8
DMA4_STRIDE_D_STRIDE_SET 0xffff0000
GP_FSEL3_FSEL39_BITS 29:27
SMI_DSW0_WFORMAT_MSB 23
SD_DQLCRC2_RISE_MSB 31
SMI_DSW2_WWIDTH_BITS 31:30
SCALER_DISPECTRL_PROF_TYPE_BITS 27:26
USB_GINTMSK_OEP_INT_LSB 19
DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
A2W_SMPS_A_VOLTS_VOLTS_SET 0x0000001f
APERF1_BW1_RMAX_MASK 0x00ffffff
VEC_REVID_MASK 0xffffffff
DMA15_DEBUG_OUTSTANDING_WRITES_MSB 7
DMA7_DEBUG_DMA_STATE_CLR 0xfe00ffff
AVE_OUT_OFFSET_GREEN_OFFSET_LSB 8
SYSAC_UC_ARBITER_CONTROL_ALGORITHM_BITS 7:6
AVE_IN_CTRL_HSYNC_IRQ_EN_LSB 5
DMA8_TI_SRC_WIDTH_LSB 9
USB_DOEPCTL0_USB_ACT_EP_RESET 0x0
EMMC_IRPT_MASK_CARD_BITS 8:8
DMA5_DEBUG_LITE_SET 0x10000000
USB_HFNUM_NUM_RESET 0x0
DMA5_CS_DREQ_LSB 3
AVE_IN_CTRL_PRIORITY_LIMIT_SET 0x07000000
V3D_PCTRS1_MASK 0x0000001f
EMMC_CONTROL0_HCTL_DWIDTH_SET 0x00000002
SD_SC_T_RRD_MSB 23
L1_D1_WBACKS_WIDTH 0
HDMI_FIFO_CTL_RECENTER_MSB 6
A2W_SMPS_L_SPAR 0x7e102ad0:RW
EMMC_FORCE_IRPT_CTO_ERR_BITS 16:16
DMA12_DEBUG_VERSION_LSB 25
VEC_CPS32_CPC 0x7e806140:RW
PCM_MODE_A_FSI_CLR 0xffefffff
USB_DTKNQR4_MASK 0xffffffff
A2W_PLLD_ANA0R_WIDTH 24
DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
ADCCS 0x1C00E000 + 0x00:RW
A2W_XOSC0R_RESET 0x00820080
CM_PLLD_DIGRST_CLR 0xfffffdff
I2C_SPI_SLV_DR_UE_SET 0x00000200
IC1_MASK3_WIDTH 31
SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_MSB 1
SMI_CS_RXR_LSB 27
I2C_SPI_SLV_IMSC_BEIM_LSB 2
A2W_PLLA_FRAC_FRAC_MSB 19
CM_DSI1PCTL_BUSYD_CLR 0xfffffeff
A2W_PLLB_ANA_KAIP_KP_SET 0x0000000f
SCALER_DISPSTAT_DMA_IRQ_LSB 4
DMA10_CS_MASK 0xf0ff017f
USB_DVBUSPULSE 0x7e98082c:RW
V3D_DBSDR3_MASK 0xffffffff
DMA1_DEBUG_VERSION_SET 0x0e000000
CM_ARMCTL_AXIHALF_SET 0x00001000
DMA3_NEXTCONBK_ADDR_LSB 5
MS_VPUSEMA_0 0x7e0000c0:RW
MS_VPUSEMA_1 0x7e0000c4:RW
EMMC_CMDTM_CMD_TYPE_LSB 22
CM_CAM0DIV_DIV_CLR 0xffff000f
APERF0_BW2_RTWAIT_WIDTH 32
MPHI_CTRL 0x7e00604c:RW
DMA13_TI_SRC_DREQ_MSB 10
APHY_CSR_GLBL_ADDR_DLL_PH_LD_VAL 0x7ee06010:RW
FPGA_MB_XC1_BUILD_NUM 0x7e20b708:RO
TB_TASK_PARAM2_MASK 0xffffffff
HDMI_VERTB0_RESET 0x00000021
A2W_PLLA_PER_DIV_BITS 7:0
SD_CS_PUSKIP_RESET 0x0
I2C_SPI_SLV_CR_CPHA_CLR 0xfffffff7
DMA7_DEBUG_RESET 0000000000
SD_DQRCRC4_RISE_MSB 31
A2W_XOSC_CTRL_USBEN_BITS 2:2
CM_PWMCTL_KILL_CLR 0xffffffdf
HD_FRAME_CNT_WIDTH 32
SYSAC_L2_ARBITER_CONTROL_LIMIT_SET 0x00000003
HDMI_RAM_PACKET_8_2_MASK 0xffffffff
CM_HSMCTL_BUSYD_LSB 8
EMMC_EXRDFIFO_CFG_RESET 0000000000
HD_CSC_22_21 0x7e80804c:RW
SLIM_DCC5_PA1 0x7e2102a4:RW
HDMI_RAM_PACKET_2_1_MASK 0xffffffff
A2W_XOSC_CTRL_USBEN_CLR 0xfffffffb
A2W_PLLA_ANA_KAIP_KA_BITS 10:8
ASB_ISP_M_CTRL_CLR_ACK_SET 0x00000002
DMA8_TI_SRC_IGNORE_SET 0x00000800
CAM0_CAMANA 0x7e800008:RW
MS_SEMA_8_RESET 0000000000
USB_GINTMSK_MODE_MIS_BITS 1:1
VEC_CONFIG0 0x7e806104:RW
A2W_PLLA_CORER_WIDTH 10
HDMI_DETECTED_HORZA_MANUAL_HPOL_BITS 13:13
A2W_XOSC_BIASR_MASK 0x0000001f
SD_DQRCRC2_FALL_RESET 0x0
SD_DQRCRC13_RISE_LSB 16
CM_INTEN_FLOSSB_LSB 15
PCMMODE PCM_BASE_ADDRESS + 0x08:RW
TS_TSENSSTAT_DATA_CLR 0xfffffc00
SCALER_DISPSTAT_DSP0_IRQ_MSB 31
CM_PWMCTL_SRC_BITS 3:0
A2W_PLLH_CTRL_PWRDN_CLR 0xfffeffff
PM_IMAGE_POWUP_MSB 0
SMI_DSW3_WPACE_MSB 14
DMA5_CS_PANIC_PRIORITY_SET 0x00f00000
CM_PLLA_HOLDCORE_BITS 5:5
A2W_XOSC_CTRL_PLLBEN_MSB 7
A2W_SMPS_L_SIV_VOLTS_LSB 0
IC0_S_MASK 0x073f073f
CM_INTEN_FLOSSD_CLR 0xfffdffff
MPHI_HSINDDA_START_BITS 31:0
PM_PROC_ISFUNC_LSB 5
CM_V3DCTL_BUSY_LSB 7
USB_HPRT_PWR_SET 0x00001000
CM_GP2CTL 0x7e101080:RW
USB_DIEPINT0_TX_FIFO_UNDRN_CLR 0xfffffeff
CCP2TX_TIC_TIIE_MSB 0
DMA0_TI_WAITS_LSB 21
DMA15_TXFR_LEN_YLENGTH_MSB 29
USB_DOEPINT0_IN_EP_NAK_EFF_BITS 6:6
GROPCTR_FBC_EZ_FE_MISSES 0x3A
DMA12_CONBLK_AD_SCB_ADDR_BITS 31:5
MS_SEMA_2_MASK_LSB 0
GP_FSEL1_FSEL19_MSB 29
CM_INTEN_LOSSC_CLR 0xffffff7f
EMMC_HWCAP1_SDR50_MSB 0
CM_CAM1CTL_BUSY_BITS 7:7
EMMC_IRPT_EN_DATA_DONE_MSB 1
HDMI_RAM_PACKET_12_7_WIDTH 32
DMA0_TI_WAIT_RESP_LSB 3
MPHI_C1INDDB_LENGTH_BITS 19:0
A2W_XOSC_CPRR_WIDTH 5
CM_INTEN_OCDONE_LSB 21
DMA6_DEBUG_FIFO_ERROR_BITS 1:1
MPHI_INTCTRL_HSDCOFLW_SET 0x00100000
A2W_SMPS_CTLA2_MASK 0x00ffffff
PCM_GRAY_EN_BITS 0:0
CAM0_CAMIVSTA_MASK 0xffffffff
DMA2_TI_SRC_WIDTH_MSB 9
CM_TDCLKEN_PLLDBYP_MSB 3
USB_GRXSTSP_DEV_PKT_STS_MSB 20
DMA15_TXFR_LEN_XLENGTH_LSB 0
USB_GINTMSK_ENUM_DONE_BITS 13:13
PCM_GRAY_WIDTH 22
HDMI_DETECTED_VERTB1_RESET 0x00000021
HDMI_HOTPLUG 0x7e90200c:RW
AUX_MU_IER_REG (0x7E215000 +0x044)
CM_GNRICCTL_BUSYD_BITS 8:8
FPGA_MB_SDC_CLK_FREQ_WIDTH 32
PM_AVS_RSTDR_SYSTEM_A_CLR 0xfffffffd
IC1_PROFILE 0x7e002838:RW
A2W_PLLB_ANA_VCOR 0x7e102ef0:RW
DMA3_CS_ACTIVE_MSB 0
SPI_LTOH_TOH_SET 0x0000000f
DMA7_SOURCE_AD 0x7e00770c:RO
PM_CAM1_LDOHPEN_LSB 2
CM_TSENSCTL_KILL_BITS 5:5
DMA13_TXFR_LEN_XLENGTH_CLR 0xffff0000
USB_HPRT_OVR_CURR_CHNG_SET 0x00000020
CM_PLLTCTL_SRC_MSB 2
DSI0_CTRL 0x7e209000:RW
DMA11_TI_PERMAP_CLR 0xffe0ffff
SD_DQRCRC5_FALL_BITS 15:0
DMA14_TI_WAITS_CLR 0xfc1fffff
VPU_ARB_CTRL_L2_THRESHOLD_CLR 0xffffffcf
CM_TDCLKEN_SLIMDFT_BITS 12:12
DMA_INT_STATUS_INT10_CLR 0xfffffbff
USB_GOTGCTL_SES_REQ_LSB 1
DMA12_CS_END_LSB 1
DMA6_TI_SRC_INC_LSB 8
GP_FSEL6_WIDTH 30
EMMC_IRPT_MASK_ADMA_ERR_BITS 25:25
IC1_MASK0 0x7e002810:RW
IC1_MASK1 0x7e002814:RW
IC1_MASK2 0x7e002818:RW
DMA8_CS_RESET_LSB 31
IC1_MASK4 0x7e002820:RW
IC1_MASK5 0x7e002824:RW
IC1_MASK6 0x7e002828:RW
GP_FSEL2_FSEL29_SET 0x38000000
V3D_SQRSV1_MASK 0xffffffff
A2W_XOSC_BIAS_MASK 0x0000001f
SD_MR_WDATA_BITS 15:8
DSI0_PHY_AFEC1_MASK 0xffffffff
HDMI_RAM_PACKET_10_6_RESET 0000000000
SH_HSTS_FIFO_ERROR_CLR 0xfffffff7
SLIM_DMA_DC5_WIDTH 32
AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_MSB 31
GRTPTBA0 0x1A005220 + 0x00:RW
GRTPTBA1 0x1A0052A0 + 0x00:RW
EMMC_INTERRUPT_READ_RDY_BITS 5:5
CMTIMERF 0x7C:RW
CAM0_CAMCAP0_WIDTH 32
CM_PERIIDIV_DIV_CLR 0xffffefff
CM_GNRICDIV_DIV_BITS 23:0
DMA13_NEXTCONBK_ADDR_BITS 31:5
HDMI_RAM_PACKET_3_8_WIDTH 32
SD_SB_COLBITS_RESET 0x1
USB_GUSBCFG_DDR_SEL_CLR 0xffffff7f
AUX_SPI1_CNTL0_REG (0x7E215000 +0x0C0)
PM_CAM1_LDOHPEN_CLR 0xfffffffb
DSI0_LPRX_TO_C_MASK 0xffffffff
CCP2TX_TS_TQL_SET 0x00001f00
CCP2TX_TC_MEN_CLR 0xfffffffd
DMA1_CS_ABORT_CLR 0xbfffffff
DMA_ENABLE_EN6_BITS 6:6
VEC_CLMP0_END_MASK 0xffffffff
SD_DQLCRC9_RISE_MSB 31
AVE_IN_STATUS_CSYNC_FIELD_SET 0x00002000
A2W_PLLH_ANA_VCO_RANGE_BITS 0:0
SD_CS_ASHDNE_MSB 17
CM_SLIMCTL_BUSY_LSB 7
GP_REN1_RENn32_BITS 31:0
DMA11_CS_ABORT_LSB 30
GP_LEN2_LENn64_CLR 0xffffffc0
UART_LSR_THRE_LSB 5
USB_DOEPCTL10_MASK 0xffffffff
CCP2TX_TTC_MASK 0x80ff1fff
DMA5_DEBUG 0x7e007520:RW
AVE_OUT_CB_COEFF_GREEN_COEFF_CLR 0xfff003ff
APERF0_BW2_WMAX_MASK 0x0ff0ffff
CM_GP0CTL_MASH_CLR 0xfffff9ff
EMMC_RESP2_WIDTH 32
PM_SMPS_RSTDR_LSB 1
A2W_PLLH_ANA1R_MASK 0x00ffffff
USB_DIEPINT0_XFER_COMPL_MSB 0
PM_PADS0_HYST_CLR 0xfffffff7
CM_PERIICTL_WIDTH 7
TB_PCM_WIDTH 32
PIXELVALVE_INTEN_0 0x7e206024:RW
HDMI_RAM_PACKET_4_5_MASK 0xffffffff
DMA8_TI_DEST_INC_SET 0x00000010
DMA4_TXFR_LEN_XLENGTH_BITS 15:0
DMA_CB_ADDR(n) MACRO
DMA_ENABLE_EN14_SET 0x00004000
A2W_PLLD_ANA_SSCLR 0x7e102a50:RW
I2C_SPI_SLV_CR_CPOL_SET 0x00000010
CM_PLLA_DIGRST_CLR 0xfffffdff
PWM_CTL_USEF3_CLR 0xffdfffff
SMI_DSW2_WPACE_BITS 14:8
DMA10_CS_PRIORITY_LSB 16
PCM_MODE_A_FSLEN_BITS 9:0
ARM_TRANSLATE 0x7E00B000 +0x100:RW
DMA4_NEXTCONBK_MASK 0xffffffe0
TXP_CTRL 0x7e00400c:RW
DMA12_DEBUG_DMA_ID_CLR 0xffff00ff
AUX_MU_IIR_IRQ 0x06
PM_PADS5_HYST_BITS 3:3
MS_SEMA_25_MASK 0x00000001
DMA9_SOURCE_AD_S_ADDR_MSB 31
PWM_STA_GAPO2_LSB 5
USB_DOEPCTL4_WIDTH 32
CM_EMMCCTL_BUSYD_CLR 0xfffffeff
APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL0 0x7ee0602c:RW
APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL1 0x7ee06030:RW
GP_FSEL1_FSEL15_LSB 15
CAM0_CAMIDS_MASK 0xffffffff
GP_LEN1_RESET 0000000000
DMA7_CS_ABORT_SET 0x40000000
HDMI_AN0_WIDTH 32
PCM_DREQ_A_TX_LSB 8
CM_ARMDIV_RESET 0x00001000
DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
EMMC_CONTROL0_HCTL_CRDDET_S_MSB 7
CM_PLLA_LOADPER_MSB 6
HDMI_SCHEDULER_CONTROL_MODE_ACTIVE_MSB 1
CM_V3DCTL_KILL_MSB 5
PM_PADS4_RESET 0x0000001b
MPHI_MOUTFS_UFLOW_BITS 31:31
A2W_PLLA_PER_CHENB_SET 0x00000100
EMMC_IRPT_MASK_CCRC_ERR_MSB 17
AVE_IN_STATUS_VFORM_FIELD_SET 0x00001000
ASB_ISP_S_CTRL_CLR_REQ_BITS 0:0
CM_HSMDIV_WIDTH 16
DMA_INT_STATUS_INT3_SET 0x00000008
A2W_PLLD_CTRLR_MASK 0x000373ff
AVE_IN_CTRL_OVERRUN_IRQ_EN_SET 0x00000001
DMA1_DEST_AD_D_ADDR_LSB 0
PM_PADS2_POWOK_MSB 5
DMA1_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
CM_OTPCTL_BUSYD_MSB 8
DMA6_DEBUG_DMA_STATE_BITS 24:16
MPHI_HSINDFS_DFIFOLVL_SET 0x00000001
GP_FSEL0_FSEL01_BITS 5:3
PWMCTL_POLA1 4
MS_SEMA_30_MASK 0x00000001
PWMCTL_POLA3 20
PWMCTL_POLA4 28
L1_D0_WR_THRUS_MASK 0000000000
DMA14_CS_WIDTH 32
USB_DIEPEMPMSK_EP_TXF_EMP_MSK_LSB 0
EMMC_STATUS_CMD_INHIBIT_BITS 0:0
CM_INTEN_GAINB_LSB 1
DMA8_DEBUG_FIFO_ERROR_CLR 0xfffffffd
HDMI_TX_PHY_TX_PHY_TMDS_CFG_RESET 0x0000001f
SCALER_DISPCTRL_HVS_EN_MSB 31
HDMI_CEC_CNTRL_1 0x7e9020e8:RW
HDMI_CEC_CNTRL_2 0x7e9020ec:RW
HDMI_CEC_CNTRL_3 0x7e9020f0:RW
HDMI_CEC_CNTRL_4 0x7e9020f4:RW
HDMI_CEC_CNTRL_5 0x7e9020f8:RW
DMA9_TI_SRC_DREQ_SET 0x00000400
USB_DIEPINT6_WIDTH 32
V3D_DBQRUN_MASK 0xffffffff
DMA10_TI_WAIT_RESP_LSB 3
ASB_H264_M_CTRL_FULL_LSB 3
DSI0_PHYC_dsi_esc_lpdt_CLR 0xfffc0fff
FPGA_MB_SDC_H264_FREQ_MASK 0xffffffff
USB_HCINT0_STALL_BITS 3:3
L1_IC1_CONTROL_DISABLE_VLINE_SET 0x00000060
A2W_PLLD_CORE_BYPEN_MSB 9
SD_DQLCRC8_MASK 0xffffffff
CM_PLLH_LOADAUX_CLR 0xfffffffd
HDMI_CEC_RX_DATA_3_WIDTH 32
PCM_GRAY_RXFIFOLEVEL_SET 0x003f0000
EMMC_IRPT_EN_SDOFF_ERR_LSB 23
MPHI_C0INDCF_HANDLE_RESET 0x0
EMMC_INTERRUPT_DTO_ERR_CLR 0xffefffff
DMA4_TI_DEST_INC_BITS 4:4
DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
DSI1_LP_DLT6_MASK 0xffffffff
GP_FEN2_FENn64_LSB 0
PCM_CS_A_TXSYNC_BITS 13:13
PWM_STA_STA2_MSB 10
CM_TSENSCTL_SRC_BITS 1:0
USB_DOEPDMA12_WIDTH 32
A2W_PLLD_ANA_SSCS_STEP_CLR 0xffff0000
MS_SEMA_15_RESET 0000000000
SCALER_DISPECTRL_PANIC_CTRL_MSB 6
MS_SEMA_6_WIDTH 1
USB_HCSPLT3_WIDTH 32
PM_DSI0_CTRLEN_BITS 0:0
USB_DCTL_GNP_IN_NAK_STS_MSB 2
HDMI_CRP_CFG_WIDTH 28
SCALER_DISPBKGND1_WIDTH 32
DMA11_DEBUG_VERSION_MSB 27
CCP2TX_TS_TFF_CLR 0xffffffdf
USB_DOEPTSIZ5_MASK 0xffffffff
MS_SEMA_9_MASK_LSB 0
FPGA_DCM_CTRL_REMOTE_EN_SET 0x00001f00
A2W_PLLB_SP0_DIV_SET 0x000000ff
A2W_SMPS_L_SCVR_MASK 0x0000001f
PIARBCTL_CAM_LIMIT_MSB 1
A2W_PLLC_FRAC_MASK 0x000fffff
DMA15_CS_MASK 0xf0ff017f
SD_CS_SDTST_SET 0x00000020
I2C_SPI_SLV_CR_RESET 0000000000
SMI_DSW0_WHOLD_MSB 21
EMMC_SLOTISR_VER_VENDOR_CLR 0x00ffffff
PWMCTL_MSEN(n) MACRO
DSI1_CTRL_WIDTH 32
EMMC_INTERRUPT_CCRC_ERR_MSB 17
CM_DPICTL_SRC_MSB 3
USB_DOEPCTL11_WIDTH 32
PWM_STA_RERR1_BITS 3:3
CM_GP0CTL_ENAB_LSB 4
CM_PWMCTL_MASH_SET 0x00000600
SD_DQLCRC4_FALL_RESET 0x0
EMMC_CONTROL1_SRST_DATA_MSB 26
SYSAC_TRANS_PRIORITY_N_PRIORITY_MSB 3
I2C1_A 0x7e80400c:RW
DMA15_DEBUG_DMA_STATE_CLR 0xfe00ffff
CM_SLIMCTL_KILL_MSB 5
SLIM_DCC1_CON_RESET 0000000000
AUX_MU_LCR_8BITS 0x03
INTERRUPT_HARDINT_OFFSET 64
GROPCTR_FBC_EZ_CLRFLG_FETCHES 0x32
APERF1_BW1_CTRL_LATHALT_BITS 28:28
MPHI_INTCTRL_HSDISC_MSB 16
A2W_SMPS_A_VOLTSR_WIDTH 5
CM_TD0CTL_STEP_LSB 12
A2W_HDMI_CTL_RCALR_MASK 0x00011f33
A2W_PLLB_ANA_SCTL_MASK 0x0000001f
TXP_CTRL_BUSY_LSB 1
EMMC_HWCAP0_WIDTH 32
USB_GAXIDEV_MASK 0xffffffff
EMMC_STATUS_NEW_READ_DATA_MSB 11
USB_HCDMA7 0x7e9805f4:RW
MS_SEMA_15_MASK_SET 0x00000001
CM_EVENT_BADPASS_BITS 18:18
A2W_PLLH_ANA_STAT_DATA_SET 0x00000fff
CAM1_CAMCAP0_MASK 0xffffffff
DMA14_CS_ERROR_CLR 0xfffffeff
USB_GUSBCFG_ULPI_EXT_VBUS_DRV_CLR 0xffefffff
DMA2_STRIDE_D_STRIDE_LSB 16
DMA11_DEBUG_DMA_STATE_BITS 24:16
A2W_PLLD_CORE_RESET 0x00000100
A2W_PLLH_ANA_STAT_RCALDONE_BITS 12:12
I2C_SPI_SLV_CR_TESTFIFO_MSB 11
A2W_PLLC_ANA_KAIP_KP_SET 0x0000000f
I2C_SPI_SLV_MIS_RXMIS_SET 0x00000001
PM_GNRIC_POWUP_BITS 0:0
CM_DFTCTL_ENAB_SET 0x00000010
USB_DVBUSDIS 0x7e980828:RW
APERF0_BW0_RPEND_WIDTH 8
USB_GRXSTSP_HST_PKT_STS_CLR 0xffe1ffff
SD_SECEND0_ADDR_LS_SET 0x00001fff
SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_CLR 0xffff00ff
TB_BOOT_OPT_TCL_SIM_CLR 0xfffffff7
PIXELVALVE0_HORZA_WIDTH 32
PIXELVALVE0_VERTB_EVEN 0x7e206020:RW
SMI_DSR1_RDREQ_LSB 7
V3D_BPCS_WIDTH 32
TB_JTB_CONFIG_TDI_RISE_LSB 9
DMA10_CS_RESET_MSB 31
DMA9_TI_DEST_IGNORE_BITS 7:7
SMI_DSR0 0x7e600010:RW
DMA7_CS_PAUSED_SET 0x00000010
A2W_PLLD_PERR 0x7e102d40:RW
HDMI_RAM_PACKET_10_4_WIDTH 32
EMMC_IRPT_MASK_ACMD_ERR_CLR 0xfeffffff
L1_IC1_PRIORITY_IC1_APRIORITY3_MSB 15
EMMC_HWCAP1_DRV18_TYPED_LSB 6
CM_PLLA_LOADCCP2_LSB 2
DMA0_TI_INTEN_BITS 0:0
ASB_H264_S_CTRL_CLR_REQ_CLR 0xfffffffe
CM_TECCTL_KILL_BITS 5:5
USB_DCTL_IGN_FRM_NUM_RESET 0x0
DMA_ENABLE_EN0_LSB 0
SD_SA_CLKSTOP_LSB 7
DMA6_TXFR_LEN_YLENGTH_CLR 0xc000ffff
I2C_SPI_SLV_DEBUG1_DATA_MSB 25
SLIM_DMA_DC_CON_MASK 0x000fffff
DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
A2W_PLLD_ANA_SSCSR 0x7e102950:RW
DMA4_DEBUG_FIFO_ERROR_MSB 1
HDMI_ENCODER_CTL 0x7e902070:RW
HDMI_RAM_GCP_3_RESET 0000000000
PM_AVS_STAT_ALERT_H264_I_LSB 2
GP_LEV2_RESET 0000000000
SMI_CS_PVMODE_RESET 0x0
PCM_CS_A_RESET 0000000000
DMA14_SOURCE_AD_S_ADDR_SET 0xffffffff
PM_SMPS_CTRLEN_BITS 0:0
ADCR0 0x1C00E000 + 0x04:RW
ADCR1 0x1C00E000 + 0x08:RW
I2C1_C_MASK 0x00008701
CM_PLLB_LOADARM_BITS 0:0
TE_0VSWIDTH 0x7e20e004:RW
FPGA_CTRL0_SPI0_SEL_A_LSB 9
USB_GUSBCFG_ULPI_UTMI_SEL_SET 0x00000010
APERF0_GEN_CTRL_RESET_BITS 1:1
SD_SF_PHYHOLD_BITS 29:29
CM_GP1CTL_BUSY_MSB 7
DMA10_CS_INT_SET 0x00000004
CM_TSENSCTL_WIDTH 10
V3D_CT1LC_MASK 0xffffffff
HDMI_RAM_PACKET_12_1_RESET 0000000000
SMI_BASE_DIRECT 0x7E601000
GP_HEN2_HENn64_SET 0x0000003f
SMI_FD_WIDTH 14
GP_FSEL5_FSEL54_MSB 14
SD_DQLCRC10_FALL_SET 0x0000ffff
APERF0_BW0_CTRL_ID_EN_RESET 0x0
PM_STATUS_WIDTH 24
CM_PLLD_HOLDCORE_LSB 5
PM_XOSC_RESET 0000000000
A2W_HDMI_CTL_RCAL_MANREN_LSB 12
MS_ICSET_1_ICSET_1_LSB 0
GP_SEN1_RESET 0x003fffff
PCM_MODE_A_FSM_SET 0x00200000
FPGA_CTRL0_TERMEN_DO_MSB 16
A2W_PLLC_ANA_SCTL_RESET_MSB 4
A2W_PLLA_CTRL_PRSTN_LSB 17
A2W_PLLA_CTRLR_MASK 0x000373ff
SH_VDD_RESET 0000000000
USB_GRSTCTL_H_SFT_RST_LSB 1
SYSAC_V3D_PRIORITY_MASK 0x0000000f
USB_GHWCFG3_TRANS_COUNT_WIDTH_BITS 3:0
CM_PLLTCTL_BUSY_SET 0x00000080
DMA14_TI_DEST_INC_BITS 4:4
CM_PLLH_DIGRST_MSB 9
CAM0_CAMCLK_RESET 0x00000002
DMA12_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
A2W_SMPS_A_MULTI_MASK 0000000000
DMA8_TXFR_LEN_XLENGTH_SET 0x0000ffff
CM_TDCLKEN_PLLDDIV2_LSB 7
USB_GPVNDCTL_REG_ADDR_MSB 21
PM_RSTS_HADSRF_BITS 9:9
USB_DIEPCTL0_SET_ODD_FR_RESET 0x0
SLIM_MC_OUT_CON_WIDTH 7
CM_GP0CTL_BUSY_SET 0x00000080
DMA15_DEBUG_READ_ERROR_CLR 0xfffffffb
AVE_OUT_STATUS_VFRONT_PORCH_LSB 7
USB_DOEPCTL0_SNAK_RESET 0x0
PCM_TXC_A_CH1WEX_LSB 31
SYSAC_V3D_LIMITER_HOLDOFF_CLR 0xfffffffe
DMA8_TXFR_LEN_XLENGTH_BITS 15:0
USB_DFIFO2_WIDTH 32
CM_PWMCTL_SRC_CLR 0xfffffff0
A2W_SMPS_L_SCV_VOLTS_LSB 0
MS_SEMA_11_MASK_MSB 0
ST_C0 0x7e00300c:RW
ST_C1 0x7e003010:RW
SH_CMD_LONG_RESPONSE_LSB 9
ST_C3 0x7e003018:RW
GP_LEV1_LEVn32_SET 0xffffffff
I2C_SPI_SLV_MIS_WIDTH 4
CM_EVENT_OCDONE_MSB 21
DMA4_CONBLK_AD_SCB_ADDR_MSB 31
PM_PADS2_WIDTH 6
SD_CS_MASK 0x01ffffff
USB_HCINT0_AHB_ERR_LSB 2
SD_WDC 0x7ee00028:RO
CM_DSI0ECTL_ENAB_BITS 4:4
UART_IIR_FCR 0x7e201008:RW
GP_FSEL0_RESET 0000000000
DMA3_SOURCE_AD_S_ADDR_CLR 0x00000000
ST_CS 0x7e003000:RW
HDMI_READ_POINTERS_DOMAIN_RESYNC_RD_MSB 26
PIXELVALVE2_C_MASK 0x00ffffff
HDMI_HORZB_MANUAL_HFP_SET 0x00000200
ALIAS_ANY_L1_NONALLOCATING(x) MACRO
USB_GPVNDCTL_CTRL_ULPI_LSB 8
SYSAC_UC_ARBITER_CONTROL_DELAY_BITS 3:2
DMA1_TI_INTEN_CLR 0xfffffffe
GP_FSEL6_FSEL64_SET 0x00007000
V3D_PCTR12_MASK 0xffffffff
DMA6_STRIDE_S_STRIDE_LSB 0
MS_STATUS_STATUS_MSB 31
DMA0_CS_ERROR_SET 0x00000100
USB_GOTGCTL_B_SES_VLD_SET 0x00080000
MULTICORE_SYNC_ICCLR_0 MULTICORE_SYNC_BASE_ADDRESS + 0x98:RW
MULTICORE_SYNC_ICCLR_1 MULTICORE_SYNC_BASE_ADDRESS + 0x9C:RW
DMA13_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
SD_VIN_MULT_RESET 0x0
CM_DFTCTL_BUSYD_BITS 8:8
SLIM_DCC3_PROT_MASK 0xc001ffff
DMA11_DEBUG_DMA_ID_MSB 15
DMA10_TI_SRC_DREQ_LSB 10
EMMC_CONTROL1_CLK_INTLEN_CLR 0xfffffffe
SMI_DSW3_WPACEALL_BITS 15:15
AUX_MU_CNTL_REG (0x7E215000 +0x060)
CM_PCMDIV_RESET 0000000000
HDMI_CPU_MASK_STATUS_RESET 0x0001ffff
HDMI_HDCP_KEY_2_WIDTH 32
GP_FEN0_FENn0_CLR 0x00000000
SD_PT1_T_INIT1_RESET 0x28
GP_REN0_RENn0_LSB 0
EMMC_HWCAP0_SLOT_TYPE_BITS 31:30
HD_MAI_THR_PANICLOW_CLR 0xffc0ffff
CM_EVENT_LOSSB_MSB 6
SD_DQLCRC4_FALL_SET 0x0000ffff
I2C_SPI_SLV_DR_RXDMABREQ_BITS 13:13
CAM0_CAMIDC_RESET 0000000000
AVE_IN_BUF1_ADDRESS 0x7e91000c:RW
MS_SEMA_13_WIDTH 1
MPHI_AXIPRIV_WIDTH 9
USB_DIEPINT0_TIMEOUT_CLR 0xfffffff7
JMCTRL_NUMCMP (1 << 8)
DMA7_TI_PERMAP_SET 0x001f0000
EMMC_CONTROL0_PWCTL_HWRST_SET 0x00001000
CM_CAM0CTL_FRAC_LSB 9
AVE_OUT_CB_COEFF_BLUE_COEFF_SET 0x000003ff
CM_ISPCTL_FRAC_MSB 9
USB_DTHRCTL_WIDTH 28
DMA1_TI_WIDTH 27
SD_DQLCRC1_FALL_RESET 0x0
USB_GUSBCFG_OTG_I2C_SEL_SET 0x00010000
SH_CMD_READ_CMD_CLR 0xffffffbf
HDMI_VERTA1_MANUAL_VSP1_MSB 24
L1_IC1_PRIORITY_WIDTH 16
HD_VID_CTL_FULSYNC_MSB 22
PCM_MODE_A_RESET 0000000000
PM_AVS_EVENT_ALERT_V3D_G_CLR 0xfffffff7
CM_DPICTL_FRAC_BITS 9:9
SH_TOUT_WIDTH 32
DMA2_TXFR_LEN_YLENGTH_MSB 29
USB_DTXFSTS0_MASK 0xffffffff
CM_H264DIV 0x7e10102c:RW
HDMI_DETECTED_HORZB_MANUAL_HBP_BITS 29:20
A2W_PLLB_DIG1_RESET 0x00004000
UART_LSR_FE_MSB 3
DMA3_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
HD_VID_CTL_CLRRGB_RESET 0x0
DMA8_CS_MASK 0xf0ff017f
CCP2TX_TS_TXB_CLR 0xfffffffe
DMA9_TI_DEST_INC_SET 0x00000010
SD_SECSRT2_EN_MSB 0
DMA10_TXFR_LEN_WIDTH 16
SD_SB_ROWBITS_LSB 2
USB_GOTGCTL_SES_REQ_RESET 0x0
MPHI_OUTDDB_HANDLE_MSB 27
VEC_WSE_VPS_DATA_1 0x7e8060cc:RW
SH_HCFG_BLOCK_IRPT_EN_CLR 0xfffffeff
PWMCTL_MODE1 1
PWMCTL_MODE2 9
PWMCTL_MODE3 17
PWMCTL_MODE4 25
EMMC_CONTROL1_CLK_FREQ_MS2_MSB 7
GP_FSEL5_FSEL50_LSB 0
MPHI_HSINDCF_EMPTY_RESET 0x0
I2C_SPI_SLV_IFLS_RXIFPSEL_CLR 0xfffff1ff
INTERRUPT_SDC ((64) + 35 )
SD_VIN_MULT_CLR 0xfeffffff
PCM_GRAY_CLR_MSB 1
CM_SDCCTL_KILL_SET 0x00000020
DMA_INT_STATUS_INT8_MSB 8
DMA7_TI_WAIT_RESP_CLR 0xfffffff7
L1_IC0_CONTROL_DISABLE_SET 0x00000001
GP_AFEN1 0x7e20008c:RW
GP_AFEN2 0x7e200090:RW
DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
VCE_BUSY_MEMSYNC 0x0a
AJB_BITS0 0x000000
AJB_BITS4 0x000004
DMA6_TI_BURST_LENGTH_SET 0x0000f000
DMA2_TXFR_LEN_XLENGTH_LSB 0
AJB_BITS8 0x000008
USB_DOEPTSIZ10 0x7e980c50:RW
USB_DOEPTSIZ11 0x7e980c70:RW
USB_DOEPTSIZ12 0x7e980c90:RW
PM_GRAFX_MEMREP_CLR 0xfffffff7
DMA3_STRIDE_MASK 0xffffffff
USB_DOEPTSIZ15 0x7e980cf0:RW
SCALER_DISPCTRL_TILE_WID_BITS 17:16
SMI_DSW0_WSETUP_MSB 29
CM_GNRICDIV_MASK 0x00ffffff
AJB_RESETN 0x004000
A2W_PLLB_ANA1R_MASK 0x00ffffff
I2C_SPI_SLV_FR_RXBUSY_MSB 5
USB_GHWCFG3_I2C_INTERFACE_SET 0x00000100
CM_OSCFREQF_FRAC_SET 0x000fffff
A2W_PLLA_PERR_WIDTH 10
A2W_PLLC_ANA_SCTL_SEL_SET 0x00000007
DMA7_CS_DREQ_BITS 3:3
SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_RESET 0x0
FPGA_CTRL0_SW_SPI_SDA_O_SET 0x00000080
IC0_FORCE1_SET_WIDTH 32
L1_IC1_BP_HITS_WIDTH 0
A2W_SMPS_L_SPVR 0x7e1029d0:RW
CM_GP1CTL_BUSY_BITS 7:7
GP_AJBTMS_MASK 0xffffffff
SH_HSTS_REW_TIME_OUT_BITS 7:7
SLIM_DCC0_STAT 0x7e21020c:RW
L1_L1_SANDBOX_START5_START_ADDR_LSB 5
HDCP_KEY_CTL_START_MSB 0
DMA11_DEBUG_READ_ERROR_MSB 2
CAM0_CAMDAT1_RESET 0x00000002
A2W_PLLA_ANA_STAT_MASK 0x00000fff
GP_PUDCLK1_WIDTH 32
HDMI_VERTA0_MANUAL_VAL0_BITS 12:0
FPGA_CTRL0_SPI0_SEL_B_MSB 12
SMI_CS_AFERR_SET 0x02000000
EMMC_INTERRUPT_CBAD_ERR_LSB 19
USB_GI2CCTL_DAT_SE0_MSB 28
MPHI_HSINDS_WORDS_MSB 20
CM_DSI1PCTL_WIDTH 10
DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
APERF0_BW2_RMAX 0x7e0098e4:RO
SD_DQLCRC3_RISE_CLR 0x0000ffff
CM_INTEN_GAINC_BITS 2:2
A2W_PLLH_ANA_STAT_MASK 0x001f1fff
DMA3_SOURCE_AD 0x7e00730c:RO
MS_SEMA_0_RESET 0000000000
DMA1_TI_DEST_IGNORE_CLR 0xffffff7f
I2C_SPI_SLV_DR_RXDMABREQ_MSB 13
SD_SB_BANKLOW_RESET 0x0
ARM_3_SEM0 (0x7E00B000 +0xB00)+0x00:RW
ARM_3_SEM1 (0x7E00B000 +0xB00)+0x04:RW
ARM_3_SEM2 (0x7E00B000 +0xB00)+0x08:RW
TS_TSENSCTL_EN_INT_SET 0x00000020
ARM_3_SEM4 (0x7E00B000 +0xB00)+0x10:RW
CAM1_CAMDBSA0_MASK 0xffffffff
ARM_3_SEM6 (0x7E00B000 +0xB00)+0x18:RW
ARM_3_SEM7 (0x7E00B000 +0xB00)+0x1C:RW
DMA3_DEST_AD_D_ADDR_BITS 31:0
DMA14_CS_PRIORITY_BITS 19:16
ASB_ISP_S_CTRL_CLR_ACK_CLR 0xfffffffd
CAM0_CAMCTL_RESET 0000000000
IC0_APB_ID 0x494e5445
GP_FSEL6_FSEL60_BITS 2:0
DMA14_TI_SRC_IGNORE_MSB 11
SH_EDM_STATE_MACHINE_LSB 0
USB_GPVNDCTL_CTRL_ULPI_RESET 0x0
ARM_3_SEMS (0x7E00B000 +0xB00)+0x00:RW
IC0_VADDR_WIDTH 32
CM_DSI1ECTL_ENAB_MSB 4
SD_DQRCRC4_FALL_MSB 15
DMA11_CS_PANIC_PRIORITY_MSB 23
HDMI_RAM_GCP_1_WIDTH 32
A2W_SMPS_CTLC3_MASK 0x00ffffff
DMA13_TI_DEST_IGNORE_CLR 0xffffff7f
CM_GP0CTL_SRC_MSB 3
USB_DOEPCTL0_NAK_STS_CLR 0xfffdffff
MPHI_MOUTFS_MASK 0xbfffffff
GP_FSEL5_FSEL52_BITS 8:6
HDMI_DETECTED_VERTA1_MANUAL_VFP1_CLR 0xfff01fff
EMMC_CONTROL2_ACBAD_ERR_BITS 4:4
DMA3_TXFR_LEN_WIDTH 30
A2W_PLLA_CTRL_PRSTN_BITS 17:17
MPHI_OUTDDA_START_SET 0xffffffff
EMMC_INTERRUPT_DEND_ERR_MSB 22
CAM0_CAMICS_RESET 0000000000
CM_EMMCCTL_SRC_CLR 0xfffffff0
A2W_XOSC_CTRL_DDREN_LSB 4
I2CDEL_REDL (0)
SD_DQRCRC13_FALL_LSB 0
GP_FSEL4_FSEL44_BITS 14:12
EMMC_TUNE_STEPS_STD 0x7e30008c:RW
DMA3_TI_WAIT_RESP_SET 0x00000008
TS_TSENSSTAT_DATA_BITS 9:0
EMMC_STATUS_WIDTH 29
DMA11_NEXTCONBK_ADDR_CLR 0x0000001f
MPHI_C0INDDB_LENGTH_SET 0x000fffff
CM_CAM1DIV_DIV_MSB 15
CM_SLIMCTL_MASK 0x000007bf
SLIM_DCC5_CON 0x7e2102a8:RW
V3D_PCTR0 0x7ec00680:RW
DMA10_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
GP_FSEL3_FSEL36_BITS 20:18
AVE_IN_CTRL_LENGTH_IN_PXLS_SET 0x00000100
L1_L1_SANDBOX_START3_CTRL_SET 0x00000001
USB_DIEPTSIZ0_SUP_CNT_BITS 30:29
MS_ICCLR_0_RESET 0000000000
CM_PLLC_DIGRST_LSB 9
MS_SEMA_18_MASK_MSB 0
A2W_XOSC0_RESET 0x00820080
CM_SDCCTL_ACCPT_MSB 16
USB_DPTXFSIZ13_MASK 0xffffffff
CM_INTEN_RESUS_MSB 22
DSI0_PHYC_txhsclk_cont_sync_MSB 10
PCM_CS_A_TXTHR_SET 0x00000060
GP_FSEL2_FSEL28_BITS 26:24
A2W_PLLH_ANA_STAT_DATA_BITS 11:0
PM_GNRIC_MEMREP_MSB 3
CM_ISPCTL_ENAB_LSB 4
V3D_CT1CA 0x7ec00000 +0x0114:RW
MS_SEMA_24_MASK_LSB 0
USB_GINTMSK_DISCONN_INT_RESET 0x0
SMI_DCS_DONE_MSB 2
HDMI_SCHEDULER_CONTROL_USE_POSTLN_AVOID_MSB 14
CM_PLLA_HOLDCCP2_SET 0x00000008
I2C1_DEL 0x7e804018:RW
CM_PCMDIV_DIV_CLR 0xff000000
A2W_XOSC_PWR_PWRDN_SET 0x00000002
USB_GSNPSID_MASK 0xffffffff
SD_DQRCRC5_RISE_CLR 0x0000ffff
I2C_SPI_SLV_HCTRL_DATA_SET 0x000000ff
CMI_USBCTL_GATE_CLR 0xffffffbf
EMMC_IRPT_EN_READ_RDY_MSB 5
EMMC_BLKSIZECNT_SDMA_BLKSIZE_CLR 0xffff8fff
DMA_INT_STATUS_INT4_LSB 4
DMA8_CS_ERROR_CLR 0xfffffeff
CM_CKSM_STATE_CLR 0xffffff00
DMA_TI_D_128 (1<<5)
V3D_BASE_ADDRESS 0x1A005000
CCP2TX_TC_TIP_BITS 15:8
SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_CLR 0xfffffff3
SD_SB_BANKLOW_MSB 6
TXP_DIM_WIDTH_BITS 11:0
USB_DOEPCTL0_CNAK_MSB 26
SH_CMD_WRITE_CMD_CLR 0xfffffe7f
SD_TMC_TSTCLK_BITS 0:0
HDMI_MBIST_TM_RESET 0000000000
A2W_PLLC_ANA1R_RESET 0x001d0000
V3D_PCTR6 0x7ec006b0:RW
CM_PULSECTL_BUSY_BITS 7:7
HDMI_DVO_TIMING_ADJUST_D_RESET 0x88888888
I2C_SPI_SLV_DMACR_TXDMAE_LSB 1
A2W_PLLA_ANA_KAIPR_WIDTH 11
DMA4_CS_RESET_MSB 31
AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_SET 0x00004000
HDMI_KSV_FIFO_0_RESET 0000000000
USB_GRXSTSP_MASK 0x01ffffff
EMMC_CMDTM_TM_BLKCNT_EN_SET 0x00000002
A2W_PLLD_ANA_KAIP_KP_SET 0x0000000f
SD_DQLCRC0_FALL_BITS 15:0
USB_GINTMSK_CON_ID_STS_CHNG_BITS 28:28
APERF1_BW0_RPEND_WIDTH 8
CM_LOCK_LOCKB_SET 0x00000002
GP_FSEL0_FSEL02_MSB 8
ST_BASE 0x7e003000
A2W_PLLD_DIG1_RESET 0x00004000
EMMC_IRPT_MASK_INT_A_LSB 9
CM_TIMERCTL_KILL_LSB 5
HD_MAI_CTL_RESET 0x00000020
GP_FSEL2_FSEL23_CLR 0xfffff1ff
DSI0_HSTX_TO_C_WIDTH 24
USB_GUSBCFG_ULPI_CLK_SUS_M_RESET 0x0
RNG_STATUS_MASK 0xffffffff
SMI_CS_DONE_MSB 1
EMMC_HWMAXAMP0_AMP_18V_LSB 16
GP_SEN0_RESET 0xffffffff
PM_PXLDO_RSTPLLDR_CLR 0xfffdffff
EMMC_FORCE_IRPT_READ_RDY_LSB 5
DMA8_TI_WIDTH 26
V3D_CT1EA 0x7ec00000 +0x010c:RW
AVE_OUT_CTRL_MODE_BITS 5:4
DMA5_TI_BURST_LENGTH_CLR 0xffff0fff
SD_DQRCRC11_FALL_BITS 15:0
A2W_XOSC_CTRL_PLLAEN_SET 0x00000040
MPHI_OUTDS_HANDLE_CLR 0xe01fffff
CM_TDCLKEN_PLLBBYP_LSB 1
USB_GUSBCFG_CORRUPT_TX_CLR 0x7fffffff
EMMC_RESP0_MASK 0xffffffff
V3D_SCRATCH 0x7ec00000 +0x0010:RW
DMA_ENABLE_EN0_MSB 0
A2W_PLLA_CTRL_PWRDN_LSB 16
SH_EDM_WRITE_THRESHOLD_BITS 13:9
DMA3_DEBUG_VERSION_CLR 0xf1ffffff
USB_HCDMA7_WIDTH 32
HDMI_VERTA0 0x7e9020cc:RW
HDMI_VERTA1 0x7e9020d4:RW
EMMC_IRPT_MASK_CARD_IN_MSB 6
AVE_OUT_Y_COEFF_GREEN_COEFF_BITS 19:10
IC1_FORCE1_MASK 0xffffffff
SD_DQLCRC12_RISE_MSB 31
A2W_PLLC_ANA_KAIPR_MASK 0x0000077f
SD_DQRCRC7_MASK 0xffffffff
USB_DIEPTXF12_MASK 0xffffffff
SD_DQLCRC9_FALL_MSB 15
CM_DSI1ECTL_KILL_CLR 0xffffffdf
PCM_CS_A_RXF_CLR 0xffbfffff
HDMI_TX_PHY_HDMI_TX_PHY_PLL_CFG (HDMI_BASE_ADDRESS + 0x2c0) + 16:RW
HDMI_BKSV0_MASK 0xffffffff
USB_GHWCFG3_SYNC_RESET_TYPE_RESET 0x0
L2_CONT_OFF_l2_enable_stats_MSB 5
CM_CAM1CTL_BUSY_LSB 7
PM_SPARER_RESET 0000000000
PCM_CH2EN (1 << 14)
SMI_DSW1_WWIDTH_SET 0xc0000000
GP_FSEL1_FSEL12_SET 0x000001c0
MPHI_C1INDS 0x7e006014:RW
HD_VID_CTL_VPOL_CLR 0xefffffff
EMMC_BLKSIZECNT_BLKSIZE_MS1_CLR 0xffff7fff
ARM_S_ACKSTOP 0x80000000
SH_HCFG_WIDE_EXT_BUS_BITS 2:2
HDMI_VERTB0 0x7e9020d0:RW
HDMI_VERTB1 0x7e9020d8:RW
DMA12_SOURCE_AD 0x7e007c0c:RO
SD_DQRCRC2_RISE_MSB 31
CM_DSI1ECTL_SRC_BITS 3:0
CM_PWMCTL_MASH_BITS 10:9
SD_SD_T_RC_MSB 24
DSI0_INT_EN_MASK 0x0fffffff
USB_HCINT0_NYET_BITS 6:6
AVE_IN_CTRL_PRIV_MODE_MSB 7
DMA2_DEBUG_LITE_SET 0x10000000
L1_D_FLUSH_E_MASK 0x3fffffe0
FPGA_DCM_WR_DATA_ADDRESS_MSB 23
TB_BOOT_OPT_BOOT_HALT_CLR 0xffffff7f
DMA2_TI_SRC_DREQ_BITS 10:10
DMA2_SOURCE_AD 0x7e00720c:RO
ASB_V3D_M_CTRL 0x7e00a00c:RW
HD_MAI_CTL_ERRORE_LSB 2
EMMC_INTERRUPT_BOOTACK_CLR 0xffffdfff
I2C1_DIV 0x7e804014:RW
EMMC_EXRDFIFO_CFG_RD_THRSH_MSB 2
A2W_PLLA_CORE_DIV_MSB 7
ARM_MYIRQ_BELL 0x00000001
USB_PCGCR_GATE_HCLK_SET 0x00000002
PM_CCP2TX_LDOCTRL_MSB 18
GP_FSEL6_FSEL69_MSB 29
FPGA_STATUS0_SPARE_IN_BITS 31:19
ASB_ISP_S_CTRL_CLR_REQ_CLR 0xfffffffe
USB_HCINTMSK6_MASK 0xffffffff
FPGA_CTRL0_DIS_RST_MSB 3
PIXELVALVE0_VERTA_MASK 0xffffffff
DMA8_TI_SRC_IGNORE_BITS 11:11
HD_SPARE_MASK 0xffffffff
A2W_XOSC_PWR_PWRDN_BITS 1:1
INTERRUPT_SMI ((64) + 47 )
CCP2RDR1 CCP2_BASE_ADDRESS + 0x80:RO
CCP2RDR2 CCP2_BASE_ADDRESS + 0x84:RO
CM_CCP2CTL_RESET 0000000000
AUX_MU_STAT_TX_IDLE 0x00000008
V3D_PCTRS13_WIDTH 5
USB_DTXFSTS13_WIDTH 32
SDCS 0x7ee00000:RW
ASB_ISP_M_CTRL_EMPTY_SET 0x00000004
HD_CSC_CTL_USERGB2YCC_BITS 1:1
ARM_0_BELLCLRDBG (0x7E00B000 +0x800)+0xE4:RW
AVE_IN_STATUS_FRAME_RATE_BITS 9:8
PWM_CTL_PWEN3_MSB 16
DMA13_TI_WAIT_RESP_SET 0x00000008
MPHI_C0INDDA_START_RESET 0x0
TB_JTB_CONFIG_OUT_MS_LSB 6
USB_GINTMSK_SOF_CLR 0xfffffff7
HDMI_RAM_PACKET_4_8_RESET 0000000000
AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_BITS 11:0
HD_VID_CTL_UFEN_CLR 0xbfffffff
I2C_SPI_SLV_DR_TXFE_BITS 20:20
USB_GI2CCTL_RW_BITS 30:30
GP_EDS0_MASK 0xffffffff
DMA14_CS_END_SET 0x00000002
HDMI_CTS_PERIOD_0_RESET 0x010124f8
SH_HCFG_REL_CMD_LINE_BITS 0:0
USB_HCFG 0x7e980400:RW
CM_PLLB_DIGRST_MSB 9
USB_GPVNDCTL_NEW_REG_REQ_SET 0x02000000
IC0_FORCE1_CLR 0x7e002054:RW
USB_GHWCFG2_NUM_HOST_CHAN_RESET 0x0
A2W_SMPS_B_STAT_VOLTS_LSB 0
USB_GI2CCTL_DEV_ADR_SET 0x0c000000
HDMI_READ_POINTERS_DRFT_FULL_MINUS_CLR 0xffefffff
CM_PLLH_LOADRCAL_BITS 2:2
SMI_DA_WRITE_MSB 9
AVE_IN_STATUS_MASK 0x9f733f7f
CCP2RDS0 CCP2_BASE_ADDRESS + 0x128:RW
CCP2RDS1 CCP2_BASE_ADDRESS + 0x228:RW
EMMC_CONTROL0_ALT_BOOT_EN_LSB 22
PIXELVALVE1_STAT_MASK 0x000003ff
DMA11_TI_SRC_DREQ_LSB 10
GRPCS 0x1A005600 + 0x00:RW
EMMC_CONTROL0_GAP_RESTART_LSB 17
HDMI_READ_POINTERS_DRFT_HOLD_RD_BITS 22:22
VEC_SECAM_GAIN_VAL_WIDTH 32
CM_AVEOCTL_BUSY_LSB 7
HDMI_HDCP_KEY_1_WIDTH 32
DMA10_TI_SRC_INC_LSB 8
MPHI_C1INDFS 0x7e006024:RW
A2W_XOSC_CTRL_DDROK_CLR 0xfffeffff
L1_L1_SANDBOX_START2_CTRL_LSB 0
V3D_SLCACTL_MASK 0xffffffff
DMA1_SOURCE_AD_S_ADDR_SET 0xffffffff
DMA6_DEBUG_DMA_ID_LSB 8
PIXELVALVE0_DSI_HACT_ACT_WIDTH 16
A2W_PLLC_ANA_KAIPR 0x7e102b30:RW
A2W_PLLD_DIG1R_RESET 0x00004000
EMMC_FORCE_IRPT_CMD_DONE_SET 0x00000001
MPHI_INTSTAT_TXEND_RESET 0x0
I2C0_C_RESET 0000000000
IC1CS 0xffffffff:RW
SDEM SD_EM
L1_D_PRIORITY_c1_per_priority_SET 0x0f000000
A2W_PLLD_DSI0_MASK 0x000003ff
PWM_CTL_SBIT2_SET 0x00000800
SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_MSB 5
HDMI_VERTA0_MANUAL_VAL0_CLR 0xffffe000
SMI_DSW2_WHOLD_MSB 21
EMMC_IRPT_EN_DMA_ERR_SET 0x10000000
A2W_PLLD_CTRLR_RESET 0x00010000
DSI1_HS_DLT5_RESET 0000000000
I2C_SPI_SLV_DR_TXBUSY_LSB 16
DMA10_CS_ACTIVE_BITS 0:0
V3D_DBQITC_MASK 0xffffffff
HD_CSC_14_13_RESET 0000000000
DMA15_CS_PANIC_PRIORITY_MSB 23
AUX_MU_STAT_RX_OFLW 0x00000010
USB_GOTGCTL_HST_NEG_SCS_SET 0x00000100
CM_DPIDIV_WIDTH 16
HDMI_DETECTED_VERTB1_WIDTH 22
A2W_PLLA_DIG3R_MASK 0x00ffffff
MPHI_C1INDCF_LENERR_BITS 30:30
DPHY_CSR_GLBL_DQ_MSTR_DLL_BYP_EN 0x7ee07014:RW
SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_CLR 0xffffffcf
MPHI_MINFS_LEVEL_LSB 0
A2W_PLLB_CTRL_PDIV_BITS 14:12
PM_RSTS_HADSRQ_BITS 8:8
DMA7_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
SPI_CS_CLEAR_CLR 0xffffffcf
USB_DCTL_GNP_IN_NAK_STS_RESET 0x0
USB_GINTMSK_I2C_INT_CLR 0xfffffdff
VPU_ARB_CTRL_L2_ALGORITHM_CLR 0xffffff3f
DMA12_CS_PRIORITY_LSB 16
DMA2_DEBUG_READ_ERROR_CLR 0xfffffffb
SMI_DSW2_WDREQ_BITS 7:7
CCP2TX_TD_TCS_LSB 0
CCP2TX_APB_ID 0x63637032
USB_GINTMSK_HCH_INT_SET 0x02000000
DMA9_NEXTCONBK_ADDR_BITS 31:5
ASB_V3D_M_CTRL_CLR_REQ_LSB 0
HDMI_13_AUDIO_CFG_1_WIDTH 10
SMI_DSW3_WWIDTH_MSB 31
SH_HCFG_SLOW_CARD_MSB 3
SD_CS_STBY_MSB 3
USB_DIEPDMAB3_WIDTH 32
DMA7_TI_WAIT_RESP_MSB 3
SMI_DSR2_RSETUP_MSB 29
CM_TECDIV_DIV_LSB 12
CAM0_CAMPRI 0x7e80000c:RW
TXP_CTRL_FIELD_CLR 0xfffffff7
CM_V3DCTL_GATE_MSB 6
ASB_V3D_S_CTRL_WCOUNT_BITS 23:14
DMA14_TI_BURST_LENGTH_SET 0x0000f000
INTERRUPT_UART ((64) + 57 )
MPHI_HSINDS_VALID_SET 0x40000000
MPHI_OUTDDA_START_MSB 31
USB_GHWCFG3_SYNC_RESET_TYPE_SET 0x00000800
V3D_CT1LC 0x7ec00000 +0x0124:RW
CM_CAM1CTL_KILL_MSB 5
CM_GNRICCTL_SRC_SET 0x0000000f
DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
HDMI_SCHEDULER_CONTROL_HSYNC_PHYST_EN_MSB 16
SD_DQRCRC12_WIDTH 32
L1_IC1_CONTROL_BP_DISABLE_MSB 3
MPHI_INTCTRL_IMFOFLW_CLR 0xfffffeff
SD_REORD_MASK 0x0fffffff
EMMC_HWCAP0_BASEMHZ_BITS 15:8
CCP2TAC 0x7e001008:RW
DMA9_CS_PAUSED_CLR 0xffffffef
EMMC_INTERRUPT_ACMD_ERR_LSB 24
EMMC_FORCE_IRPT_DEND_ERR_MSB 22
SD_SECSRT2_ADDR_LS_BITS 12:1
SD_MR_RDATA_LSB 16
EMMC_HWCAP1_DRV18_TYPEA_SET 0x00000010
HD_MAI_CTL_CHALIGN_LSB 13
AVE_IN_STATUS_BUF0_COMPL_LSB 1
TXP_PROGRESS_LINES_CLR 0xfffff000
CCP2TX_TDL_LEN_CLR 0xc0000000
USB_DFIFO11_MASK 0xffffffff
DMA3_TI_SRC_INC_LSB 8
PIARBCTL_CAM_DELAY_RESET 0x0
DMA12_CS_DREQ_MSB 3
L1_L1_SANDBOX_START3_RESET 0000000000
SD_DQLCRC15_FALL_RESET 0x0
A2W_XOSC_CTRLR 0x7e102990:RW
HDMI_READ_POINTERS_DRFT_WR_ADDR_LSB 8
CM_DSI0PCTL_BUSYD_SET 0x00000100
USB_GUSBCFG_IND_COMP_LSB 23
HD_VID_CTL_FULSYNC_RESET 0x0
EMMC_IRPT_MASK_INT_C_MSB 11
USB_DIEPCTL0_CNAK_LSB 26
ASB_V3D_S_CTRL_FULL_CLR 0xfffffff7
HDMI_TX_PHY_SPREAD_SPECTRUM_WIDTH 32
SD_PRE 0x7ee000b0:RO
DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
GPFEN1 0x7e200000 + 0x5C:RW
GPFEN2 0x7e200000 + 0x60:RW
USB_GGPIO_GPO_CLR 0x0000ffff
UART_LCR_EPS_SET 0x00000010
DSI0_PHYC_txulpshs_1_sync_LSB 6
CM_BURSTCTL_BUSY_LSB 7
MPHI_C0INDCF_HANDLE_MSB 27
CM_INTEN_LOSSH_LSB 9
DMA4_TI_BURST_LENGTH_LSB 12
CCP2TBA 0x7e00101c:RW
AVE_OUT_Y_COEFF_BLUE_COEFF_LSB 0
DMA14_TI_SRC_INC_CLR 0xfffffeff
USB_GHWCFG4_EN_DESC_DMA_BITS 30:30
TS_TSENSCTL_DIRECT_BITS 6:6
SD_SECSRT2_MASK 0xffffffff
SMI_DSW1_WFORMAT_SET 0x00800000
A2W_SMPS_L_SCV_MASK 0x0000001f
AVE_IN_STATUS_FRAME_RATE_DET_SET 0x00000040
DMA11_DEST_AD_D_ADDR_BITS 31:0
A2W_PLLD_ANA_VCO_RANGE_BITS 0:0
A2W_PLLC_ANA_SSCL 0x7e102230:RW
EMMC_CONTROL0_PWCTL_SDVOLTS_SET 0x00000e00
I2C_SPI_SLV_IFLS_TXIFPSEL_CLR 0xfffffe3f
A2W_PLLC_ANA_SSCS 0x7e102130:RW
EMMC_FORCE_IRPT_CMD_DONE_BITS 0:0
ARM_2_MAIL1_WRT (0x7E00B000 +0xA00)+0xA0:RW
CM_TD0CTL_BUSYD_MSB 8
PM_IMAGE_ISPRSTN_MSB 8
UART_LCR_LOOP_SET 0x00000010
SMI_CS_CLEAR_SET 0x00000010
DMA6_CS 0x7e007600:RW
SYSAC_PERI_ARBITER_CONTROL_LIMIT_CLR 0xfffffffc
CAM1_CAMIBSA0 0x7e801110:RW
CAM1_CAMIBSA1 0x7e801304:RW
SD_CS_IDLE_SET 0x00000200
SPI_DLEN 0x7e20400c:RW
EMMC_INTERRUPT_DMA_ERR_SET 0x10000000
SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_RESET 0x0
DMA1_DEST_AD_MASK 0xffffffff
APERF1_BW1_CTRL_ID_EN_SET 0x20000000
PIARBCTL_CAM_CHANNEL_INIBIT_BITS 15:8
VEC_FREQ1_0 0x7e806184:RW
V3D_PCTRC_MASK 0x0000ffff
I2C1_DLEN_MASK 0x0000ffff
HDMI_HORZA_MANUAL_VPOL_LSB 14
SMI_DSW1_WSTROBE_BITS 6:0
SD_PT1 0x7ee00014:RW
SD_PT2 0x7ee00010:RW
L1_D1_WR_MISSES 0x7ee02198:RO
CM_AVEOCTL_KILL_MSB 5
SD_DQRCRC11_RISE_SET 0xffff0000
DMA1_NEXTCONBK_MASK 0xffffffe0
DMA4_TI_WAIT_RESP_MSB 3
EMMC_HWMAXAMP0_WIDTH 24
PM_AVS_STAT_ALERT_SYSTEM_A_LSB 1
L1_D0_WBACKS_WIDTH 0
CM_TDCLKEN_SLIMDFT_MSB 12
DMA15_TI_INTEN_MSB 0
TXP_CTRL_TEST_MODE_LSB 4
PM_PROC_WIDTH 23
USB_HPRT_TST_CTL_RESET 0x0
L2_IN_FLIGHT_WIDTH 4
SYSAC_UC_ARBITER_CONTROL_ALGORITHM_MSB 7
DSI1_TXPKT1_C_WIDTH 32
MS_MBOX_5_MBOX_LSB 0
CM_TCNTCTL_SRC1_CLR 0xffffcfff
DMA8_TI_DEST_WIDTH_SET 0x00000020
A2W_PLLH_CTRL_PWRDN_BITS 16:16
SD_RWC_LASTCNT_MSB 20
USB_DCTL_TST_CTL_LSB 4
CM_H264CTL_FRAC_CLR 0xfffffdff
USB_GRSTCTL_C_SFT_RST_RESET 0x0
EMMC_IRPT_MASK_DMA_ERR_LSB 28
USB_DOEPCTL0_SNP_MSB 20
CCP2TDL 0x7e001020:RW
PM_IMAGE_MEMREP_SET 0x00000008
HDMI_RAM_PACKET_3_6_RESET 0000000000
PM_SPAREW_SPARE_SET 0x00ffffff
EMMC_SLOTISR_VER_VENDOR_LSB 24
HDMI_RAM_PACKET_8_4_WIDTH 32
AVE_IN_CTRL_ENABLE_CLR 0x7fffffff
EMMC_IRPT_MASK_CMD_DONE_LSB 0
DMA14_CS_PRIORITY_MSB 19
VPU_ARB_CTRL_L2_DELAY_BITS 3:2
USB_HCINT0_DATA_TGL_ERR_MSB 10
AVE_IN_SYNC_CTRL 0x7e910040:RW
DMA10_TI_DEST_IGNORE_LSB 7
SD_CS_RESTRT_MSB 0
MS_SEMA_0_MASK_SET 0x00000001
GP_HEN0_HENn0_LSB 0
PM_DSI1_LDOLPEN_LSB 1
PM_PROC_ISFUNC_MSB 5
V3D_CT1PC 0x7ec00000 +0x012c:RW
DMA0_CS_ACTIVE_SET 0x00000001
A2W_XOSC_MULTI 0x7e102f90:RW
DMA1_TI_SRC_WIDTH_LSB 9
A2W_PLLD_CORE 0x7e102440:RW
SD_RWC_RSTMAX_LSB 31
SLIM_DCC3_PA0 0x7e210260:RW
SLIM_DCC3_PA1 0x7e210264:RW
CM_CKSM_AUTO_LSB 20
CM_PLLC_LOADCORE1_BITS 2:2
HDMI_RAM_PACKET_4_6_WIDTH 32
I2C_SPI_SLV_CR_MASK 0x0001ffff
DMA_ENABLE_EN6_LSB 6
I2C_SPI_SLV_DMACR_DMAONERR_MSB 2
A2W_PLLB_ANA_KAIPR_WIDTH 11
FPGA_CTRL0_SPI0_SEL_B_SET 0x00001000
FPGA_STATUS0_SD_CD_MSB 5
SD_DQRCRC14_MASK 0xffffffff
USB_DIEPDMAB12_WIDTH 32
I2CDIV_2 0x7e805000 + 0x14:RW
DMA7_TI_SRC_INC_CLR 0xfffffeff
DMA10_TI_WAITS_LSB 21
APERF1_BW2_RMAX_WIDTH 24
A2W_PLLA_CORE_BYPEN_MSB 9
DMA5_SOURCE_AD_S_ADDR_BITS 31:0
DMA1_CS_ABORT_MSB 30
DMA4_CS_PANIC_PRIORITY_SET 0x00f00000
DMA9_TI_PERMAP_CLR 0xffe0ffff
PCM_TXC_A_CH2WEX_MSB 15
DMA10_TI_PERMAP_SET 0x001f0000
V3D_INTENA_MASK 0xffffffff
CMI_CAMTEST_ENAB_LSB 4
IC0_MASK4_MASK 0x77777777
DMA_INT_STATUS_INT5_BITS 5:5
TB_JTB_CONFIG_INV_CLK_BITS 7:7
I2C_SPI_SLV_VCSTAT 0x7e214030:RW
DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
DMA0_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
SD_RWC_RXOVR_BITS 7:7
SD_CMD_MASK 0x0fffffff
HDMI_PACKET_FIFO_CFG_WIDTH 1
DMA15_SOURCE_AD_S_ADDR_MSB 31
GP_FSEL6_FSEL62_BITS 8:6
DMA8_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
CM_SDCCTL_CTRL_CLR 0xffff0fff
DSI0_PHYC 0x7e209040:RW
PM_RSTS_HADWRF_CLR 0xffffffdf
CCP2RSA1 CCP2_BASE_ADDRESS + 0x20C:RW
PWM_STA_GAPO4_MSB 7
CAM1_CAMDCS_MASK 0xffffffff
USB_GINTMSK_ENUM_DONE_LSB 13
HDMI_RAM_PACKET_6_3_RESET 0000000000
VCE_SEMA_CLEAR 0x7f000000 + 0x140024:RW
HD_MAI_CTL_ERRORE_RESET 0x0
DMA11_TI_DEST_WIDTH_SET 0x00000020
DMA_CS_PRIORITY (1<<16)
AVE_IN_STATUS_FRAME_RATE_DET_BITS 6:6
CM_OTPCTL_FRAC_LSB 9
CCP2TX_TD_IES_CLR 0xffffff9f
I2C0_A_WIDTH 7
CMNVT 0x7C:RW
GP_FSEL3_FSEL38_CLR 0xf8ffffff
PCM_DREQ_A_TX_PANIC_LSB 24
SMI_DSR1_RPACE_MSB 14
HDMI_RAM_GCP_6_MASK 0xffffffff
USB_DIEPCTL0_MPS_CLR 0xfffff800
SCALER_DISPSTAT_DSP2_IRQ_CLR 0x00000007
MS_SEMA_12_MASK_CLR 0xfffffffe
PWM_DMAC_PANIC_SET 0x0000ff00
MS_ICSET_1_MASK 0x00000001
V3D_PCTRS6_WIDTH 5
HDMI_RAM_PACKET_10_1_MASK 0xffffffff
DMA6_TI_WAITS_SET 0x03e00000
HDMI_RAM_PACKET_2_5_RESET 0000000000
PIXELVALVE0_INTEN_MASK 0x000003ff
APERF1_BW0_CTRL_ID_SET 0x00001f00
AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_CLR 0x00000000
V3D_DBQGHC_WIDTH 32
DSI1_HS_DLT3_WIDTH 32
TS_TSENSSTAT_MASK 0x00000fff
MPHI_CTRL_DIRECT_RESET 0x0
EMMC_DMA_STATUS_MASK 0xffff00ff
OTP_JTAG_VPU_PARITY_REDUNDANT 76
A2W_PLLD_CORE_DIV_LSB 0
HDMI_RAM_PACKET_8_6_RESET 0000000000
SYSAC_PERI_ARBITER_CONTROL_LIMIT_MSB 1
PM_CCP2TX_LDOEN_LSB 1
DMA6_CS_ABORT_MSB 30
SYSAC_HVSM_PRIORITY 0x7e009008:RW
DMA9_TXFR_LEN_XLENGTH_MSB 15
SD_DQRCRC11_RISE_LSB 16
PM_IMAGE_PERIRSTN_CLR 0xffffffbf
DMA9_DEBUG_OUTSTANDING_WRITES_BITS 7:4
SCALER_DISPALPHA2_MASK 0xffffffff
SD_PT1_WIDTH 28
SMI_DSR2_MODE68_LSB 23
DMA14_DEBUG_FIFO_ERROR_CLR 0xfffffffd
A2W_PLLC_DIG0R 0x7e102820:RW
APERF1_BW0_CTRL_MASK 0xf0001f1f
A2W_PLLD_ANA_SSCLR_MASK 0x0001ffff
HD_HDM_CTL_PDSTBY_MSB 5
CM_INTEN_GAIND_MSB 3
USB_GHWCFG2_FSPHY_INTERFACE_SET 0x00000300
ARM_T_RAWIRQ 0x7E00B000 +0x410:RW
SYSAC_V3D_LIMITER_SPARE_BITS 3:1
A2W_PLLC_ANA_SSCS_STEP_SET 0x0000ffff
DSI1_TXPKT_PIXD_FIFO_RESET 0000000000
PWM_DMA ( 5*(1<<16))
DMA9_TI_SRC_IGNORE_SET 0x00000800
UART_LSR_DR_CLR 0xfffffffe
USB_GINTMSK_OEP_INT_BITS 19:19
SDWDC 0x7ee00028:RO
USB_GRSTCTL_TXF_FLSH_SET 0x00000020
HD_VID_CTL_EMPSYNC_LSB 20
SD_DQLCRC12_FALL_RESET 0x0
USB_GINTMSK_PRT_INT_MSB 24
CM_PLLD_HOLDPER_LSB 7
PM_AVS_EVENT_ALERT_SYSTEM_A_BITS 1:1
USB_GUSBCFG_ULPI_FS_LS_LSB 17
GP_FSEL2_FSEL27_SET 0x00e00000
DMA10_CS_INT_BITS 2:2
V3D_IDENT3_WIDTH 32
DMA3_CONBLK_AD_SCB_ADDR_LSB 5
USB_DIEPTXF1_MASK 0xffffffff
A2W_SMPS_CTLB1_WIDTH 24
A2W_PLLC_DIG1R 0x7e102824:RW
IC0_FORCE1_SET_MASK 0xffffffff
DMA3_STRIDE_S_STRIDE_BITS 15:0
I2C_SPI_SLV_IFLS_RESET 0x00000492
USB_HCFG_LS_PHY_CLK_SEL_CLR 0xfffffffc
IC0_MASK3_RESET 0000000000
DMA6_SOURCE_AD_WIDTH 32
L1_L1_SANDBOX_END4_RESET 0000000000
CCP2TIC 0x7e001014:RW
MPHI_CTRL_REQ_SOFT_RST_SET 0x00010000
L1_IC0_CONTROL_ENABLE_STATS_BITS 2:2
CM_SMICTL_WIDTH 10
CM_CAM0CTL_KILL_BITS 5:5
CM_TD0CTL_ENAB_SET 0x00000010
CM_UARTDIV_MASK 0x003fffff
EMMC_IRPT_EN_DEND_ERR_CLR 0xffbfffff
SD_PHYC_CRC_EN_LSB 20
A2W_XOSC_CTRL_HDMIOK_BITS 13:13
SD_SE_T_XSR_RESET 0x28
SD_SECSRT0_EN_LSB 0
PWMDMAC 0x7e20c000 + 0x08:RW
SMI_DSW3_WSWAP_MSB 22
SD_TMC_TS_CLR 0xfffffffd
SDPT SD_PT
L1_L1_SANDBOX_START1_WIDTH 30
SMI_DC_PANICW_MSB 17
EMMC_HWMAXAMP0_AMP_30V_SET 0x0000ff00
MPHI_CTRL_STBY_RESET 0x1
DMA3_TI_DEST_DREQ_MSB 6
SCALER_DISPECTRL_WIDTH 32
A2W_PLLC_DIG2R 0x7e102828:RW
I2C_SPI_SLV_HCTRL 0x7e214034:RW
DMA11_DEST_AD_WIDTH 32
DMA12_TI_SRC_DREQ_LSB 10
DMA8_TI_INTEN_MSB 0
EMMC_SPI_INT_SPT_SELECT_LSB 0
L2_WR_HITS_WIDTH 32
SD_DQLCRC3_FALL_CLR 0xffff0000
PM_PADS6_POWOK_SET 0x00000020
USB_DOEPDMA15_MASK 0xffffffff
EMMC_INTERRUPT_CBAD_ERR_CLR 0xfff7ffff
DMA14_TI_SRC_DREQ_BITS 10:10
DMA9_DEBUG_READ_ERROR_BITS 2:2
USB_HFNUM 0x7e980408:RW
PWM_CTL_USEF1_CLR 0xffffffdf
USB_HPRT_EN_CHNG_RESET 0x0
AVE_OUT_CR_COEFF_GREEN_COEFF_CLR 0xfff003ff
SMI_DSW2_WSWAP_LSB 22
HDMI_RAM_PACKET_CONFIG_RESET 0000000000
VEC_INTERRUPT_CONTROL_WIDTH 32
A2W_PLLC_DIG3R 0x7e10282c:RW
SDSECEND0 0x7ee00040:RW
SDSECEND1 0x7ee00048:RW
SDSECEND2 0x7ee00050:RW
SDSECEND3 0x7ee00058:RW
VIDEO_ENC_PrimaryControl 0x7e806068:RW
L1_L1_SANDBOX_START4_MASK 0x3fffffff
A2W_XOSC_CTRL_PLLDOK_MSB 17
SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_BITS 5:4
CM_DSI0ECTL_FRAC_BITS 9:9
DMA9_TI_SRC_INC_MSB 8
DMA0_CS_RESET_BITS 31:31
DISPC_BASE_ADDRESS 0x1C009000
CAM0_CAMDBSA0_WIDTH 32
DMA6_TI_DEST_DREQ_LSB 6
APERF0_BW0_CTRL_ID_EN_LSB 29
CM_PLLA_LOADDSI0_LSB 0
CM_CAM1CTL_WIDTH 10
FPGA_CTRL0_DIS_CTL2_MSB 2
DSI_INT_STATUS 0x7e209000 + 0x24:RW
HDMI_VERTB0_MANUAL_VBP0_MSB 8
PIXELVALVE1_VERTB 0x7e207018:RW
APERF0_BW2_CTRL_RESET_MSB 31
AVE_IN_CHAR_CTRL_MASK 0x8000000f
MPHI_OUTDFS_DFIFOLVL_LSB 0
SMI_DSW3_WWIDTH_BITS 31:30
I2C_SPI_SLV_ICR_OEIC_CLR 0xfffffff7
A2W_PLLD_DSI1_DIV_CLR 0xffffff00
GP_LEV2_LEVn64_CLR 0xffffffc0
PM_CAM1_LDOLPEN_BITS 1:1
AVE_OUT_CTRL_INVERT_DSYNC_SET 0x00040000
A2W_SMPS_L_SCA_ANA_SET 0x00000fff
AVE_IN_OUTSTANDING_BUFF0_RESET 0000000000
CM_H264CTL_KILL_BITS 5:5
PM_DSI0_LDOHPEN_LSB 2
CM_TCNTCNT_CNT_MSB 23
DMA5_CS_ACTIVE_LSB 0
DMA_INT_STATUS_INT1_SET 0x00000002
CAM0_CAMIDI1_RESET 0000000000
USB_HCFG_LS_SUPP_RESET 0x0
MS_SEMA_7_MASK_SET 0x00000001
DMA13_CS_PRIORITY_LSB 16
SH_TOUT_TIME_OUT_BITS 31:0
USB_GI2CCTL_SUSP_CTL_SET 0x02000000
AUX_SPI_CNTL0_POSTIN 0x00010000
DMA1_TI_SRC_IGNORE_MSB 11
PM_GNRIC_RSTN_CLR 0xfffff03f
GRFCBA 0x1A005400 + 0x14:RW
SDSA 0x7ee00004:RW
SDSB 0x7ee00008:RW
HDMI_RAM_PACKET_12_5_MASK 0xffffffff
MPHI_CTRL_STBY_LSB 27
DMA3_DEBUG_DMA_ID_BITS 15:8
A2W_XOSC_CTRL_PLLDOK_BITS 17:17
PCM_MODE_A_CLKI_CLR 0xffbfffff
CM_TD0DIV_MASK 0x00ffffff
APERF0_GEN_CTRL_RESET_SET 0x00000002
FPGA_CTRL0_TERMEN_CLK_LSB 17
OTP_MAX_ROW (((((((((((((((((((((8 +4)+4)+1)+1)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+1)
HDMI_PCI_CLEAR (HDMI_BASE_ADDRESS + 0x340) + 0x20:RW
USB_GRSTCTL_TXF_NUM_RESET 0x0
A2W_PLLB_FRACR_MASK 0x000fffff
VEC_DAC_MISC_MASK 0xffffffff
DMA10_DEBUG_FIFO_ERROR_MSB 1
USB_DOEPDMA5_WIDTH 32
SH_HCFG_WIDTH 11
A2W_XOSC_CTRL_HDMIOK_SET 0x00002000
GP_SEN0_SEN_LSB 0
SD_DQRCRC5_FALL_CLR 0xffff0000
PIARBCTL_CAM_LIMIT_RESET 0x0
A2W_PLLA_CCP2_DIV_SET 0x000000ff
PCM_CS_A_TXSYNC_CLR 0xffffdfff
OTP_CONFIG_REG 0x7e20f004:RW
USB_GHWCFG4_NUM_PERIO_EPS_BITS 3:0
A2W_PLLC_ANA_VCOR_RESET 0000000000
HDMI_READ_POINTERS_DRFT_ALMOST_FULL_MSB 21
PM_RSTS_HADSRQ_CLR 0xfffffeff
DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
A2W_PLLD_DSI1_CHENB_CLR 0xfffffeff
HDMI_VERTA0_RESET 0x002141e0
SLIM_DCC6_STAT_RESET 0000000000
I2C_SPI_SLV_HCTRL_DATA_BITS 7:0
SCALER_DISPSLAVE0_MASK 0xffffffff
A2W_PLLB_ANA_KAIP_KI_BITS 6:4
V3D_CT1PC_WIDTH 32
A2W_XOSC_MULTI_WIDTH 0
SLIM_DCC9_STAT_WIDTH 32
HDMI_RAM_PACKET_7_2_MASK 0xffffffff
CM_ARMCTL_BUSY_MSB 7
CM_UARTCTL_ENAB_LSB 4
USB_DOEPINT0_OUT_PKT_ERR_SET 0x00000100
SD_DQRCRC5_FALL_MSB 15
V3D_DBSSR_MASK 0xffffffff
HDMI_AUDIO_PACKET_CONFIG_MASK 0x3fffffff
HDMI_RAM_PACKET_1_1_MASK 0xffffffff
MPHI_C0INDDA_START_LSB 0
CM_TDCLKEN_IMAGETD_CLR 0xffffdfff
SYSAC_UC_ARBITER_CONTROL_LIMIT_BITS 1:0
DMA12_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
PCMMODE_CLKI (1 << 22)
USB_DOEPCTL0_SET_D0_PID_BITS 28:28
PCMMODE_CLKM (1 << 23)
PIARBCTL_CAM_RESET 0000000000
USB_HPTXSTS_HPTXFSPCAVAIL_BITS 15:0
CM_VPUCTL_GATE_LSB 6
DMA3_DEBUG_DMA_STATE_SET 0x01ff0000
MS_SEMA_19_MASK_CLR 0xfffffffe
ASB_ISP_M_CTRL_FULL_BITS 3:3
USB_DIEPDMAB4_MASK 0xffffffff
DMA14_TXFR_LEN_XLENGTH_SET 0x0000ffff
EMMC_STATUS_DAT_LEVEL0_CLR 0xff0fffff
APERF1_BW2_ATRANS_WIDTH 32
PM_GRAFX_POWUP_MSB 0
USB_GOTGINT_SES_REQ_SUC_STS_CHG_BITS 8:8
HDMI_RAM_PACKET_6_1_WIDTH 32
L1_D_PRIORITY_c1_per_priority_BITS 27:24
DMA12_TI_BURST_LENGTH_LSB 12
SCALER_OLEDCOEF2_WIDTH 32
A2W_PLLD_ANA_STATR_MASK 0x00000fff
EMMC_CONTROL1_CLK_EN_BITS 2:2
USB_DOEPINT7_MASK 0xffffffff
SD_SF_MDLL_CAL_MSB 8
DMA9_SOURCE_AD_S_ADDR_BITS 31:0
HD_HDM_CTL_ENDIAN_RESET 0x0
USB_GINTMSK_USB_SUSP_MSB 11
DMA8_CS_PANIC_PRIORITY_SET 0x00f00000
IS_ALIAS_COHERENT(x) MACRO
SD_SECSRT2_EN_RESET 0x0
SH_CMD_NEW_FLAG_MSB 15
CM_EVENT_LOSSC_BITS 7:7
HDMI_BCH_CONFIGURATION 0x7e9020bc:RW
DMA8_NEXTCONBK_ADDR_LSB 5
USB_GGPIO_GPO_RESET 0x0
DMA4_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
I2C_SPI_SLV_RIS_OERIS_LSB 3
EMMC_STATUS_DAT_INHIBIT_SET 0x00000002
USB_DIEPTXF1_FIFO_STADDR_RESET 0x0
HDMI_RAM_PACKET_2_3_WIDTH 32
APERF0_BW0_CTRL_EN_BITS 30:30
PWM_CTL_CLRF1_MSB 6
A2W_PLLH_ANA_KAIPR 0x7e102b70:RW
HDMI_DETECTED_VERTA0_MANUAL_VAL0_BITS 12:0
HDMI_13_AUDIO_CFG_1 0x7e902150:RW
USB_GI2CCTL_WIDTH 32
CMCAM 0x7C:RW
CM_DSI1EDIV_DIV_MSB 15
USB_HCCHAR0_MC_EC_BITS 21:20
TXP_XTRA_WIDTH 1
PM_DSI1_CTRLEN_CLR 0xfffffffe
HD_CSC_22_21_MASK 0xffffffff
DMA13_TI_DEST_DREQ_MSB 6
TS_TSENSSTAT_VALID_BITS 10:10
HD_MAI_CTL_BUSY_RESET 0x0
CM_DSI0PCTL_FRAC_LSB 9
MPHI_HSINDS_DISCARD_CLR 0x7fffffff
A2W_PLLH_DIG3_MASK 0x00ffffff
HD_VID_CTL_FULRGB_CLR 0xffdfffff
ASB_V3D_M_CTRL_RCOUNT_BITS 13:4
ASB_ISP_M_CTRL_CLR_ACK_BITS 1:1
MPHI_C1INDCF_HANDLE_RESET 0x0
APERF1_BW2_WTRANS_WIDTH 32
TH0T2UD 0x18011000 + 0x24:RW
HDMI_VERTA0_MANUAL_VFP0_MSB 19
CCP2TPC 0x7e00100c:RW
CM_OTPDIV_MASK 0x0001f000
SD_CS_STATEN_RESET 0x0
SMI_CS_PVMODE_CLR 0xffffefff
AVE_IN_CURRENT_LINE_BUF0_RESET 0000000000
USB_GOTGCTL_HNP_REQ_BITS 9:9
USB_GPVNDCTL_NEW_REG_REQ_LSB 25
CM_TDCLKEN_PLLCBYP_MSB 2
GP_AFEN2_WIDTH 6
A2W_PLLC_CORE0_BYPEN_MSB 9
VEC_CGMSAE_BOT_FORMAT_MASK 0xffffffff
I2C_SPI_SLV_RSR_RXDMAPREQ_CLR 0xffffffef
I2C_SPI_SLV_ICR_TXIC_LSB 1
DMA_INT_STATUS_INT13_BITS 13:13
DMA15_TI_WAIT_RESP_BITS 3:3
L2_CONT_OFF_l2_no_wr_allocate_MSB 1
TXP_DIM_WIDTH 28
VPU_ARB_CTRL_UC_DELAY_CLR 0xfffffff3
PWM_CTL_RPTL4_CLR 0xfbffffff
GP_PUDCLK2_PUDCLKn64_MSB 5
I2C0_CLKT_MASK 0x0000ffff
CM_SLIMCTL_RESET 0x00000200
A2W_HDMI_CTL_RCAL_MANR_CLR 0xfffff0ff
A2W_XOSC_CTRL_PLLCEN_CLR 0xfffffffe
SYSAC_USB_PRIORITY_PRIORITY_SET 0x0000000f
PM_AVS_INTEN_ALERT_PERI_A_BITS 0:0
A2W_PLLA_CTRL_MASK 0x000373ff
HDMI_SW_RESET_CNTRL_MASK 0x00000003
VEC_CONFIG2_MASK 0xffffffff
I2C_SPI_SLV_RSR_OE_LSB 0
PM_HDMI_CTRLEN_SET 0x00000001
PCM_CS_A_TXW_SET 0x00020000
L1_IC1_PRIORITY_IC1_APRIORITY1_MSB 7
USB_HPTXSTS 0x7e980410:RW
USB_GOTGCTL_DBNC_TIME_LSB 17
CM_INTEN_FLOSSC_SET 0x00010000
L1_L1_SANDBOX_START2_START_ADDR_LSB 5
V3D_CT1CS_MASK 0xffffffff
L1_L1_SANDBOX_END2_WIDTH 30
USB_GI2CCTL_DAT_SE0_RESET 0x0
DMA4_TI_WAITS_LSB 21
APERF0_BW1_RMAX_WIDTH 24
MPHI_C1INDS_DISCARD_MSB 31
USB_DTKNQR2_WIDTH 32
PCM_RXC_A_CH1EN_LSB 30
A2W_PLLC_ANA_KAIPR_WIDTH 11
A2W_PLLC_FRAC_FRAC_LSB 0
SMI_CS_START_LSB 3
SMI_DSW0_WDREQ_SET 0x00000080
USB_DOEPINT0_SETUP_CLR 0xfffffff7
ARM_I0_BELL1 0x00000008
SH_HSTS_CMD_TIME_OUT_BITS 6:6
SCALER_DISPBASE0_WIDTH 32
FPGA_CTRL0_DIS_RST_LSB 3
CM_TECCTL_ENAB_CLR 0xffffffef
PCM_CS_A_RXR_BITS 18:18
INTERRUPT_SDIO ((64) + 56 )
DMA_CH_BASE(n) MACRO
DSI0_TST_MON 0x7e209070:RW
DMA0_CONBLK_AD_MASK 0xffffffe0
USB_DCFG_PER_SCH_INTV_CLR 0xfcffffff
DMA9_DEBUG_DMA_ID_SET 0x0000ff00
SMICS_TEEN 8
DMA_INT_STATUS_INT0_BITS 0:0
CM_EVENT_FGAIND_CLR 0xffffdfff
I2C_SPI_SLV_CR_HOSTCTRLEN_MSB 12
SMI_DSW1_WSETUP_BITS 29:24
PM_CAM1_CTRLEN_MSB 0
SMI_DC_DMAP_SET 0x01000000
CRYPTO_ISR_RNG_INT 0x0100000
GP_FSEL3_FSEL32_SET 0x000001c0
A2W_PLLH_PIX_CHENB_SET 0x00000100
GP_FSEL5_FSEL52_MSB 8
EMMC_CONTROL0_WAKE_ONINT_EN_LSB 24
PCM_MODE_A_PDMN_LSB 27
DMA0_CS_RESET 0000000000
APERF1_BW0_WTRANS_RESET 0000000000
USB_HPRT_SUSP_SET 0x00000080
MPHI_INTCTRL_RX1DISC_BITS 4:4
MPHI_MOUTFS_LEVEL_BITS 9:0
FPGA_CTRL0_DISP_BUFFER_BITS 11:11
ASB_ISP_M_CTRL_FULL_MSB 3
DMA3_DEBUG_WIDTH 29
EMMC_STATUS_DAT_LEVEL1_CLR 0xe1ffffff
DMA4_CS_END_SET 0x00000002
A2W_PLLC_CORE1R_RESET 0x00000100
CCP2TSC 0x7e001010:RW
USB_DIEPTSIZ0_MC_RESET 0x0
STCS_0 0x7e003000:RW
DMA4_CS_PRIORITY_BITS 19:16
OTP_STATUS_REG 0x7e20f010:RO
SLIM_DCC9_CON 0x7e210328:RW
A2W_SMPS_L_SIA_ANA_CLR 0xfffffc00
DMA1_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
V3D_PCTRS10_MASK 0x0000001f
UART_MSR_DDCD_MSB 3
DMA9_TI_DEST_DREQ_CLR 0xffffffbf
DMA11_CS_DREQ_STOPS_DMA_LSB 5
DMA6_STRIDE_D_STRIDE_LSB 16
DMA3_TI_BURST_LENGTH_BITS 15:12
JP_C1BA 0x7e005050:RW
OTP_HDCP_AES_PARITY_SIZE_IN_ROWS 1
CM_DSI0ECTL_KILL_BITS 5:5
PWMCTL_PWEN(n) MACRO
A2W_PLLB_ANA_SSCS_MODE_BITS 16:16
A2W_PLLB_SP2_BYPEN_BITS 9:9
DMA6_TI 0x7e007608:RO
USB_GHWCFG2_DFIFO_DYNAMIC_SET 0x00080000
L2_CONT_OFF_l2_flush_LSB 2
PWM_DAT4_RESET 0000000000
DSI0_CMD_PKTH 0x7e209008:RW
HDMI_HORZA_MANUAL_HPOL_CLR 0xffffdfff
HDMI_MBIST_TM_MASK 0x00ffffff
UART_LCR_OUT2_SET 0x00000008
L1_IC0_PRIORITY_IC0_APRIORITY3_LSB 12
MPHI_AXIPRIV_RXPROT_CLR 0xffffff8f
PM_GNRIC_MRDONE_SET 0x00000010
GP_REN1_WIDTH 32
PM_HDMI_LDOCTRL_BITS 18:2
DMA10_CS_ERROR_SET 0x00000100
SH_RSP3_CID_CSD_LSB 0
DMA1_CS_DREQ_BITS 3:3
USB_GHWCFG2_SINGLE_POINT_CLR 0xffffffdf
SMI_DSR1_RPACE_CLR 0xffff80ff
A2W_PLLD_DIG2_MASK 0x00ffffff
A2W_PLLA_CCP2_DIV_BITS 7:0
USB_GNPTXSTS_TX_Q_SPC_AVAIL_MSB 23
A2W_PLLD_DIG2_RESET 0x00100401
MS_SEMA_20_MASK_BITS 0:0
DSI_HS_CLT0 0x7e209000 + 0x44:RW
TXP_DST_PTR 0x7e004000:RW
DSI_HS_CLT2 0x7e209000 + 0x4C:RW
SLIM_DCC6_STAT_WIDTH 32
USB_DIEPTSIZ9_MASK 0xffffffff
DMA9_DEBUG_FIFO_ERROR_LSB 1
CAM1_CAMCAP0 0x7e801034:RW
CAM1_CAMCAP1 0x7e801038:RW
DMA5_TI_DEST_DREQ_CLR 0xffffffbf
CM_INTEN_FGAIND_BITS 13:13
EMMC_FORCE_IRPT_CARD_OUT_LSB 7
DMA10_DEBUG_VERSION_SET 0x0e000000
HDMI_SCHEDULER_CONTROL_MODE_ACTIVE_SET 0x00000002
USB_DCTL_CGNP_IN_NAK_LSB 8
EMMC_BUS_CTRL_WIDTH 32
DMA12_CS_PAUSED_CLR 0xffffffef
AUX_SPI1_CNTL1_REG (0x7E215000 +0x0C4)
SMI_DSW2_WSTROBE_LSB 0
IC1_FORCE1_SET_MASK 0xffffffff
L1_L1_SANDBOX_START6_START_ADDR_CLR 0xc000001f
CAM1_CAMDBSA1 0x7e801310:RW
CM_EVENT_FLOSSA_BITS 14:14
EMMC_HWCAP1_DATA_RETUNE_MSB 15
A2W_PLLD_CTRL_PRSTN_MSB 17
HD_MAI_CTL_CHNUM_MSB 7
I2C_SPI_SLV_DR_TXFLEVEL_LSB 22
IMASK4_0 0x7e002020:RW
IMASK4_1 0xffffffff:RW
CM_TD1CTL_FRAC_CLR 0xfffffdff
GP_FSEL4_FSEL47_LSB 21
VEC_CGMSAE_TOP_DATA_MASK 0xffffffff
A2W_SMPS_L_SPV 0x7e1021d0:RW
USB_HCINT0_DATA_TGL_ERR_BITS 10:10
PM_AVS_EVENT 0x7e100084:RW
MPHI_CTRL_ENABLE_RESET 0x0
CM_PLLA_HOLDDSI0_SET 0x00000002
A2W_PLLB_SP1_WIDTH 10
USB_DIEPINT0_IN_EP_NAK_EFF_BITS 6:6
A2W_PLLD_ANA2R_MASK 0x00ffffff
A2W_XOSC_CTRL_PLLDEN_CLR 0xffffffdf
EMMC_DBG_SEL_SELECT_MSB 0
A2W_SMPS_L_SPAR_WIDTH 10
EMMC_IRPT_MASK_CARD_CLR 0xfffffeff
TB_JTB_PORTEN_MASK 0x000000ff
ASB_ISP_M_CTRL_CLR_REQ_CLR 0xfffffffe
EMMC_IRPT_EN_DTO_ERR_CLR 0xffefffff
USB_GOTGINT_WIDTH 20
WSE_VPS_DATA_1 0x7e8060cc:RW
AVE_IN_CTRL_BUF1_IRQ_EN_SET 0x00000004
SYSAC_PERI_ARBITER_CONTROL 0x7e00904c:RW
SD_PHYC_IOB_TMODE_BITS 12:12
USB_GINTMSK_IEP_INT_BITS 18:18
CM_PLLTCNT3_CNT_CLR 0xff000000
PIXELVALVE0_VSYNCD_EVEN 0x7e206008:RW
VEC_CGMSAE_REVID_WIDTH 32
HDMI_TX_PHY_HDMI_TX_PHY_SPARE (HDMI_BASE_ADDRESS + 0x2c0) + 32:RW
USB_HCFG_LS_SUPP_LSB 2
SD_CS_EN_CLR 0xfffffffd
SPI_CS_CSPOL_CLR 0xffffffbf
SMI_DSR0_RESET 0x0101000c
DMA2_SOURCE_AD_S_ADDR_MSB 31
USB_DOEPTSIZ0_WIDTH 32
HD_HDM_CTL_CECOVR_SET 0x00000100
EMMC_TUNE_STEP 0x7e300088:RW
IC1_FORCE1_WIDTH 32
DMA13_TI_SRC_DREQ_LSB 10
SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_LSB 4
HDMI_CEC_RX_DATA_1 0x7e90210c:RW
HDMI_CEC_RX_DATA_2 0x7e902110:RW
HDMI_CEC_RX_DATA_3 0x7e902114:RW
HDMI_CEC_RX_DATA_4 0x7e902118:RW
I2C_SPI_SLV_CR_I2C_CLR 0xfffffffb
CAM0_BASE 0x7e800000
SCALER_DISPCTRL_DSP2_IRQ_CTRL_LSB 11
MS_SEMA_30_RESET 0000000000
SYSAC_DMA_ARBITER_CONTROL_LITE 0x7e00905c:RW
A2W_PLLD_ANA3_MASK 0x00ffffff
SCALER_DISPCTRL_HVS_EN_LSB 31
USB_DOEPDMA10_MASK 0xffffffff
CM_TD0DIV_DIV_SET 0x00ffffff
EMMC_CONTROL2_ACNOX_ERR_MSB 0
FPGA_DCM_WR_DATA_MASK 0x00ffffff
CM_GP1DIV_DIV_BITS 23:0
ARM_S_WRITPEND 0x000FFC00
EMMC_HWCAP1_DRV18_TYPED_BITS 6:6
EMMC_IRPT_MASK_DTO_ERR_LSB 20
PCMCS_TXTHR_EMPTY (0 << 5)
FPGA_CTRL0_CAM_CTL0_MSB 0
DMA1_TI_MASK 0x07fffffb
L1_IC1_RAS_POPS 0x7ee020d4:RO
GP_AREN2_WIDTH 6
SMI_CS_EDREQ_RESET 0x0
CM_CCP2DIV_DIV_MSB 12
A2W_PLLH_PIX_BYPEN_BITS 9:9
AVE_IN_BUF1_ADDRESS_BUF1_ADDR_SET 0xffffffff
L1_IC0_RAS_UNDERFLOW_WIDTH 0
APHY_CSR_DDR_PLL_HOLD_CH 0x7ee0604c:RW
CCP2TX_TAC_ARST_CLR 0xfffffffe
SMI_DSW1_WPACE_CLR 0xffff80ff
A2W_PLLD_DSI1R_RESET 0x00000100
DMA12_DEST_AD 0x7e007c10:RO
DMA_INT_STATUS_INT12_SET 0x00001000
GP_CLR1_CLRn32_MSB 31
APERF1_GEN_CTRL_ENABLE_CLR 0xfffffffe
SYSAC_HOST_PRIORITY_PRIORITY_BITS 3:0
SCALER_DISPECTRL_SECURE_MODE_CLR 0x7fffffff
HDMI_SCHEDULER_CONTROL_VSYNC_RESET_VAL_BITS 21:18
CAM0_CAMDLT_WIDTH 32
DMA1_DEBUG_FIFO_ERROR_CLR 0xfffffffd
L1_L1_SANDBOX_END2_MASK 0x3fffffe0
SMI_DSR2_RPACEALL_SET 0x00008000
A2W_SMPS_CTLA0R_WIDTH 24
DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
SCALER_DISPECTRL_PROF_TYPE_SET 0x0c000000
MS_MBOX_4_MBOX_BITS 31:0
MS_ICSET_0_ICSET_0_LSB 0
SLIM_DCC8_PROT_WIDTH 32
CM_TDCLKEN_PLLADIV2_BITS 4:4
SDWTC 0x7ee00020:RO
MPHI_MINFS_RPTR_SET 0x3ff00000
CM_UARTDIV_WIDTH 22
USB_DSTS_ERRTIC_ERR_MSB 3
GP_SET1_SETn32_CLR 0x00000000
L1_D_CONTROL_DC_DISABLE_BITS 0:0
GP_FEN0_MASK 0xffffffff
DMA8_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
MS_SEMA_6_MASK_BITS 0:0
GP_FSEL2_FSEL28_LSB 24
SD_MR_ADDR_SET 0x000000ff
SD_SECSRT3_ADDR_LS_CLR 0xffffe001
SD_DQRCRC11_FALL_SET 0x0000ffff
HDMI_DETECTED_HORZB_MANUAL_HBP_LSB 20
USB_GINTMSK_INCOMPL_P_CLR 0xffdfffff
DMA2_DEBUG_VERSION_SET 0x0e000000
DSI0_PHYC_txulps_clk_sync_BITS 9:9
CAM1_CAMIVSTA_MASK 0xffffffff
DMA3_NEXTCONBK_ADDR_CLR 0x0000001f
AVE_IN_STATUS_BUF0_COMPL_CLR 0xfffffffd
PM_RSTS_HADWRQ_CLR 0xffffffef
DMA5_CS_DREQ_STOPS_DMA_BITS 5:5
CM_ARMCTL_BUSY_LSB 7
TB_PRINTER_DATA_WIDTH 32
L1_IC0_CONTROL_DISABLE_VLINE_SET 0x00000060
SYSAC_HOST_PRIORITY_PRIORITY_LSB 0
DMA15_CS_DREQ_STOPS_DMA_BITS 5:5
CM_V3DCTL_BUSYD_SET 0x00000100
CM_PLLTCNT0_WIDTH 24
PM_GRAFX_MEMREP_LSB 3
AVE_IN_STATUS_OVERRUN_CNT_BITS 28:24
L1_IC0_CONTROL_BP_DISABLE_LSB 3
DMA4_CS_ACTIVE_MSB 0
DSI0_LP_DLT6_RESET 0000000000
EMMC_IRPT_MASK_ENDBOOT_CLR 0xffffbfff
MS_SEMA_22_MASK_SET 0x00000001
DMA15_CS_ACTIVE_BITS 0:0
HD_MAI_CTL_PAREN_LSB 8
A2W_PLLB_ANA_MULTI 0x7e102ff0:RW
SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_MSB 7
DMA12_TI_PERMAP_CLR 0xffe0ffff
SD_MRT_T_MRW_SET 0x000001ff
L1_IC1_RAS_UNDERFLOW_MASK 0000000000
EMMC_CONTROL2_TUNED_BITS 23:23
SLIM_DCC4_PA0_MASK 0x00ffff1f
CM_GP2CTL_KILL_LSB 5
HDMI_SCHEDULER_CONTROL_ENC_ONLY_WHEN_AUTH_BITS 6:6
DPHY_CSR_CRC_DATA_RESET 0000000000
A2W_PLLA_FRAC_FRAC_LSB 0
SD_DQRCRC14_FALL_LSB 0
MPHI_HSINDCF_HANDLE_SET 0x0ff00000
USB_HPRT_SPD_MSB 18
DMA7_CS_RESET 0000000000
PWM_CTL_PWEN3_LSB 16
A2W_PLLB_CTRL_PRSTN_LSB 17
SD_PHYC_VREF_ENB_RESET 0x0
SCALER_DISPCTRL_DSP2_PANIC_CLR 0xcfffffff
TXP_CTRL_ALPHA_INVERT_CLR 0xffffefff
IC1_C 0x7e002800:RW
SMI_DSW0_WHOLD_BITS 21:16
APERF1_BW0_CTRL_BUS_CLR 0xffffffe0
SD_CS_RESTRT_CLR 0xfffffffe
EMMC_FORCE_IRPT_CARD_IN_BITS 6:6
GP_AJBTDO_MASK 0xffffffff
SD_DQRCRC7_WIDTH 32
SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_CLR 0xffffff3f
IC1_S 0x7e002804:RO
USB_HCSPLT0_COMP_SPLT_MSB 16
CM_GP2DIV 0x7e101084:RW
MS_IREQ_0_RESET 0000000000
I2C_SPI_SLV_CR_INV_RXF_MSB 10
CAM0_CAMDBG2_RESET 0000000000
CAM1_CAMCAP0_WIDTH 32
CM_OSCCOUNT 0x7e101100:RW
DMA12_DEBUG_OUTSTANDING_WRITES_BITS 7:4
DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
PM_WDOG_TIME_CLR 0xfff00000
A2W_PLLD_DIG2R 0x7e102848:RW
CM_DSI0PDIV_MASK 0x00001000
DMA15_TI_DEST_DREQ_CLR 0xffffffbf
MPHI_VERSION_MASK 0xffffffff
DMA5_DEBUG_OUTSTANDING_WRITES_LSB 4
A2W_PLLB_CTRL_PWRDN_CLR 0xfffeffff
PM_RSTC_SRCFG_BITS 9:8
DSI0_LPRX_TO_C 0x7e209034:RW
DMA11_DEBUG_DMA_STATE_SET 0x01ff0000
PM_USB_WIDTH 1
USB_DOEPCTL0_SET_D1_PID_RESET 0x0
EMMC_CONTROL1_SRST_HC_LSB 24
USB_DIEPTSIZ0_SUP_CNT_SET 0x60000000
V3D_CT0LC_MASK 0xffffffff
SYSAC_DMA_ARBITER_CONTROL_L2_WIDTH 16
A2W_PLLA_DIG2_RESET 0x00100401
DSI0_RX1_PKTH_MASK 0xffffffff
V3D_DBSCFG_MASK 0xffffffff
CM_ARMCTL_BUSY_BITS 7:7
SLIM_DCC3_STAT_WIDTH 32
EMMC_CONTROL1_DATA_TOUNIT_LSB 16
DMA11_CS_ERROR_LSB 8
USB_GPVNDCTL_REG_ADDR_RESET 0x0
DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
A2W_PLLD_DSI1_DIV_BITS 7:0
BOOTROM_BRCTL 0x10000000 + 0xC000:RW
PM_RSTC_DRCFG_SET 0x00000003
PCM_MODE_A_CLKM_SET 0x00800000
CM_PLLB_LOADARM_CLR 0xfffffffe
USB_DIEPCTL0_DPID_BITS 16:16
DMA14_CS_RESET_MSB 31
USB_DCTL_CGOUT_NAK_MSB 10
FPGA_MB_XH264_BUILD_NUM_WIDTH 32
AVE_IN_STATUS_OVERRUN_DET_MSB 0
PM_PXLDO_RSTOSCDR_BITS 16:16
SH_HBLC_MASK 0x0000ffff
PWM_DAT2_WIDTH 32
CCP2TX_TS_TEI_BITS 18:18
USB_DAINT_OUT_EP_INT_SET 0xffff0000
CM_DSI0EDIV_DIV_BITS 15:4
DMA6_TI_DEST_IGNORE_MSB 7
USB_GLPMCFG 0x7e980054:RW
DMA6_DEST_AD 0x7e007610:RO
CM_ISPCTL_SRC_SET 0x0000000f
V3D_PCTR10_MASK 0xffffffff
MPHI_INTSTAT_RX0TEND_LSB 4
A2W_PLLD_PER_DIV_LSB 0
A2W_PLLC_CORE1_WIDTH 10
DMA1_DEBUG_DMA_STATE_LSB 16
ASB_V3D_S_CTRL_CLR_ACK_BITS 1:1
DMA15_CS_DREQ_STOPS_DMA_LSB 5
HD_CSC_CTL_COLORD_LSB 5
DMA15_TI_SRC_IGNORE_MSB 11
SD_RWC_WIDTH 32
USB_DIEPINT7_MASK 0xffffffff
A2W_PLLA_ANA2R_MASK 0x00ffffff
SCALER_DISPCTRL2_WIDTH 32
A2W_PLLD_DIG0_WIDTH 24
I2C_SPI_SLV_IMSC_OEIM_LSB 3
PM_AVS_STAT 0x7e100080:RW
DMA7_DEST_AD_D_ADDR_BITS 31:0
SH_HBLC_BLOCKCOUNT_SET 0x000001ff
GP_FSEL3_FSEL38_BITS 26:24
HDMI_DETECTED_VERTA0_MANUAL_VSP0_MSB 24
GP_FSEL0_FSEL00_MSB 2
FPGA_CTRL0_DISP_BUFFER_CLR 0xfffff7ff
DMA4_NEXTCONBK_ADDR_MSB 31
DMA6_DEST_AD_D_ADDR_SET 0xffffffff
MPHI_C0INDCF_LENERR_RESET 0x0
USB_GUSBCFG_ULPI_IF_PROT_DIS_MSB 25
CMUART 0x7C:RW
TB_BOOT_OPT_TB_PRESENT_MSB 31
AVE_OUT_CTRL_INVERT_HSYNC_LSB 14
GP_FSEL2_FSEL21_CLR 0xffffffc7
USB_DOEPDMA6_MASK 0xffffffff
PCM_MODE_A_CLKM_BITS 23:23
MS_STATUS_MASK 0xffffffff
TB_BOOT_SECURE_MODE_JTAG_SECURE_SET 0x00000003
PIXELVALVE1_C_MASK 0x00ffffff
SLIM_DCC2_STAT 0x7e21024c:RW
DMA2_DEST_AD_D_ADDR_MSB 31
A2W_PLLD_PERR_WIDTH 10
A2W_PLLA_PER_BYPEN_MSB 9
V3D_PCTR4_WIDTH 32
USB_GHWCFG2_FSPHY_INTERFACE_MSB 9
PM_PXBG_CTRL_SET 0x0000ffff
A2W_SMPS_CTLA0R 0x7e1028a0:RW
SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_RESET 0x0
TB_JTB_CONFIG_TDI_RISE_BITS 9:9
A2W_SMPS_CTLC0R_MASK 0x00ffffff
A2W_PLLC_ANA_SCTL_UPDATE_MSB 3
STC0_0 0x7e00300c:RW
A2W_PLLC_ANA_SSCLR_RESET 0000000000
DMA0_TI_BURST_LENGTH_MSB 15
SD_CS_SDTST_RESET 0x0
PCM_CS_A_RXTHR_CLR 0xfffffe7f
AVE_IN_LINE_NUM_INT_WIDTH 12
DPI_C_MASK 0x0000ffff
L1_D1_WR_THRUS_MASK 0000000000
DMA0_TI_SRC_INC_LSB 8
USB_DIEPINT0_SETUP_SET 0x00000008
TB_ADDR 0x7e20b000:RW
AVE_OUT_CTRL_INVERT_VSYNC_SET 0x00008000
MS_SEMA_27_MASK_MSB 0
A2W_PLLD_ANA_KAIPR_WIDTH 11
PCM_CS_A_EN_MSB 0
CM_PLLTCNT1_CNT_BITS 23:0
A2W_PLLH_ANA_SCTL_MASK 0x0000001f
SD_SB_ROWBITS_BITS 3:2
DMA14_DEST_AD_D_ADDR_MSB 31
SD_CS_CLKOFF_LSB 14
V3D_VPACNTL_MASK 0xffffffff
SCALER_DISPLACT1_WIDTH 32
TB_HOST 0x7e20b300:RW
PM_AVS_STAT_ALERT_V3D_G_BITS 3:3
A2W_PLLC_ANA_MULTI_MASK 0000000000
HDMI_DETECTED_VERTA1_MANUAL_VAL1_CLR 0xffffe000
USB_GHWCFG4_NUM_PERIO_EPS_RESET 0x0
EMMC_CONTROL0_HCTL_HS_EN_BITS 2:2
SYSAC_DMA_ARBITER_CONTROL_PER_RESET 0000000000
CAM0_CAMICC_RESET 0000000000
A2W_SMPS_CTLA1R 0x7e1028a4:RW
V3D_INTCTL_WIDTH 32
DMA1_TXFR_LEN_XLENGTH_SET 0x0000ffff
PCM_CS_A_RXD_CLR 0xffefffff
CM_PCMCTL_ENAB_CLR 0xffffffef
DMA11_TI_SRC_INC_CLR 0xfffffeff
DMA12_CS_WIDTH 32
STC0_x(x) MACRO
EMMC_FORCE_IRPT_SDOFF_ERR_SET 0x00800000
DMA0_CONBLK_AD_RESET 0000000000
HDMI_RAM_PACKET_4_5 0x7e9024a4:RW
APERF0_BW0_ATWAIT_WIDTH 32
CM_DPICTL_BUSY_MSB 7
GP_FSEL1_FSEL10_SET 0x00000007
GP_CLR2_WIDTH 6
CM_PLLA_LOADCCP2_BITS 2:2
I2C_SPI_SLV_MIS_BEMIS_MSB 2
EMMC_INTERRUPT_RETUNE_LSB 12
PM_AVS_RSTDR_PERI_A_LSB 0
USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_LSB 0
EMMC_INTERRUPT_INT_B_MSB 10
EMMC_BLKSIZECNT_BLKSIZE_LSB 0
USB_DIEPTXF1_WIDTH 32
SMI_DSR3_MASK 0xffffffff
A2W_SMPS_CTLA2R 0x7e1028a8:RW
CM_LOCK_FLOCKD_BITS 11:11
CCP2TX_TAC_DLAC_LSB 8
A2W_PLLH_ANA_KAIP_KI_LSB 4
A2W_XOSC_CTRL_SMPSOK_BITS 15:15
L1_IC1_CONTROL_START_FLUSH_SET 0x00000002
EMMC_IRPT_MASK_DMA_MSB 3
EMMC_CONTROL0_BOOT_EN_BITS 21:21
USB_GRSTCTL_INT_TKN_Q_FLSH_SET 0x00000008
SD_SECSRT1_EN_MSB 0
EMMC_HWCAP0_TCLKUNIT_SET 0x00000080
USB_PCGCR_PWR_CLMP_MSB 2
PM_PADS6_PD_CLR 0xfffffeff
DMA9_DEBUG_VERSION_MSB 27
AVE_OUT_STATUS_HBACK_PORCH_MSB 5
DMA4_CS_ERROR_SET 0x00000100
HD_HDM_CTL_MASK 0x000003f7
CM_TECCTL_FRAC_SET 0x00000200
CM_TIMERCTL_RESET 0000000000
GROPCTRS10 0x1A005100 + 0x0D4:RW
SD_SECEND1_ADDR_MS_MSB 31
CAM1_CAMDLT_RESET 0000000000
TH0T2PC 0x18011000 + 0x20:RW
PWM_CTL_PWEN1_MSB 0
L1_D0_RD_MISSES 0x7ee02148:RO
I2C_SPI_SLV_DR_RXFLEVEL_MSB 31
DMA13_TI_DEST_WIDTH_CLR 0xffffffdf
USB_DOEPCTL0_SET_EVEN_FR_CLR 0xefffffff
CM_CKSM_OSC_SET 0x000c0000
SCALER_DISPECTRL_POSTED_CTRL_BITS 21:16
DMA9_CS_ABORT_LSB 30
MPHI_INTSTAT_RX1TEND_MSB 12
SPI_CS_INTD_LSB 9
EMMC_SLOTISR_VER 0x7e3000fc:RW
SYSAC_ISP_PRIORITY_PRIORITY_SET 0x0000000f
A2W_XOSC_CPR_CPR1_SET 0x00000010
DSI0_CTRL_MASK 0x00000007
HDMI_AN_INFLUENCE_1_WIDTH 32
CM_DFTCTL_BUSYD_MSB 8
MS_SEMA_29_MASK_SET 0x00000001
SH_HSTS_BLOCK_IRPT_SET 0x00000200
A2W_PLLC_CORE0_MASK 0x000003ff
A2W_PLLA_ANA_SCTL_RESET_BITS 4:4
USB_DOEPTSIZ0_XFERSIZE_LSB 0
USB_DIEPCTL10_WIDTH 32
A2W_PLLB_ARM_BYPEN_LSB 9
A2W_PLLD_DSI1_MASK 0x000003ff
USB_GINTMSK_OEP_INT_MSB 19
TXP_CTRL_LINEAR_UTILE_SET 0x00000080
HDMI_RAM_PACKET_11_7_WIDTH 32
CM_TDCLKEN_IMAGETD_BITS 13:13
PM_PADS6_POWOK_MSB 5
DMA9_TI_DEST_IGNORE_SET 0x00000080
DMA10_CONBLK_AD 0x7e007a04:RW
USB_GI2CCTL_REG_ADDR_LSB 8
A2W_XOSC_CTRL_DDREN_BITS 4:4
MS_MBOX_5_RESET 0000000000
SCALER_OLEDCOEF2_MASK 0xffffffff
DMA11_CS_PANIC_PRIORITY_BITS 23:20
DSI_BASE 0x7e209000
HD_HDM_CTL_ENABLE_CLR 0xfffffffe
VPU_ARB_CTRL_L2_LIMIT_BITS 1:0
USB_DOEPTSIZ0_RX_DPID_LSB 29
DMA8_TI_SRC_WIDTH_MSB 9
DMA0_CONBLK_AD 0x7e007004:RW
USB_DIEPINT0_OUT_PKT_ERR_LSB 8
SH_HSTS_CRC7_ERROR_SET 0x00000010
USB_GHWCFG2_HSPHY_INTERFACE_CLR 0xffffff3f
DMA1_STRIDE_WIDTH 32
DMA4_TI_SRC_INC_CLR 0xfffffeff
PM_PROC_ISPOW_MSB 2
DMA5_CS_DREQ_MSB 3
V3D_DBSDR0 0x7ec00000 +0x0e10:RW
V3D_DBSDR1 0x7ec00000 +0x0e14:RW
V3D_DBSDR2 0x7ec00000 +0x0e18:RW
V3D_DBSDR3 0x7ec00000 +0x0e1c:RW
A2W_XOSC_BIAS_HIGHP_MSB 4
DMA7_NEXTCONBK_ADDR_SET 0xffffffe0
HD_MAI_CTL_MASK 0x0000ffff
USB_VBUS_DRV 0x7e980000 + 0x88:RW
USB_GHWCFG2_NUM_HOST_CHAN_BITS 14:17
SLIM_DCC0_STAT_WIDTH 32
DMA12_DEBUG_VERSION_MSB 27
UART_LCR_STB_CLR 0xfffffffb
DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
SD_SA_RFSH_T_BITS 31:16
SD_RAC_WIDTH 28
CAM0_CAMIBSA1_WIDTH 32
I2C_SPI_SLV_IMSC_WIDTH 4
AUX_SPI_CNTL0_HOLD0 0x00000000
DMA1_TI_INTEN_BITS 0:0
EMMC_HWCAP1_MULTIPLIER_MSB 23
USB_GINTMSK_ERLY_SUSP_SET 0x00000400
DMA5_DEST_AD_D_ADDR_SET 0xffffffff
USB_HCINT2_MASK 0xffffffff
CAM0_CAMDBG0_WIDTH 32
SMIDS_PACE 8
A2W_XOSC_CTRL_PLLCOK_SET 0x00001000
SMI_CS_RXR_MSB 27
I2C_SPI_SLV_IMSC_BEIM_MSB 2
DMA14_TI_SRC_DREQ_LSB 10
DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
DMA2_CS_PANIC_PRIORITY_LSB 20
SCALER_DISPSTAT_DMA_IRQ_MSB 31
AVE_IN_CURRENT_LINE_NUM_RESET 0000000000
GR_SYSTEM_DEBUG_BASE 0x1A005100
A2W_PLLA_DSI0 0x7e102300:RW
DMA13_TI_SRC_WIDTH_MSB 9
CSI2RDR3 CSI2_BASE_ADDRESS + 0x94:RW
SPI_CS_DMAEN_MSB 8
PIXELVALVE0_VERTA_EVEN_WIDTH 32
USB_DIEPTSIZ14_MASK 0xffffffff
PM_CAM1_CTRLEN_SET 0x00000001
EMMC_CMDTM_CMD_TYPE_MSB 23
A2W_PLLA_DIG0_WIDTH 24
APERF0_BW2_RTRANS_RESET 0000000000
SMI_DSW1_WWIDTH_BITS 31:30
TB_TASK 0x7e20b000:RW
CM_TD1DIV_DIV_SET 0x00ffffff
SMI_CS_TXD_MSB 28
DMA7_CS_DREQ_LSB 3
UART_LSR_PE_CLR 0xfffffffb
CM_HSMCTL_BUSYD_MSB 8
APERF1_BW2_CTRL_LATHALT_BITS 28:28
PCM_INTEN_A_TXW_LSB 0
USB_GHWCFG3_TRANS_COUNT_WIDTH_SET 0x0000000f
USB_DOEPCTL0_STALL_MSB 21
PIXELVALVE1_VERTA_EVEN 0x7e20701c:RW
SD_SECSRT1_ADDR_MS_SET 0xffffe000
I2C2_CLKT 0x7e80501c:RW
EMMC_INTERRUPT_WRITE_RDY_MSB 4
CM_TCNTCNT_MASK 0x00ffffff
USB_DCFG_NZ_STS_OUT_HSHK_RESET 0x0
A2W_PLLA_ANA_SSCLR_MASK 0x0001ffff
FPGA_CTRL0_SW_SPI_SDA_O_BITS 7:7
GP_FSEL6_FSEL63_LSB 9
HD_CSC_CTL_MODE_SET 0x0000000c
DMA11_BASE 0x7e007b00
AUX_SPI_CNTL0_HOLD7 0x00002000
SD_DQRCRC13_RISE_MSB 31
APERF1_BW0_CTRL_EN_LSB 30
SD_DQLCRC8_WIDTH 32
EMMC_FORCE_IRPT_DMA_SET 0x00000008
DMA15_CS_PRIORITY_LSB 16
CM_PULSECTL_FRAC_CLR 0xfffffdff
DPHY_CSR_CRC_CTRL_WIDTH 9
A2W_SMPS_L_SIV_VOLTS_MSB 4
DMA4_BASE 0x7e007400
CM_V3DCTL_BUSY_MSB 7
A2W_PLLC_ANA0R_RESET 0000000000
A2W_PLLA_CCP2_WIDTH 10
GP_FSEL2_FSEL20_MSB 2
SD_DQRCRC0_RISE_LSB 16
DMA0_TI_WAITS_MSB 25
TS_TSENSCTL_RSTDELAY_BITS 25:18
AVE_OUT_CR_COEFF_MASK 0x3fffffff
GRMSCT 0x1A005C00 + 0x10:RW
CM_DSI1ECTL_ENAB_BITS 4:4
MS_SEMA_2_MASK_MSB 0
AVE_OUT_STATUS_PXL_FORMAT_ERROR_LSB 0
SD_VIN_WRITE_RESET 0x0
I2C_SPI_SLV_FR_TXFE_CLR 0xffffffef
AVE_IN_CTRL_BYTE_ORDER_SET 0x00003800
SLIM_DMA_DC5_MASK 0xffffffff
APHY_CSR_BASE 0x7ee06000
DMA8_DEBUG_VERSION_BITS 27:25
MS_MBOX_3_MBOX_SET 0xffffffff
USB_DIEPCTL7_WIDTH 32
HDMI_CEC_CNTRL_4_MASK 0xffffffff
CM_SMICTL_FRAC_CLR 0xfffffdff
SLIM_DCC2_PROT_WIDTH 32
DMA0_TI_WAIT_RESP_MSB 3
VEC_CLMP0_END 0x7e806148:RW
USB_DIEPINT0_TX_FIFO_UNDRN_BITS 8:8
CM_GP2CTL_BUSYD_SET 0x00000100
INTERRUPT_HW_OFFSET (64)
DMA1_DEBUG_LITE_LSB 28
CM_INTEN_OCDONE_MSB 21
MPHI_AXIPRIV_TXPROT_SET 0x00000007
DMA11_DEST_AD_MASK 0xffffffff
AJB_BITS12 0x00000C
AJB_BITS16 0x000010
I2C_SPI_SLV_RSR_UE_CLR 0xfffffffd
PWM_CTL_SBIT3_BITS 19:19
HDMI_CEC_CNTRL_5_WIDTH 28
USB_HPRT_CONN_STS_CLR 0xfffffffe
DMA15_TXFR_LEN_XLENGTH_MSB 15
DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
USB_HFIR_IN_SET 0x0000ffff
CM_TDCLKEN_PLLABYP_LSB 0
USB_GINTMSK_MODE_MIS_RESET 0x0
SD_DQLCRC13_FALL_CLR 0xffff0000
AVE_IN_CTRL_FRAME_MODE_BITS 10:9
CAM0_CAMIHWIN_MASK 0xffffffff
MPHI_C0INDCF_ORUN_BITS 29:29
AUX_SPI_STAT_TXFULL 0x00000400
HDMI_RAM_GCP_2 0x7e902408:RW
AVE_OUT_CTRL_ENABLE_CLR 0x7fffffff
DSI_INT_ENABLE 0x7e209000 + 0x28:RW
CM_SLIMCTL 0x7e1010a8:RW
SMI_DSR0_RHOLD_SET 0x003f0000
HDMI_TX_PHY_TX_PHY_STATUS_MASK 0xffffffff
I2C_SPI_SLV_ICR_RXIC_SET 0x00000001
CM_AVEODIV_RESET 0000000000
CM_PLLH_LOADRCAL_LSB 2
L2_CONT_OFF_l2_standby_LSB 10
PM_AVS_EVENT_ALERT_PERI_A_SET 0x00000001
USB_DOEPDMAB14_MASK 0xffffffff
AJB_BITS20 0x000014
AJB_BITS24 0x000018
AJB_BITS28 0x00001C
TB_TASK_TEXT_FLAG_CLR 0xfffeffff
SD_VIN_ID_BITS 15:0
DMA9_DEBUG_OUTSTANDING_WRITES_LSB 4
PM_PADS5_MASK 0x0000007f
USB_GOTGCTL_SES_REQ_MSB 1
USB_GRXSTSP_DEV_BCNT_CLR 0xffff800f
APERF0_BW2_CTRL_LATHALT_CLR 0xefffffff
DMA6_TI_SRC_INC_MSB 8
PCM_INTEN_A_TXERR_SET 0x00000004
USB_GOTGINT_SES_REQ_SUC_STS_CHG_LSB 8
SMI_DA_ADDR_MSB 5
DMA9_TI_SRC_WIDTH_LSB 9
PCM_TXC_A_CH2POS_CLR 0xffffc00f
L1_IC0_PRIORITY_IC0_APRIORITY0_SET 0x0000000f
SMI_DA_WRITE_LSB 8
CAM1_CAMDBSA1_WIDTH 32
VCE_REASON_SINGLE 0x13
DMA5_TI_SRC_IGNORE_BITS 11:11
GP_EDS1_EDSn32_LSB 0
A2W_HDMI_CTL_RCAL_RSTB_SET 0x00010000
CMI_CAM1_RX0SRC_LSB 2
EMMC_FORCE_IRPT_CBAD_ERR_BITS 19:19
DMA14_CONBLK_AD_SCB_ADDR_LSB 5
DMA13_TI_SRC_INC_BITS 8:8
TE_1C_MASK 0xffffffff
L1_IC1_RAS_PUSHES 0x7ee020d0:RO
PM_IMAGE_WIDTH 23
AJB_BITS32 0x000020
DSI1_RXPKT_FIFO_WIDTH 32
TB_TASK_TXTCLR_WIDTH 32
GRTCFG3 0x1A005260 + 0x04:RW
AVE_IN_LINE_LENGTH_MASK 0x00000fff
CCP2TX_TTC_WIDTH 32
MS_SEMA_8_MASK_LSB 0
I2C2_FIFO 0x7e805010:RW
RNG_CTRL 0x7e104000:RW
USB_DIEPINT0_OUT_TKN_EP_DIS_LSB 4
PCM_GRAY_FLUSHED_LSB 10
USB_DOEPINT0_TX_FIFO_UNDRN_MSB 8
SLIM_DCC1_PA0 0x7e210220:RW
SLIM_DCC1_PA1 0x7e210224:RW
CM_SLIMCTL_BUSY_MSB 7
EMMC_HWCAP0_XMEDBUS_SET 0x00040000
USB_GRSTCTL_DMA_REQ_MSB 30
UART_LSR_THRE_MSB 5
CM_SYSCTL 0x7e101010:RW
TB_PRINTER_DATA 0x7e20b404:RW
USB_DIEPCTL0_STALL_SET 0x00200000
PCMCS_RXSYNC (1 << 14)
USB_GUSBCFG_FS_INTF_RESET 0x0
USB_DIEPCTL0_DPID_RESET 0x0
ASB_V3D_M_CTRL_WCOUNT_CLR 0xff003fff
DMA8_TI_BURST_LENGTH_LSB 12
PM_SMPS_RSTDR_MSB 1
OTP_CODE_SIGNING_KEY_ROW ((((((((8 +4)+4)+1)+1)+1)+4)+4)+1)
I2C_SPI_SLV_RSR_TXDMABREQ_LSB 3
DMA11_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
SMI_DSW2_WWIDTH_MSB 31
CM_PLLTCTL_WIDTH 8
ST_C2_RESET 0000000000
DSI0_PHYC_WIDTH 18
DMA15_DEST_AD_D_ADDR_BITS 31:0
SMI_FD_FCNT_MSB 5
CM_EVENT_BADPASS_SET 0x00040000
VEC_MASK0_MASK 0xffffffff
HD_MAI_FMT_MASK 0xffffffff
DMA1_DEBUG_DMA_ID_BITS 15:8
DMA10_CS_PRIORITY_MSB 19
DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
EMMC_HWCAP0_HS_SET 0x00200000
MS_MBOX_3_WIDTH 32
A2W_PLLB_ANA_STAT_MASK 0x00000fff
GRTCOFF0 0x1A005300 + 0x04:RW
GRTCOFF1 0x1A005300 + 0x84:RW
APERF0_BW0_RTRANS_MASK 0xffffffff
A2W_PLLH_ANA_KAIP_KP_BITS 3:0
SD_DQLCRC5_RISE_LSB 16
MS_SEMA_1_MASK_BITS 0:0
PM_HDMI_LDOCTRL_SET 0x0007fffc
DMA2_CS_ERROR_LSB 8
GP_FSEL1_FSEL15_MSB 17
PM_SMPS_UPEN_BITS 2:2
GP_LEN0_LENn0_SET 0xffffffff
AVE_IN_CURRENT_ADDRESS_CUR_ADDR_SET 0xffffffff
SLIM_MC_IN_CON_MASK 0x00000f1d
HDMI_CEC_CNTRL_3_MASK 0xffffffff
USB_DIEPCTL0_SET_EVEN_FR_BITS 28:28
USB_GRSTCTL_TXF_FLSH_MSB 5
PCM_DREQ_A_TX_MSB 14
HDMI_CPU_MASK_SET_MASK 0xffffffff
A2W_PLLH_ANA_KAIP_KP_SET 0x0000000f
A2W_HDMI_CTL3_RESET 0x00000040
L1_IC1_RD_MISSES 0x7ee020c4:RO
A2W_PLLC_ANA_SSCLR 0x7e102a30:RW
HDMI_CEC_RX_DATA_4_RESET 0000000000
EMMC_INTERRUPT_DCRC_ERR_CLR 0xffdfffff
HDMI_DETECTED_VERTB1_MANUAL_VBP1_MSB 8
EMMC_CONTROL0_HCTL_CRDDET_S_BITS 7:7
MPHI_HSINDFS_WIDTH 32
USB_DIEPDMA6_MASK 0xffffffff
A2W_PLLB_CTRL_PDIV_MSB 14
AVE_OUT_CTRL_ERROR_IRQ_EN_BITS 0:0
HDMI_RAM_PACKET_13_2_WIDTH 32
CAM1_CAMIBEA1 0x7e801308:RW
PWMDAT1 0x7e20c000 + 0x14:RW
DMA8_TI_SRC_WIDTH_BITS 9:9
PM_PADS4_HYST_BITS 3:3
DMA1_CONBLK_AD_RESET 0000000000
USB_HCSPLT4_MASK 0xffffffff
DMA9_DEBUG_READ_ERROR_SET 0x00000004
GP_PUDCLK2_MASK 0x0000003f
A2W_PLLA_ANA_STATR_MASK 0x00000fff
MPHI_RXAXICFG_INTHRESH_MSB 16
USB_GINTMSK_NP_TXF_EMP_LSB 5
OTP_JTAG_DISABLE_BIT 16
IC1_FORCE1_CLR_RESET 0000000000
USB_DCTL_CGNP_IN_NAK_RESET 0x0
USB_GAHBCFG_DMA_EN_CLR 0xffffffdf
A2W_PLLB_ANA_SCTL_RESET_LSB 4
CM_INTEN_GAINB_MSB 1
USB_GRSTCTL_FRM_CNTR_RST_MSB 2
SD_VIN_SPLIT_LSB 17
AVE_IN_STATUS_BUF1_COMPL_SET 0x00000004
USB_DOEPTSIZ0_PKT_CNT_SET 0x1ff80000
DMA3_DEBUG_READ_ERROR_LSB 2
AUX_SPI_CNTL1_CSPLUS1 0x00000100
SD_SA_PGEHLD_IDL_CLR 0xffff7fff
AUX_SPI_CNTL1_CSPLUS3 0x00000300
AUX_SPI_CNTL1_CSPLUS4 0x00000400
AUX_SPI_CNTL1_CSPLUS5 0x00000500
AUX_SPI_CNTL1_CSPLUS6 0x00000600
AUX_SPI_CNTL1_CSPLUS7 0x00000700
DMA10_TI_WAIT_RESP_MSB 3
ASB_H264_M_CTRL_FULL_MSB 3
APERF0_BW1_CTRL_ID_EN_CLR 0xdfffffff
USB_GINTMSK_P_TXF_EMP_MSB 26
VCODEC_VERSION 821
DMA7_CS_DISDEBUG_MSB 29
PIXELVALVE1_INTEN_WIDTH 10
A2W_HDMI_CTL_RCAL_MANREN_BITS 12:12
DMA6_CS_PANIC_PRIORITY_LSB 20
EMMC_IRPT_EN_SDOFF_ERR_MSB 23
IC0_MASK2_MASK 0x77777777
USB_HCCHAR1_MASK 0xffffffff
CM_DSI0HSCK_SELPLLD_LSB 0
CM_TIMERCTL_BUSY_BITS 7:7
DMA9_CS_DREQ_CLR 0xfffffff7
PERFMON_BASE_ADDRESS 0x7e20d000
GP_FSEL2_FSEL25_SET 0x00038000
HD_MAI_CTL_WHOLSMP_LSB 12
GP_FEN2_FENn64_MSB 5
EMMC_SLOTISR_VER_SLOT_STATUS_BITS 7:0
A2W_SMPS_B_STAT_POK_SET 0x00001000
USB_DIEPCTL0_SNAK_RESET 0x0
DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
DMA10_CS_PANIC_PRIORITY_CLR 0xff0fffff
DC0START 0x7ee02104:RW
PM_PADS2_POWOK_BITS 5:5
CM_LOCK_LOCKA_LSB 0
SD_DQRCRC7_RISE_LSB 16
CAM0_CAMIBWP_RESET 0000000000
MAX_TIMER_NUM 4
SH_RSP1_CID_CSD_CLR 0x00000000
PCM_RXC_A_CH1WEX_CLR 0x7fffffff
EMMC_BLKSIZECNT_BLKCNT_SET 0xffff0000
MS_SEMA_9_MASK_MSB 0
HDMI_RAM_PACKET_11_1_RESET 0000000000
MPHI_C1INDDB_MENDINT_SET 0x40000000
PM_IMAGE_ENAB_CLR 0xffffefff
SD_CS_RDH_IDLE_SET 0x00010000
DMA5_STRIDE 0x7e007518:RO
USB_DOEPCTL0_STALL_SET 0x00200000
SYSAC_DMA_DREQ_CONTROL_WIDTH 4
EMMC_INTERRUPT_CTO_ERR_CLR 0xfffeffff
AVE_IN_OUTSTANDING_BUFF1_MASK 0x000000ff
SMI_DSW0_WDREQ_CLR 0xffffff7f
A2W_PLLH_CTRL_PRSTN_SET 0x00020000
HDMI_FIFO_CTL_USE_EMPTY_LSB 13
PWM_CTL_MODE2_CLR 0xfffffdff
SH_EDM_READ_THRESHOLD_LSB 14
PM_PADS0_POWOK_LSB 5
HDMI_CP_TST 0x7e902058:RW
CM_LOCK_FLOCKB_BITS 9:9
USB_GINTMSK_I2C_INT_BITS 9:9
IC0_MASK1_WIDTH 31
HDMI_VERTA0_MANUAL_VFP0_SET 0x000fe000
USB_HCCHAR0_WIDTH 32
SPI_DLEN_LEN_LSB 0
DMA11_TI_SRC_WIDTH_BITS 9:9
DMA2_TI_TDMODE_CLR 0xfffffffd
USB_GRXSTSP_HST_BCNT_SET 0x00007ff0
PM_STATUS_MASK 0x00ffffff
USB_HCINT0_BBL_ERR_LSB 8
AVE_IN_CTRL_ENABLE_MSB 31
CM_TDCLKEN_PLLCDIV2_LSB 6
PCM_MODE_A_FRXP_CLR 0xfdffffff
A2W_PLLA_ANA_SSCL_WIDTH 22
A2W_PLLA_ANA_VCO_RESET 0000000000
CM_GP0CTL_ENAB_MSB 4
DSI0_DISP0_CTR 0x7e209018:RW
PWM_RNG4_MASK 0000000000
SMI_DSW0_WSTROBE_CLR 0xffffff80
DMA10_CS_DREQ_SET 0x00000008
JMWDATA 0x7e005000 + 0x34:RW
USB_DAINT_OUT_EP_INT_BITS 31:16
UART_MSR_DDCD_BITS 3:3
MPHI_TXAXICFG_TXPPRIO_CLR 0xffffff0f
DMA3_TI_DEST_WIDTH_BITS 5:5
DMA15_TI_SRC_IGNORE_SET 0x00000800
ARM_MC_MAIL_CLEAR 0x00000008
I2C2_A 0x7e80500c:RW
I2C2_C 0x7e805000:RW
CCP2REA0 CCP2_BASE_ADDRESS + 0x110:RW
CCP2REA1 CCP2_BASE_ADDRESS + 0x210:RW
I2CS_TXE (1 << 6)
A2W_PLLB_FRAC_MASK 0x000fffff
A2W_PLLB_ANA_SCTL_SEL_CLR 0xfffffff8
ACISASR 0x1C004800 + 0x14:RW
TXP_CTRL_FORMAT_CLR 0xfffff0ff
HDCP_KEY_CTL_DISHDCP_CLR 0xfffffffb
DMA_CS_ABORT (1<<30)
SMI_DSR3_RSETUP_LSB 24
CM_TD0CTL_STEP_MSB 12
L1_IC0_CONTROL_BP_DISABLE_BITS 3:3
SD_APB_ID 0x5344434f
MPHI_C1INDDA_START_CLR 0x00000000
TB_JTB_CONFIG_TDI_RISE_SET 0x00000200
MPHI_CTRL_EIGHTBIT_SET 0x00001000
DMA8_TI_PERMAP_SET 0x001f0000
EMMC_CONTROL1_CLK_GENSEL_CLR 0xffffffdf
GP_FSEL1_FSEL11_LSB 3
USB_DOEPCTL3_MASK 0xffffffff
A2W_PLLA_DSI0_CHENB_BITS 8:8
USB_DIEPINT0_IN_TKN_EP_MIS_CLR 0xffffffdf
FPGA_CTRL0_DIS_CTL0_MSB 0
CM_EVENT_GAINH_CLR 0xffffffef
CAM0_CAMANA_WIDTH 32
HDMI_BKSV0 0x7e902010:RW
USB_DCTL_PWRON_PRG_DONE_LSB 11
DMA15_TI_DEST_WIDTH_BITS 5:5
DMA2_STRIDE_D_STRIDE_MSB 31
L1_L1_SANDBOX_START6_CTRL_CLR 0xfffffffe
DMA9_DEST_AD_D_ADDR_LSB 0
PM_IMAGE_POWOK_BITS 1:1
DMA_INT_STATUS_INT13_LSB 13
DMA15_TI_SRC_DREQ_LSB 10
SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_CLR 0xfffffff3
USB_DIEPTSIZ0_MC_LSB 29
EMMC_IRPT_EN_DMA_ERR_BITS 28:28
A2W_PLLD_PER_CHENB_LSB 8
A2W_PLLH_RCAL_CHENB_LSB 8
MS_SEMA_28_RESET 0000000000
SLIM_DCC0_CON_RESET 0000000000
SYSAC_HVSM_PRIORITY_N_PRIORITY_SET 0x0000000f
CM_GP2CTL_SRC_SET 0x0000000f
EMMC_BUS_CTRL_BUS_WIDTH_LSB 8
A2W_PLLA_MULTI 0x7e102f00:RW
AVE_IN_BLOCK_ID 0x7e910060:RW
SPI_CS_INTR_CLR 0xfffffbff
DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
SD_DMRCRC1_LOW_CLR 0xffff0000
SD_SECSRT1_EN_SET 0x00000001
USB_HPRT_TST_CTL_MSB 16
EMMC_HWCAP1_DRV18_TYPED_MSB 6
CM_PLLA_LOADCCP2_MSB 2
AVE_IN_BUF0_ADDRESS 0x7e910008:RW
AUX_SPI_CNTL0_CSFROMFF 0x00008000
ASB_H264_M_CTRL_WCOUNT_CLR 0xff003fff
DMA12_SOURCE_AD_S_ADDR_CLR 0x00000000
AUX_MU_LCR_REG (0x7E215000 +0x04C)
V3D_DBSDR0_WIDTH 32
SDIDL 0x7ee00018:RW
SD_SA_CLKSTOP_MSB 7
CM_PLLD_HOLDDSI1_BITS 3:3
A2W_HDMI_CTL_RCAL_MANREN_MSB 12
DMA2_DEBUG_READ_ERROR_BITS 2:2
EMMC_DBG_SEL_MASK 0x00000001
CM_SDCCTL_BUSY_SET 0x00000080
SMI_DSR1_RESET 0x0101000c
DMA13_DEBUG_LITE_BITS 28:28
USB_DOEPDMA3_MASK 0xffffffff
PM_AVS_STAT_ALERT_H264_I_MSB 2
SD_SC_T_RFC_RESET 0x1e
DMA9_CS_PANIC_PRIORITY_BITS 23:20
USB_DTHRCTL_TX_THR_LEN_CLR 0xfffff803
A2W_PLLD_DSI1_BYPEN_BITS 9:9
DMA2_TI_WAIT_RESP_CLR 0xfffffff7
MPHI_CTRL_DIRECT_MSB 4
TE_0TIMER_WIDTH 32
USB_DIEPTSIZ0_XFERSIZE_BITS 18:0
USB_HCDMA1_MASK 0xffffffff
PM_RSTS_HADDRQ_LSB 0
USB_GHWCFG4_NUM_IN_EPS_SET 0x0c000000
A2W_PLLA_DSI0_BYPEN_CLR 0xfffffdff
DMA11_CS_RESET_CLR 0x7fffffff
MPHI_INTSTAT_IMFOFLW_SET 0x20000000
EMMC_SLOTISR_VER_SLOT_STATUS_LSB 0
TB_BOOT_OPT_TCL_SIM_SET 0x00000008
SMI_DCS_EANBLE_CLR 0xfffffffe
SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_LSB 6
AVE_OUT_CTRL_PRIV_ACCESS_MSB 8
DMA6_TXFR_LEN_XLENGTH_CLR 0xffff0000
MPHI_AXIPRIV_HSPECEN_CLR 0xfffffeff
CM_PLLD_HOLDCORE_MSB 5
A2W_PLLC_ANA_SSCSR 0x7e102930:RW
I2C_SPI_SLV_RSR_RXDMAPREQ_LSB 4
MS_ICSET_1_ICSET_1_MSB 0
AVE_IN_CTRL_HIGH_PRIORITY_SET 0x00f00000
L1_L1_SANDBOX_START3_START_ADDR_CLR 0xc000001f
DMA13_CS_ABORT_CLR 0xbfffffff
SD_SA_CLKSTOP_BITS 7:7
DMA9_TI_DEST_DREQ_LSB 6
HDMI_SCHEDULER_CONTROL_MODE_ACTIVE_BITS 1:1
A2W_PLLA_CTRL_PRSTN_MSB 17
TB_PRINTER_CTRL 0x7e20b400:RW
USB_GRSTCTL_H_SFT_RST_MSB 1
PM_GNRIC_RESET 0000000000
A2W_PLLC_PER_BYPEN_BITS 9:9
DMA5_DEST_AD_MASK 0xffffffff
AVE_IN_CTRL_BUF0_IRQ_EN_SET 0x00000002
GRPCZSM 0x1A005600 + 0x58:RW
USB_PCGCR_PWR_CLMP_SET 0x00000004
USB_DOEPINT0_IN_TKN_EP_MIS_LSB 5
DMA12_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
A2W_PLLH_CTRL_PDIV_MSB 14
CM_TDCLKEN_PLLDDIV2_MSB 7
CM_PULSECTL_SRC_CLR 0xfffffffc
USB_DCTL_WIDTH 16
DPHY_CSR_DQ_SPR1_RO 0x7ee07070:RW
SPI_CS_CLEAR_BITS 5:4
USB_DSTS_ERRTIC_ERR_RESET 0x0
DMA10_TI_PERMAP_LSB 16
A2W_HDMI_CTL1_MASK 0x00ffffff
CM_TD1CTL_SRC_LSB 0
CM_GP0CTL_KILL_CLR 0xffffffdf
V3D_DBQGHC 0x7ec00000 +0x0e34:RW
A2W_SMPS_L_SCV_VOLTS_MSB 4
DSI1_HS_DLT3 0x7e70005c:RW
DSI1_HS_DLT4 0x7e700060:RW
V3D_DBQGHG 0x7ec00000 +0x0e38:RW
V3D_DBQGHH 0x7ec00000 +0x0e3c:RW
SCALER_DISPALPHA2 0x7e400070:RW
A2W_PLLH_AUX_WIDTH 10
CM_INTEN_A2WDONE_LSB 20
CM_VPUCTL_BUSY_LSB 7
ASB_CPR_CTRL_WCOUNT_BITS 23:14
AVE_OUT_CTRL_INVERT_HSYNC_MSB 14
USB_HCINT0_AHB_ERR_MSB 2
GP_FEN0 0x7e200058:RW
GP_FEN1 0x7e20005c:RW
GP_FEN2 0x7e200060:RW
AVE_OUT_CR_COEFF_BLUE_COEFF_SET 0x000003ff
EMMC_CONTROL0_WAKE_ONREM_EN_SET 0x04000000
HDMI_DMA (17*(1<<16))
PM_CAM0_RESET 0000000000
SD_SC_T_WTR_LSB 4
ASB_CPR_CTRL 0x7e00a004:RW
DMA3_TXFR_LEN_YLENGTH_BITS 29:16
USB_GPVNDCTL_DIS_ULPI_DRVR_CLR 0x7fffffff
CM_GP0CTL_SRC_BITS 3:0
USB_GPVNDCTL_CTRL_ULPI_MSB 13
SD_CARCRC_RISE_RESET 0x0
USB_DTHRCTL_RX_THR_LEN_CLR 0xf801ffff
AVE_OUT_CTRL_REFRESH_RATE_LSB 2
CM_PERIACTL_GATE_CLR 0xffffffbf
USB_DIEPINT13_MASK 0xffffffff
AUX_SPI_CNTL0_CSA_N 0x00000000
EMMC_BUS_CTRL_BUS_WIDTH_CLR 0xffff80ff
DMA15_DEBUG_FIFO_ERROR_LSB 1
DMA9_DEBUG_DMA_ID_CLR 0xffff00ff
SD_SC_MASK 0x7ff00f77
CM_VECCTL_FRAC_CLR 0xfffffdff
MS_SEMA_7_RESET 0000000000
ST_C0_RESET 0000000000
SD_DQRCRC1_FALL_CLR 0xffff0000
USB_GPVNDCTL_STS_BSY_BITS 26:26
HDMI_SCHEDULER_CONTROL_ALWS_VERT_KEEPOUT_CLR 0xfffffff7
A2W_PLLD_PER_DIV_MSB 7
DMA12_DEBUG_LITE_CLR 0xefffffff
SD_CS_ASHDN_T_LSB 19
A2W_PLLH_AUX_BYPEN_SET 0x00000200
DMA10_TI_SRC_DREQ_MSB 10
DSI0_RX1_PKTH_WIDTH 32
SMI_DSR1_MODE68_CLR 0xff7fffff
PWM_CTL_RPTL2_CLR 0xfffffbff
PIXELVALVE_0_BASE_ADDRESS 0x7e206000
USB_GHWCFG4_EN_VBUSVALID_FILTER_LSB 21
CM_DSI1PDIV_DIV_SET 0x00001000
RNG_APB_ID 0x20726e67
DMA14_TI_WAITS_LSB 21
MS_SEMA_13_MASK 0x00000001
MPHI_AXIPRIV_MASK 0x00000177
USB_HCCHAR0_EP_DIR_CLR 0xffff7fff
GP_REN0_RENn0_MSB 31
CAM1_CAMIDCA_WIDTH 32
L1_IC0_PRIORITY 0x7ee02004:RW
CPG_Debug1_WIDTH 32
DMA5_CS_ABORT_MSB 30
AVE_OUT_STATUS_HSYNC_MSB 6
FPGA_MB_XSYS_BUILD_NUM 0x7e20b700:RO
USB_DIEPCTL0_USB_ACT_EP_SET 0x00008000
I2C_SPI_SLV_MIS_TXMIS_MSB 1
MPHI_HSINDCF_MTERM_BITS 28:28
CM_CAM0CTL_FRAC_MSB 9
L2_WR_BACKS_WIDTH 32
AVE_IN_CTRL_BUF_SER_IRQ_EN_SET 0x00000008
CM_PULSECTL_BUSYD_BITS 8:8
EMMC_INTERRUPT_INT_A_CLR 0xfffffdff
CM_EVENT_GAINC_LSB 2
A2W_HDMI_CTL1R_WIDTH 24
GP_FSEL1 0x7e200004:RW
GP_FSEL2 0x7e200008:RW
GP_FSEL3 0x7e20000c:RW
GP_FSEL4 0x7e200010:RW
GP_FSEL5 0x7e200014:RW
GP_FSEL6 0x7e200018:RW
HD_CSC_CTL_MODE_MSB 3
PWM_DMAC 0x7e20c008:RW
HDMI_AN_INFLUENCE_1_MASK 0xffffffff
DMA12_TI_SRC_DREQ_BITS 10:10
CM_GNRICDIV_DIV_LSB 0
OTP_JTAG_DEBUG_KEY_ROW_REDUNDANT 68
SMI_DSR3_FSETUP_CLR 0xffbfffff
DMA7_DEBUG_DMA_STATE_SET 0x01ff0000
SD_VIN_ID_CLR 0xffff0000
HDMI_DETECTED_HORZA_MANUAL_HPOL_LSB 13
CM_OTPCTL_BUSY_LSB 7
DMA14_CS_PANIC_PRIORITY_CLR 0xff0fffff
EMMC_CONTROL2_ACBAD_ERR_LSB 4
GP_FEN2_RESET 0000000000
MS_SEMA_22_MASK 0x00000001
USB_GUSBCFG_TERM_SEL_DL_PULSE_LSB 22
DSI1_TXPKT2_H_WIDTH 32
USB_DTKNQR1_WIDTH 32
VEC_CLMP0_START_WIDTH 32
SMI_CS_PVMODE_SET 0x00001000
SD_SB_ROWBITS_MSB 3
PIXELVALVE_HSYNC_x(x) MACRO
USB_DOEPINT0_IN_TKN_TXFEMP_BITS 4:4
DMA11_CS_PRIORITY_MSB 19
DMA12_TI_SRC_IGNORE_SET 0x00000800
GP_FSEL5_FSEL50_MSB 2
SCALER_DISPLIST2_MASK 0xffffffff
AVE_IN_STATUS_OVERRUN_CNT_LSB 24
PM_PADS2_HYST_MSB 3
SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_RESET 0x0
PCM_MODE_A_FSI_SET 0x00100000
CM_TIMERCTL_BUSY_LSB 7
DMA11_CS_PAUSED_SET 0x00000010
I2C1_DIV_MASK 0x0000ffff
DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
CM_PLLD_DIGRST_SET 0x00000200
CM_TD0CTL_SRC_CLR 0xfffffff0
DMA2_TXFR_LEN_XLENGTH_MSB 15
CM_TSENSCTL_BUSYD_MSB 8
DMA11_TI_DEST_IGNORE_LSB 7
CM_DSI1PCTL_BUSYD_SET 0x00000100
HDMI_RAM_PACKET_1_0 0x7e902424:RW
HDMI_RAM_PACKET_1_1 0x7e902428:RW
DMA2_TI_SRC_IGNORE_LSB 11
SH_HBCT_WIDTH 32
HDMI_RAM_PACKET_1_4 0x7e902434:RW
HDMI_RAM_PACKET_1_5 0x7e902438:RW
HDMI_RAM_PACKET_1_6 0x7e90243c:RW
HDMI_RAM_PACKET_1_7 0x7e902440:RW
HDMI_RAM_PACKET_1_8 0x7e902444:RW
AVE_IN_CURRENT_LINE_BUF0 0x7e91001c:RW
UART_MSR_CTS_BITS 4:4
USB_GINTMSK_P_TXF_EMP_RESET 0x0
DMA11_CS_DREQ_BITS 3:3
SLIM_DCC0_PA1_RESET 0000000000
AVE_IN_APB_ID 0x61766530
DMA1_CS 0x7e007100:RW
CM_CCP2CTL_MASK 0x00000397
I2C_SPI_SLV_DEBUG2_DATA_LSB 0
GRTMPM1_BASE 0x1A005F00
CM_CAM0DIV_DIV_SET 0x0000fff0
L1_L1_SANDBOX_START5_START_ADDR_MSB 29
CAM1_CAMANA_RESET 0x00000777
SLIM_DCC9_PA0_RESET 0000000000
DMA2_CONBLK_AD_RESET 0000000000
L1_IC0_PRIORITY_IC0_APRIORITY1_LSB 4
DMA_DEBUG_STATE (1<<16)
L2_WR_BACKS 0x7ee01110:RO
SD_DQLCRC1_MASK 0xffffffff
SD_CS_DEL_KEEP_BITS 18:18
CM_PWMCTL_KILL_SET 0x00000020
SCALER_DISPSLAVE2_WIDTH 32
DMA2_DEBUG_DMA_ID_SET 0x0000ff00
MS_SEMA_26_WIDTH 1
CM_DSI1ECTL_BUSY_CLR 0xffffff7f
A2W_XOSC_CTRL_USBEN_SET 0x00000004
SD_SB_EIGHTBANK_RESET 0x0
AVE_IN_CTRL_BUF1_IRQ_EN_MSB 2
I2C_SPI_SLV_DEBUG2_DATA_BITS 23:0
APERF1_BW1_RTWAIT_WIDTH 32
DMA15_CONBLK_AD_SCB_ADDR_LSB 5
GP_FSEL6_FSEL60_SET 0x00000007
GRMSVI 0x1A005C00 + 0x08:RW
AVE_OUT_CTRL_SOFT_RESET_BITS 30:30
A2W_PLLH_FRAC 0x7e102260:RW
IC0_FORCE0_SET_WIDTH 32
USB_DOEPINT0_XFER_COMPL_CLR 0xfffffffe
HDMI_RAM_PACKET_9_7_WIDTH 32
A2W_PLLH_CTRL_PWRDN_SET 0x00010000
PCM_CS_A_TXERR_CLR 0xffff7fff
DMA12_CS 0x7e007c00:RW
USB_DIEPTSIZ7_WIDTH 32
HDMI_SCHEDULER_CONTROL_USE_PREDICTS_BITS 2:2
CAM1_CAMCLK 0x7e801010:RW
L1_D_PRIORITY_c0_per_priority_CLR 0xfffff0ff
SCALER_DISPECTRL_CB_BUSY_SET 0xfffffc00
L1_IC1_BP_HITS 0x7ee020c8:RO
USB_HCINT0_STALL_CLR 0xfffffff7
CAM1_CAMCLT 0x7e801014:RW
EMMC_IRPT_EN_DCRC_ERR_BITS 21:21
A2W_PLLD_FRAC_FRAC_BITS 19:0
DMA13_DEBUG_READ_ERROR_SET 0x00000004
AVE_OUT_STATUS_COEFF_ERROR_MSB 2
HDMI_RAM_PACKET_11_5_MASK 0xffffffff
TXP_CTRL_FORMAT_SET 0x00000f00
CM_DSI0PCTL_WIDTH 10
APERF1_BW2_WTRANS_MASK 0xffffffff
AVE_OUT_CTRL_COEFF_IRQ_EN_CLR 0xfffffffd
USB_DIEPINT0_TX_FIFO_UNDRN_SET 0x00000100
DMA5_CS_ABORT_LSB 30
GP_AREN0 0x7e20007c:RW
GP_AREN1 0x7e200080:RW
GP_AREN2 0x7e200084:RW
PWM_CTL_MODE1_CLR 0xfffffffd
CM_HSMCTL_RESET 0000000000
L1_IC1_FLUSH_E 0x7ee0208c:RW
DMA2_CONBLK_AD 0x7e007204:RW
EMMC_STATUS_CARD_DETECT_CLR 0xfffbffff
A2W_PLLA_ANA_SCTL_RESET_SET 0x00000010
SD_DQRCRC7_RISE_RESET 0x0
DSI0_CMD_PKTC_MASK 0xffffffff
USB_DOEPCTL0_SET_D0_PID_CLR 0xefffffff
A2W_SMPS_LDO1R_RESET 0000000000
L1_IC1_FLUSH_S 0x7ee02088:RW
CM_INTEN_LOSSC_SET 0x00000080
SLIM_DCC9_PROT 0x7e210330:RW
MPHI_C0INDCF_LENGTH_BITS 19:0
SD_DQRCRC13_FALL_MSB 15
DMA6_DEBUG_READ_ERROR_BITS 2:2
AJB_D1_RISE 0x000200
A2W_PLLD_ANA_STAT_MASK 0x00000fff
DMA0_TI_DEST_DREQ_CLR 0xffffffbf
SD_TMC_IPRD_LSB 8
EMMC_CONTROL2_EN_AINT_LSB 30
SD_DQLCRC7_RISE_BITS 31:16
USB_DTXFSTS14_MASK 0xffffffff
A2W_PLLA_FRAC_MASK 0x000fffff
DMA15_CS_INT_LSB 2
DMA3_TI_SRC_IGNORE_LSB 11
CM_AVEOCTL_BUSY_CLR 0xffffff7f
OTP_CTRL_HI_REG_MASK 0x0000ffff
VPU_ARB_CTRL_UC_WIDTH 16
PWM_CTL_MSEN1_BITS 7:7
OTP_PRIVATE_KEY_ROW_REDUNDANT ((((((((((((((((((8 +4)+4)+1)+1)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+4)
GP_PUD_RESET 0000000000
HDMI_RAM_PACKET_6_2_MASK 0xffffffff
CM_CAM0CTL_ENAB_LSB 4
USB_DOEPTSIZ12_MASK 0xffffffff
HDMI_RAM_PACKET_3_6_WIDTH 32
I2C_SPI_SLV_RIS_TXRIS_CLR 0xfffffffd
CM_ISPCTL_ENAB_MSB 4
I2C2_DIV_WIDTH 16
MS_SEMA_24_MASK_MSB 0
HD_VID_CTL_FULRGB_RESET 0x0
SYSAC_DBG_PRIORITY_WIDTH 4
PM_AVS_RSTDR_SYSTEM_A_SET 0x00000002
SD_CS_STALLING_MSB 24
PCM_MODE_A_PDME_CLR 0xfbffffff
MS_SEMA_30_MASK_LSB 0
HDMI_SCHEDULER_CONTROL_POSTLN_AVOID_LSB 8
USB_GINTMSK_OEP_INT_RESET 0x0
PM_AVS_STAT_ALERT_H264_I_BITS 2:2
EMMC_EXRDFIFO_EN_ENABLE_MSB 0
MPHI_INTSTAT 0x7e006050:RW
USB_HCINT0_XFER_COMPL_LSB 0
USB_GRXFSIZ_GRXF_DEP_CLR 0xffff0000
DMA11_TI_PERMAP_SET 0x001f0000
HDMI_RAM_PACKET_3_8_RESET 0000000000
VPU_ARB_CTRL_L2_THRESHOLD_SET 0x00000030
DMA_INT_STATUS_INT10_SET 0x00000400
I2C_SPI_SLV_FR_RXFF_BITS 3:3
USB_DIEPINT0_BACK2BACK_SETUP_MSB 6
SD_DQRCRC14_RISE_CLR 0x0000ffff
CM_EMMCCTL_KILL_LSB 5
USB_DFIFO6_MASK 0xffffffff
DMA14_SOURCE_AD_WIDTH 32
I2C_SPI_SLV_DMACR_TXDMAE_MSB 1
DMA1_STRIDE_S_STRIDE_CLR 0xffff0000
HD_HDM_CTL_RFSTBY_SET 0x000000c0
MS_SEMA_14_MASK_LSB 0
SH_HSTS_FIFO_ERROR_SET 0x00000008
I2C_SPI_SLV_DR_RXFF_LSB 19
ARM_SD_OWN0 0x00000003
ARM_SD_OWN1 0x0000000C
ARM_SD_OWN2 0x00000030
ARM_SD_OWN3 0x000000C0
ARM_SD_OWN4 0x00000300
ARM_SD_OWN5 0x00000C00
ARM_SD_OWN6 0x00003000
ARM_SD_OWN7 0x0000C000
SD_CS_EN_RESET 0x0
I2C_SPI_SLV_CR_BRK_BITS 7:7
CM_TIMERCTL_KILL_MSB 5
EMMC_CONTROL0_HCTL_LED_BITS 0:0
MPHI_CTRL_SOFT_RST_DNE_CLR 0xfffdffff
GROPCTR_FBC_CZ_FETCHES 0x30
GP_FSEL2_FSEL26_LSB 18
USB_GOTGCTL_HST_SET_HNP_EN_RESET 0x0
USB_GUSBCFG_DDR_SEL_SET 0x00000080
SLIM_DCC4_CON_MASK 0xffff0070
PCM_CH1WID_LSB 16
DMA9_TI_DEST_WIDTH_SET 0x00000020
EMMC_HWMAXAMP0_AMP_18V_MSB 23
PM_GRAFX_ENAB_CLR 0xffffefff
CCP2TX_TC_MEN_SET 0x00000002
USB_DOEPDMAB7_WIDTH 32
MS_SEMA_3_MASK_CLR 0xfffffffe
USB_DIEPCTL3_MASK 0xffffffff
DMA14_DEBUG_FIFO_ERROR_SET 0x00000002
VEC_CPS1213_CPS1415 0x7e80612c:RW
EMMC_CONTROL1_CLK_INTLEN_BITS 0:0
FPGA_MB_XSLC3_BUILD_NUM_MASK 0xffffffff
SCALER_OLEDOFFS_WIDTH 32
SH_HCFG_WIDE_EXT_BUS_SET 0x00000004
CM_TDCLKEN_PLLBBYP_MSB 1
A2W_PLLC_DIG3_RESET 0x00000004
USB_GI2CCTL_DEV_ADR_RESET 0x0
CM_GP0CTL_MASH_SET 0x00000600
CCP2TX_TS_TQI_LSB 19
L2_BASE 0x7ee01000
EMMC_CONTROL0_GAP_STOP_LSB 16
USB_GAHBCFG_DMA_EN_BITS 5:5
DPI_APB_ID 0x44504920
A2W_PLLA_CTRL_PWRDN_MSB 16
DMA5_CS_RESET_CLR 0x7fffffff
DMA7_SOURCE_AD_S_ADDR_LSB 0
MS_SEMA_19_MASK_BITS 0:0
ARM_IE_VP1HALT 0x00000020
SMI_CS_ENABLE_LSB 0
USB_DOEPCTL0_DIS_CLR 0xbfffffff
PWM_CTL_USEF3_SET 0x00200000
HDMI_CEC_RX_DATA_2_MASK 0xffffffff
CM_PCMCTL_BUSY_BITS 7:7
USB_DIEPDMA11 0x7e980a74:RW
CM_PLLA_LOADPER_BITS 6:6
PWM_CTL_PWEN1_SET 0x00000001
DMA12_DEBUG_DMA_ID_SET 0x0000ff00
SCALER_DISPECTRL_CB_BUSY_CLR 0x000003ff
APERF1_BW2_CTRL_RESET_BITS 31:31
V3D_CT0CS_MASK 0xffffffff
IC_0 0x7e002000:RW
IC_1 0xffffffff:RW
V3D_PCTRS5_MASK 0x0000001f
CM_CAM1CTL_BUSY_MSB 7
HDMI_DETECTED_HORZB_MANUAL_HSP_CLR 0xfff003ff
HDMI_ASYNC_RM_OFFSET (HDMI_BASE_ADDRESS + 0x300) + 20:RW
HDMI_CP_CONFIG_MASK 0x7fffffff
MPHI_RXAXICFG_RXPPRIO_BITS 7:4
A2W_HDMI_CTL_MULTI 0x7e102f80:RW
A2W_PLLC_ANA3R_MASK 0x00ffffff
HDMI_TX_PHY_TX_PHY_SPARE 0x7e9022e0:RW
EMMC_INTERRUPT_DMA_ERR_BITS 28:28
AJB_BITS34 0x000022
ARM_T_PREDIV 0x7E00B000 +0x41c:RW
MPHI_C0INDS_DISCARD_BITS 31:31
APERF0_BW0_ATWAIT_RESET 0000000000
EMMC_IRPT_EN_ACMD_ERR_LSB 24
DMA1_TI_SRC_INC_CLR 0xfffffeff
USB_DIEPTSIZ0_RX_DPID_BITS 30:29
DSI1_INT_EN 0x7e700034:RW
MPHI_INTCTRL_MASK 0x00111111
USB_GNPTXFSIZ_NP_TXF_DEP_BITS 31:16
DMA12_TI_DEST_WIDTH_SET 0x00000020
AUX_MU_MSR_CTS 0x10
EMMC_EXRDFIFO_CFG_MASK 0x00000007
TIMER_CTRL_ONESHOT (1 << 0)
L1_IC0_CONTROL_START_FLUSH_CLR 0xfffffffd
DMA6_CS_WIDTH 32
HD_VID_CTL_ERROR_RESET 0x0
SD_DQLCRC5_FALL_LSB 0
EMMC_CONTROL0_WAKE_ONINS_EN_LSB 25
SD_DQRCRC0_RISE_BITS 31:16
DMA12_DEST_AD_WIDTH 32
DMA10_DEBUG_WIDTH 29
SD_CMD_RESET 0000000000
MPHI_CTRL_INVERT_BITS 8:8
DMA8_DEBUG_FIFO_ERROR_SET 0x00000002
HDMI_HDMI_13_AUDIO_CFG_1 HDMI_BASE_ADDRESS + 336:RW
DMA_INT_STATUS_INT0_LSB 0
DMA11_SOURCE_AD 0x7e007b0c:RO
MPHI_INTSTAT_OMFUFLW_CLR 0xefffffff
HDMI_HORZB_MANUAL_HFP_BITS 9:9
A2W_PLLC_CORE0R_RESET 0x00000100
TB_JTB_CONFIG_OUT_MS_MSB 6
NU_HOSTIO_OF_RESET 0000000000
HDMI_RAM_PACKET_8_6_MASK 0xffffffff
SMI_DCS_START_CLR 0xfffffffd
PM_AVS_RSTDR 0x7e10007c:RW
DSI0_PHYC_dsi_esc_lpdt_SET 0x0003f000
SD_DQLCRC10_RISE_BITS 31:16
HDMI_FIFO_CTL_FIFO_RESET_SET 0x00000020
HDMI_FIFO_CTL_CAPTURE_POINTER_LSB 2
USB_DOEPTSIZ0_SUP_CNT_RESET 0x0
DMA1_SOURCE_AD 0x7e00710c:RO
PIXELVALVE0_VERTB_EVEN_MASK 0xffffffff
CM_PERIIDIV 0x7e101024:RO
EMMC_INTERRUPT_DTO_ERR_SET 0x00100000
CM_ISPCTL_SRC_BITS 3:0
USB_DIEPTSIZ0_RX_DPID_RESET 0x0
SDDATA SDCARD_BASE + 0x40:RW
CM_DSI1ECTL_FRAC_BITS 9:9
DMA8_TI_WAITS_LSB 21
SH_HSTS_RESET 0000000000
DMA1_CS_RESET_BITS 31:31
CAM0_CAMIDI0 0x7e800108:RW
PIXELVALVE2_HORZA 0x7e80700c:RW
PIXELVALVE2_HORZB 0x7e807010:RW
DMA5_CS_ERROR_BITS 8:8
SD_SECEND3_ADDR_LS_LSB 0
USB_GINTMSK 0x7e980018:RW
SCALER_ID 0x7e400000 + 0x08:RW
AVE_OUT_STATUS_VBACK_PORCH_BITS 8:8
DMA11_TI_SRC_DREQ_MSB 10
DMA_INT_STATUS_INT15_SET 0x00008000
EMMC_CONTROL0_GAP_RESTART_MSB 17
CAM0_CAMIDI1 0x7e80030c:RW
DMA6_DEBUG_DMA_ID_CLR 0xffff00ff
APERF1_BW2_RTWAIT_RESET 0000000000
CAM1_CAMCTL 0x7e801000:RW
CM_AVEOCTL_BUSY_MSB 7
USB_GOTGCTL_DBNC_TIME_BITS 17:17
MPHI_MINFS_OFLOW_RESET 0x0
DMA10_TI_SRC_INC_MSB 8
CMI_CAMTEST_SRC_MSB 3
CCP2TX_TS_TFF_SET 0x00000020
DMA8_CS_PANIC_PRIORITY_CLR 0xff0fffff
DMA0_CS_ABORT_BITS 30:30
FPGA_CTRL0_SW_SPI_SDA_O_LSB 7
DMA12_CS_INT_LSB 2
SD_SA_POWSAVE_MSB 0
DMA6_DEBUG_DMA_ID_MSB 15
MPHI_OUTDS_WIDTH 31
DMA6_CS_ACTIVE_LSB 0
FPGA_DCM_WR_DATA_DATA_SET 0x0000ffff
GP_AFEN1_WIDTH 32
CAM1_CAMIDI1_RESET 0000000000
GP_SET1_RESET 0000000000
SD_SECEND1_ADDR_LS_CLR 0xffffe000
USB_DOEPINT0_OUT_PKT_ERR_BITS 8:8
TB_BOOT_OPT_NO_PRINT_SET 0x00000040
CM_SLIMCTL_MASH_BITS 10:9
SD_SF_WIDTH 30
USB_GOTGCTL_HST_NEG_SCS_BITS 8:8
A2W_HDMI_CTL_RCAL_SELAVG_LSB 0
MULTICORE_SYNC_SEMA_STATUS MULTICORE_SYNC_BASE_ADDRESS + 0x80:RW
PIXELVALVE0_STAT_MASK 0x000003ff
HDMI_DETECTED_HORZA_MASK 0x00007fff
I2C2_DLEN 0x7e805008:RW
L1_L1_SANDBOX_PERI_BR_MASK 0x00001f1f
A2W_PLLH_AUX_CHENB_BITS 8:8
EMMC_BUS_CTRL_CLK_PINS_LSB 0
SD_DQRCRC7_FALL_LSB 0
V3D_PCTR1_MASK 0xffffffff
USB_GUSBCFG_ULPI_IF_PROT_DIS_RESET 0x0
SYSTEM_TIMER_BASE1 0xffffffff:RW
FPGA_MB_SDC_CLK_FREQ 0x7e20b728:RO
SD_CS_SDUP_BITS 15:15
SD_SECSRT1_EN_BITS 0:0
AVE_IN_MAX_TRANSFER_MAX_TRANSFER_BITS 31:0
DMA15_DEBUG_DMA_STATE_SET 0x01ff0000
A2W_PLLB_ANA_KAIPR 0x7e102bf0:RW
MPHI_MINFS_LEVEL_MSB 9
SD_MR_DONE_MSB 31
CPG_Param1_WIDTH 32
SLIM_DMA_MC_CON 0x7e210080:RW
USB_DOEPDMAB4_MASK 0xffffffff
DMA12_CS_PRIORITY_MSB 19
CCP2TX_TD_TCS_MSB 4
DMA3_CS_DISDEBUG_BITS 29:29
MPHI_C0INDS_HANDLE_MSB 28
AM_DB_PERPRI 0x1800d018:RW
DMA15_TI_INTEN_CLR 0xfffffffe
DMA14_TI_DEST_INC_LSB 4
ASB_V3D_M_CTRL_CLR_REQ_MSB 0
INTERRUPT_HDMI0 ((64) + 40 )
INTERRUPT_HDMI1 ((64) + 41 )
HDMI_RAM_PACKET_7_4_WIDTH 32
USB_DIEPTSIZ8_WIDTH 32
CCP2TX_TS_TUE_SET 0x00000008
EMMC_STATUS_WRITE_TRANSFER_CLR 0xfffffeff
DMA14_CS_ERROR_SET 0x00000100
USB_GUSBCFG_ULPI_EXT_VBUS_DRV_SET 0x00100000
DMA5_CS_DREQ_BITS 3:3
A2W_PLLH_CTRL_NDIV_BITS 7:0
CM_GP1CTL_MASH_SET 0x00000600
PM_DFT_ALLOWAUDIOCKSTOP_LSB 0
CM_DSI1PCTL_SRC_LSB 0
AVE_OUT_OFFSET_BLUE_OFFSET_CLR 0xffffff00
CM_GP0DIV_DIV_LSB 0
SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_SET 0x0000ff00
SLIM_DCC9_STAT_MASK 0xc0ff00c7
TS_TSENSCTL_RSTB_LSB 1
PM_RSTC_SRCFG_SET 0x00000300
EMMC_SLOTISR_VER_SDVERSION_MSB 23
A2W_PLLB_SP1_MASK 0x000003ff
GP_FSEL6_FSEL65_MSB 17
DMA5_DEBUG_DMA_STATE_LSB 16
TB_BOOT_STATUS_WIDTH 1
PCM_MODE_A_CLK_DIS_LSB 28
FPGA_MB_XH264_BUILD_NUM_MASK 0xffffffff
SMI_DC_REQW_CLR 0xffffffc0
DMA2_DEBUG_FIFO_ERROR_LSB 1
HDMI_TST_AN0 0x7e902028:RW
HDMI_TST_AN1 0x7e90202c:RW
DMA3_CONBLK_AD_RESET 0000000000
EMMC_IRPT_MASK_ACMD_ERR_SET 0x01000000
SD_MR_RDATA_MSB 23
HD_MAI_CTL_CHALIGN_MSB 13
CM_GP1DIV_RESET 0000000000
ASB_H264_S_CTRL_CLR_REQ_SET 0x00000001
EMMC_INTERRUPT_MASK 0xffffffff
HDMI_RAM_PACKET_9_1_RESET 0000000000
A2W_PLLD_DSI0R_RESET 0x00000100
USB_GI2CCTL_REG_ADDR_RESET 0x0
TB_BOOT_STATUS_MASK 0x00000001
DMA6_TXFR_LEN_YLENGTH_SET 0x3fff0000
HDMI_READ_POINTERS_DRFT_WR_ADDR_MSB 15
I2C_SPI_SLV_DR_OE_LSB 8
VEC_CPS01_CPS23_MASK 0xffffffff
SYSAC_DMA_DREQ_CONTROL 0x7e009064:RW
HD_MAI_CTL_PAREN_BITS 8:8
SD_PHYC_CRC_CLR_CLR 0xfeffffff
DSI1_DISP1_CTRL_MASK 0xffffffff
USB_GOTGINT_HST_NEG_SUC_STS_CHG_LSB 9
USB_DOEPCTL14_MASK 0xffffffff
DMA2_TI_SRC_IGNORE_MSB 11
SH_HSTS_DATA_FLAG_BITS 0:0
SMI_DA_ADDR_CLR 0xffffffc0
VPU_ARB_CTRL_L2_ALGORITHM_BITS 7:6
A2W_PLLH_PIXR_RESET 0x00000100
DSI0_PHYC_txulpshs_1_sync_MSB 6
CCP2TX_TC_SWR_CLR 0x7fffffff
DMA4_DEBUG_DMA_ID_BITS 15:8
CM_INTEN_LOSSH_MSB 9
DMA4_TI_BURST_LENGTH_MSB 15
HDMI_RAM_PACKET_5_3_RESET 0000000000
AVE_OUT_Y_COEFF_BLUE_COEFF_MSB 9
IDCMDID 0x10002024:RW
A2W_PLLC_PER_BYPEN_LSB 9
EMMC_CONTROL1_CLK_FREQ8_SET 0x0000ff00
A2W_PLLC_DIG1_WIDTH 24
GRTLBIAS7 0x1A0052E0 + 0x1C:RW
USB_GHWCFG4_EN_IDDIG_FILTER_CLR 0xffefffff
AVE_IN_CTRL_OVERRUN_IRQ_EN_LSB 0
MPHI_RXAXICFG_RXPPRIO_LSB 4
SYSAC_H264_PRIORITY_WIDTH 4
EMMC_IRPT_EN_DEND_ERR_SET 0x00400000
STCHI 0x7e003008:RO
SLIM_DCC8_PA0_RESET 0000000000
I2C_SPI_SLV_MIS_RXMIS_LSB 0
HDMI_RAM_PACKET_1_5_RESET 0000000000
CAM1_CAMIVWIN 0x7e801128:RW
SD_RWC_MAXCNT_BITS 28:24
DMA3_CS_DISDEBUG_LSB 29
A2W_PLLD_ANA_SCTL_RESET_LSB 4
MS_SEMA_29_MASK 0x00000001
USB_HCFG_LS_PHY_CLK_SEL_SET 0x00000003
HDMI_AN_INFLUENCE_2_RESET 0000000000
CM_PLLC_HOLDCORE2_CLR 0xffffffdf
HDMI_PERT_INSERT_ERR_SEP_WIDTH 32
MPHI_C0INDDB_LENGTH_LSB 0
SMI_DSW0_MASK 0xffffffff
GP_FSEL2_FSEL21_BITS 5:3
CCP2TX_TS_TFF_MSB 5
HDMI_HORZA_MANUAL_VPOL_MSB 14
CM_CAM0CTL_SRC_LSB 0
DMA15_DEBUG_READ_ERROR_SET 0x00000004
HDMI_TX_PHY_TX_PHY_CTL_0 0x7e9022c4:RW
HDMI_TX_PHY_TX_PHY_CTL_1 0x7e9022c8:RW
HDMI_TX_PHY_TX_PHY_CTL_2 0x7e9022cc:RW
SYSAC_V3D_LIMITER_HOLDOFF_SET 0x00000001
CAM1_CAMDCS_RESET 0000000000
SD_DQLCRC15_RISE_LSB 16
CM_PWMCTL_SRC_SET 0x0000000f
USB_GINTMSK_NP_TXF_EMP_RESET 0x0
VEC_CPS45_CPS67 0x7e806124:RW
GP_FSEL1_FSEL13_BITS 11:9
SYSAC_UC_ARBITER_CONTROL_DELAY_RESET 0x0
APERF0_BW0_CTRL_ID_EN_BITS 29:29
PWM_BASE 0x7e20c000
SD_IDL_RESET 0000000000
SMI_DSW1_WFORMAT_LSB 23
ARM_1_MAIL1_WRT (0x7E00B000 +0x900)+0xA0:RW
GRVVSTRD 0x1A005D00 + 0x00:RW
SCALER_DISPECTRL_CR_NE_CTRL_CLR 0x3fffffff
USB_DCTL_TST_CTL_MSB 6
DMA11_CS_ABORT_MSB 30
SYSAC_BASE 0x7e009000
APERF0_BW0_CTRL_RESET_RESET 0x0
DMA9_DEBUG_WIDTH 29
SD_DQLCRC6_WIDTH 32
GP_FSEL0_FSEL05_BITS 17:15
GP_CLR2_CLRn64_LSB 0
APERF1_GEN_CTRL_WIDTH 2
MS_ICCLR_0_MASK 0x00000001
I2C_SPI_SLV_VCSTAT_RESET 0000000000
CM_TD1CTL_BUSYD_CLR 0xfffffeff
SD_DQRCRC1_RISE_RESET 0x0
EMMC_SLOTISR_VER_VENDOR_MSB 31
ASB_CPR_CTRL_EMPTY_CLR 0xfffffffb
ASB_V3D_S_CTRL_MASK 0x00ffffff
EMMC_IRPT_MASK_CMD_DONE_MSB 0
CM_PLLA_HOLDCORE_CLR 0xffffffdf
L1_IC1_CONTROL_ENABLE_STATS_CLR 0xfffffffb
I2C0_DLEN_MASK 0x0000ffff
GROPCTR_FBC_CZ_PBE_HITS 0x27
DMA10_TI_DEST_IGNORE_MSB 7
OTP_CTRL_LO_REG_MASK 0xffffffff
UART_LCR_OUT1_LSB 2
GPREN1 0x7e200000 + 0x50:RW
GP_HEN0_HENn0_MSB 31
DMA1_TI_INTEN_SET 0x00000001
PM_DSI1_LDOLPEN_MSB 1
PM_HDMI_CTRLEN_LSB 0
A2W_PLLC_CTRL 0x7e102120:RW
DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
DMA1_TI_SRC_WIDTH_MSB 9
AVE_OUT_Y_COEFF_RED_COEFF_CLR 0xc00fffff
EMMC_TUNE_STEPS_STD_WIDTH 6
PM_GRAFX_MRDONE_SET 0x00000010
HDMI_DETECTED_HORZA_MANUAL_VPOL_BITS 14:14
SD_RWC_RSTMAX_MSB 31
PCM_GRAY_RXLEVEL_LSB 4
CM_CKSM_AUTO_MSB 20
PM_PADS6_DRIVE_LSB 0
DMA4_STRIDE_S_STRIDE_BITS 15:0
USB_HCINT3_MASK 0xffffffff
CM_GP1CTL_MASH_BITS 10:9
CM_INTEN_FGAIND_CLR 0xffffdfff
EMMC_CONTROL1_CLK_INTLEN_SET 0x00000001
DMA1_TI 0x7e007108:RO
TB_BOOT_SECURE_MODE_MASK 0x00000003
GP_FSEL6_FSEL61_LSB 3
SMI_DSR0_WIDTH 32
SD_CS_DPD_LSB 2
CM_GNRICCTL_FLIP_BITS 11:11
DSI_HSTX_TO_CNT 0x7e209000 + 0x30:RW
USB_DOEPTSIZ0_MC_BITS 30:29
GP_FEN0_FENn0_SET 0xffffffff
PIXELVALVE2_INTEN 0x7e807024:RW
MPHI_C0INDCF_ORUN_CLR 0xdfffffff
SCALER_DISPSTAT_DMA_ERR_BIT2_BITS 31:7
FPGA_CTRL0_DIS_CTL2_CLR 0xfffffffb
DMA10_TI_WAITS_MSB 25
CM_CCP2CTL 0x7e101050:RW
HD_MAI_THR_PANICLOW_SET 0x003f0000
SD_PHYC_MDLL_TMODE_BITS 16:16
CMI_CAM1_RX3SRC_LSB 8
EMMC_CONTROL0_PWCTL_SDVOLTS_MSB 11
DMA2_DEBUG_READ_ERROR_MSB 2
DMA13_CS_DISDEBUG_BITS 29:29
USB_DCTL_IGN_FRM_NUM_MSB 15
CCP2TX_TSC 0x7e001010:RW
CM_V3DCTL_KILL_BITS 5:5
USB_DIEPINT0_TIMEOUT_SET 0x00000008
DMA0_TXFR_LEN_YLENGTH_LSB 16
MPHI_AXIPRIV_TXPROT_LSB 0
EMMC_IRPT_MASK_CCRC_ERR_BITS 17:17
USB_DOEPCTL0_TYPE_RESET 0x0
MPHI_INTSTAT_RX0TEND_MSB 4
JP_APB_ID 0x4a504547
MPHI_C1INDDB_LENGTH_MSB 19
CMI_CAMTEST_ENAB_MSB 4
I2CA_0 0x7e205000 + 0x0C:RW
CM_INTEN_BADPASS_BITS 18:18
I2CA_2 0x7e805000 + 0x0C:RW
SH_CMD_READ_CMD_SET 0x00000040
AVE_OUT_STATUS_VSYNC_MSB 9
OTP_HDCP_AES_KEY_SIZE_IN_ROWS 4
PM_PADS5_POWOK_CLR 0xffffffdf
SMI_DSR1_RWIDTH_LSB 30
CAM1_CAMIHSTA_WIDTH 32
CM_DSI1ECTL_BUSYD_LSB 8
MPHI_C0INDDB_MORUN_BITS 31:31
PM_AVS_EVENT_ALERT_V3D_G_SET 0x00000008
PM_PROC_ENAB_MSB 12
INTERRUPT_3D ((64) + 10 )
SD_DQRCRC5 0x7ee00120:RO
VCE_PROGRAM_MEM_SIZE 0x4000
SD_DQRCRC0_MASK 0xffffffff
TXP_CTRL_TFORMAT_LSB 5
CM_INTEN_LOSSD_LSB 8
CM_OTPCTL_FRAC_MSB 9
STCLO 0x7e003004:RO
PCM_DREQ_A_TX_PANIC_MSB 30
EMMC_INTERRUPT_TUNE_ERR_MSB 26
CCP2TX_TS_TXB_SET 0x00000001
CM_H264CTL_BUSYD_LSB 8
EMMC_FORCE_IRPT_ATA_ERR_MSB 29
USB_HPRT_EN_CHNG_LSB 3
CM_INTEN_LOSSC_BITS 7:7
L2_TAG_STALLS_MASK 0xffffffff
V3D_DBQITE_WIDTH 32
PIXELVALVE0_C_MASK 0x00ffffff
HDMI_VERTA1_MANUAL_VFP1_LSB 13
SH_HCFG_BLOCK_IRPT_EN_SET 0x00000100
SCALER_DISPCTRL_IRQ_EN_BITS 6:0
I2CA_x(x) MACRO
SD_SA_PGEHLD_IDL_BITS 15:15
MPHI_INTSTAT_RX1DISC_LSB 24
HD_MAI_DAT 0x7e808020:RW
A2W_PLLA_ANA_VCO_RANGE_LSB 0
SD_VIN_MULT_SET 0x01000000
DMA8_TI_DEST_IGNORE_CLR 0xffffff7f
HD_MAI_CTL_ENABLE_BITS 3:3
DMA2_CS_ABORT_CLR 0xbfffffff
MS_SEMA_2_MASK 0x00000001
DMA13_CS_PAUSED_CLR 0xffffffef
PM_PXBG_MASK 0x0000ffff
PM_GRAFX_MRDONE_BITS 4:4
A2W_SMPS_L_SCAR 0x7e102cd0:RW
EMMC_IRPT_EN_OEM_ERR_CLR 0x3fffffff
AVE_IN_FRAME_NUM_FRAME_NUM_MSB 11
HDMI_FIFO_CTL_RECENTER_LSB 6
DMA7_DEBUG_OUTSTANDING_WRITES_BITS 7:4
SMI_DSR2_MODE68_MSB 23
A2W_PLLD_ANA3R_RESET 0x00000180
PM_GRAFX_MEMREP_SET 0x00000008
VEC_CPS01_CPS23_WIDTH 32
SH_ARG_ARGUMENT_LSB 0
DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
DMA0_TI_DEST_WIDTH_LSB 5
AVE_IN_CHAR_CTRL 0x7e91003c:RW
SMI_DSR0_RPACE_MSB 14
SD_DQRCRC8 0x7ee0012c:RO
USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_RESET 0x0
L2_SD_STALLS_WIDTH 32
SH_HCFG_BUSY_IRPT_EN_BITS 10:10
DMA6_NEXTCONBK_ADDR_CLR 0x0000001f
DMA_ENABLE_EN13_CLR 0xffffdfff
USB_DTXFSTS0_SPC_AVAIL_BITS 31:16
EMMC_HWCAP0_TCLKUNIT_MSB 7
DMA_INT_STATUS_INT11_LSB 11
L1_L1_SANDBOX_START2_START_ADDR_SET 0x3fffffe0
CM_TDCLKEN_HDMIBYP_BITS 8:8
MPHI_CTRL_DIRECT_CLR 0xffffffef
CM_PLLD_HOLDPER_MSB 7
A2W_PLLH_MULTI 0x7e102f60:RW
DMA4_DEST_AD_D_ADDR_CLR 0x00000000
USB_GUSBCFG_ULPI_FS_LS_MSB 17
PWM_CTL_USEF2_BITS 13:13
PM_PADS3_HYST_SET 0x00000008
SMI_FIFO_ADDRESS(device,addr) MACRO
V3D_INTDIS_WIDTH 32
CSI2_REA_x(x) MACRO
MS_SEMA_15_MASK_CLR 0xfffffffe
CM_LOCK_LOCKC_MSB 2
A2W_PLLA_PER_WIDTH 10
SD_DQRCRC15_FALL_RESET 0x0
DMA10_CS_DISDEBUG_LSB 29
SD_DQLCRC3_RISE_SET 0xffff0000
USB_DTHRCTL_NON_ISO_THR_EN_CLR 0xfffffffe
V3D_CT0PC_WIDTH 32
DMA1_TI_DEST_IGNORE_SET 0x00000080
HDMI_CPU_SET_RESET 0000000000
DMA8_DEBUG_DMA_ID_CLR 0xffff00ff
IC1_SRC1 0x7e00280c:RO
SD_PHYC_CRC_EN_MSB 20
EMMC_FORCE_IRPT_DEND_ERR_CLR 0xffbfffff
PIXELVALVE1_VERTB_EVEN_MASK 0xffffffff
SD_SECSRT0_EN_MSB 0
CM_TCNTCTL_MASK 0x000030cf
MPHI_MINFS_OFLOW_LSB 31
ASB_ISP_S_CTRL_CLR_ACK_SET 0x00000002
EMMC_INTERRUPT_CARD_OUT_SET 0x00000080
HDMI_RAM_PACKET_RSVD_0 (HDMI_BASE_ADDRESS + 0x400) + 504:RW
HDMI_RAM_PACKET_RSVD_1 (HDMI_BASE_ADDRESS + 0x400) + 508:RW
CM_H264CTL_ENAB_CLR 0xffffffef
IVADDR_0 0x7e002030:RW
IVADDR_1 0xffffffff:RW
SMI_CS_START_BITS 3:3
AVE_OUT_CTRL_INTERLEAVE_BITS 12:12
SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_LSB 0
APERF1_BW2_CTRL_EN_SET 0x40000000
USB_DPTXFSIZ12_MASK 0xffffffff
USB_GHWCFG2_FSPHY_INTERFACE_RESET 0x0
DMA13_TI_DEST_IGNORE_SET 0x00000080
USB_DOEPCTL0_NAK_STS_SET 0x00020000
DMA12_TI_SRC_DREQ_MSB 10
IS_ALIAS_NOT_L1(p) MACRO
USB_DIEPINT6 0x7e9809c8:RW
SMIDCS_WRITE 3
EMMC_SPI_INT_SPT_SELECT_MSB 7
VPU_ARB_CTRL_UC_CHANNEL_INIBIT_LSB 8
HDMI_RAM_PACKET_5_1_WIDTH 32
HDMI_DETECTED_VERTA1_MANUAL_VFP1_SET 0x000fe000
SCALER_DISPECTRL_CR_NE_CTRL_MSB 31
DMA12_CS_ERROR_LSB 8
APERF1_BW2_WTRANS 0x7ee080d0:RO
CM_EMMCCTL_SRC_SET 0x0000000f
PWM_CTL_USEF4_LSB 29
EMMC_HWCAP0_BUS64_SET 0x10000000
APERF0_BW1_CTRL_LATHALT_BITS 28:28
GP_FSEL2_FSEL24_LSB 12
SMI_DSW2_WSWAP_MSB 22
HD_CSC_CTL_COLORD_MSB 7
DMA11_TI_SRC_WIDTH_MSB 9
USB_HPTXSTS_HPTXQSPCAVAIL_CLR 0xff00ffff
CM_V3DDIV_DIV_BITS 15:4
L1_D_PRIORITY_c1_l2_priority_BITS 19:16
HDMI_RAM_PACKET_1_3_WIDTH 32
VCE_CONTROL_CLEAR_RUN 0
CM_EMMCCTL_FRAC_SET 0x00000200
APERF1_BW0_RTWAIT_RESET 0000000000
PCM_INTEN_A_RXERR_MSB 3
SCALER_DISPSTAT_RD_IRQ_SET 0xffffffc0
GP_FSEL1_FSEL13_MSB 11
USB_GNPTXSTS_TX_Q_TOP_LSB 24
ARM_T_IRQCNTL 0x7E00B000 +0x40C:RW
I2C_SPI_SLV_RIS_BERIS_CLR 0xfffffffb
APERF0_BW0_CTRL_ID_EN_MSB 29
DMA6_TI_WAIT_RESP_LSB 3
CM_PLLA_LOADDSI0_MSB 0
SMI_CS_DONE_LSB 1
SD_SE_T_XSR_MSB 5
GP_FSEL3_FSEL34_CLR 0xffff8fff
MPHI_C0INDS_WORDS_RESET 0x0
GROPCTR_PBE_DEPTH_TEST_FAIL 0x1F
SD_TMC_IPSEL_LSB 4
I2C_SPI_SLV_CR_INV_TXF_CLR 0xffffdfff
CAM0_CAMPRI_MASK 0xffffffff
CMI_CAMTEST_SRC_BITS 3:0
DSI1_TST_SEL 0x7e700078:RW
L1_L1_SANDBOX_START0_START_ADDR_CLR 0xc000001f
USB_GRSTCTL_AHB_IDLE_BITS 31:31
DMA9_TI_INTEN_CLR 0xfffffffe
CM_PLLA_LOADDSI0_BITS 0:0
CM_PCMDIV_DIV_SET 0x00ffffff
DPHY_CSR_CRC_DATA_MASK 0x0fffffff
GP_SET2_RESET 0000000000
PM_DSI0_LDOHPEN_MSB 2
HDMI_RAM_PACKET_11_8_RESET 0000000000
DMA5_CS_ACTIVE_MSB 0
CM_PERIICTL_GATE_LSB 6
CM_TSENSCTL_SRC_SET 0x00000003
CM_CKSM_STATE_SET 0x000000ff
USB_DOEPINT0_IN_EP_NAK_EFF_CLR 0xffffffbf
DMA3_CS_DREQ_SET 0x00000008
SLIM_DMA_DC_STAT_1_WIDTH 20
APERF1_BW1_WMAX_RESET 0000000000
SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_SET 0x0000000c
USB_DVBUSPULSE_PULSE_CLR 0xfffff000
SYSAC_JPEG_PRIORITY_RESET 0000000000
I2C_SPI_SLV_RSR_RESET 0000000000
CM_OTPCTL_ENAB_LSB 4
SMI_CS_CLEAR_BITS 4:4
DMA13_TI_PERMAP_CLR 0xffe0ffff
CM_TECDIV_DIV_CLR 0xfffc0fff
HDMI_RAM_PACKET_3_0_RESET 0000000000
SH_CMD_WRITE_CMD_SET 0x00000180
EMMC_INTERRUPT_ATA_ERR_CLR 0xdfffffff
APERF0_GEN_CTRL_WIDTH 2
A2W_PLLB_FRAC_FRAC_LSB 0
USB_DTXFSTS7_WIDTH 32
MPHI_CTRL_STBY_MSB 27
APERF0_BW1_RMAX_RESET 0000000000
APERF0_BW1_CTRL_ID_CLR 0xffffe0ff
USB_GUSBCFG_ULPI_CLK_SUS_M_CLR 0xfff7ffff
USB_GOTGCTL_HST_SET_HNP_EN_CLR 0xfffffbff
DMA0_TI_SRC_DREQ_CLR 0xfffffbff
SD_DMRCRC1_LOW_RESET 0x0
USB_DIEPCTL0_EO_FR_NUM_BITS 16:16
A2W_PLLA_ANA3_RESET 0x00000180
A2W_PLLH_ANA_KAIPR_WIDTH 11
V3D_CT1CA_MASK 0xffffffff
SYSAC_V3D_LIMITER_ENABLE_RESET 0x0
CAM1_CAMDBG2_RESET 0000000000
GP_SEN0_SEN_MSB 31
HDMI_SCHEDULER_CONTROL_USE_PREDICTS_CLR 0xfffffffb
VEC_FREQ3_2_WIDTH 32
USB_GINTMSK_GOUT_NAK_EFF_MSB 7
GP_FSEL2_FSEL23_SET 0x00000e00
PM_AVS_STAT_ALERT_ARM_P_BITS 4:4
DMA5_CS_INT_LSB 2
DMA0_DEBUG_VERSION_BITS 27:25
CM_DPICTL_RESET 0000000000
DMA14_DEBUG_VERSION_LSB 25
DMA4_CONBLK_AD_RESET 0000000000
DMA13_DEBUG_DMA_STATE_LSB 16
INTERRUPT_SPARE2 ((64) + 60 )
SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_CLR 0xffff00ff
SD_SE_RL_CLR 0xfc0fffff
SD_DQRCRC14_FALL_CLR 0xffff0000
USB_DIEPINT0_IN_TKN_TXFEMP_CLR 0xffffffef
UART_MSR_DDSR_LSB 1
CM_EVENT_FLOSSA_CLR 0xffffbfff
DMA12_TXFR_LEN_XLENGTH_CLR 0xffff0000
MPHI_OUTDS_HANDLE_SET 0x1fe00000
SD_PHYC_BIST_MODE_CLR 0xfffffeff
USB_GI2CCTL_ADDR_LSB 16
HDMI_TX_PHY_TX_PHY_SPARE_WIDTH 32
USB_GUSBCFG_CORRUPT_TX_SET 0x80000000
MPHI_OUTDS_VALID_CLR 0xbfffffff
CM_ISPDIV_DIV_LSB 4
DMA5_STRIDE_WIDTH 32
DMA1_DEBUG_LITE_BITS 28:28
MPHI_HSINDDA_WIDTH 32
DMA12_DEBUG_VERSION_BITS 27:25
PM_PROC_MEMREP_LSB 3
CM_VPUCTL_GATE_MSB 6
SD_PT2_MASK 0xffffffff
PM_HDMI_RSTDR_MSB 19
DMA1_DEBUG_OUTSTANDING_WRITES_MSB 7
INTERRUPT_SPARE5 ((64) + 63 )
CM_SLIMDIV_DIV_BITS 23:0
USB_DTXFSTS4_MASK 0xffffffff
HDMI_RAM_PACKET_2_0_WIDTH 32
GRTCS1 0x1A005280 + 0x00:RW
SCALER_1_DMA (22*(1<<16))
CM_INTEN_WRFAIL_BITS 19:19
DMA4_CS_ERROR_BITS 8:8
MS_SEMA_25_MASK_CLR 0xfffffffe
SD_SF_MASK 0x3fffffff
CM_DSI1ECTL_KILL_SET 0x00000020
PCM_CS_A_RXF_SET 0x00400000
SLIM_DCC1_PA1_RESET 0000000000
DMA12_TI_BURST_LENGTH_MSB 15
HDMI_HORZB_MANUAL_HSP_LSB 10
USB_DOEPCTL0_SET_ODD_FR_MSB 29
PWM_DMAC_ENAB_BITS 31:31
V3D_PCTRS13_MASK 0x0000001f
USB_DOEPCTL0_SET_D1_PID_SET 0x20000000
CM_LOCK_FLOCKH_CLR 0xffffefff
CM_H264DIV_RESET 0000000000
EMMC_HWMAXAMP0_MASK 0x00ffffff
EMMC_IRPT_MASK_DATA_DONE_SET 0x00000002
HD_VID_CTL_VPOL_SET 0x10000000
EMMC_BLKSIZECNT_BLKSIZE_MS1_SET 0x00008000
IC0_FORCE0_CLR_MASK 0xffffffff
HD_HDM_CTL_PDSTBY_RESET 0x3
AVE_OUT_CTRL_NTSC_PAL_IDENT_LSB 13
VEC_CGMSAE_TOP_FORMAT 0x7e80604c:RW
SYSAC_UC_ARBITER_CONTROL_LIMIT_RESET 0x0
DSI0_PHYC_txhsclk_cont_sync_LSB 10
CM_EVENT_RESUS_BITS 22:22
EMMC_FORCE_IRPT_ACMD_ERR_SET 0x01000000
EMMC_FORCE_IRPT_DATA_DONE_MSB 1
A2W_PLLA_FRACR_WIDTH 20
MPHI_C1INDDB_LENGTH_LSB 0
A2W_PLLD_ANA0_RESET 0000000000
TXP_BASE 0x7e004000
SMI_DSR1_FSETUP_MSB 22
CM_DSI0PCTL_FRAC_MSB 9
UNICAM_IBSA0(x) MACRO
UNICAM_IBSA1(x) MACRO
DMA3_TI_SRC_WIDTH_CLR 0xfffffdff
SYSAC_HVSM_PRIORITY_N_PRIORITY_RESET 0x0
SD_DQRCRC12_FALL_RESET 0x0
TH0T3UD 0x18011000 + 0x2C:RW
HDMI_DVO_TIMING_ADJUST_C_WIDTH 32
MULTICORE_SYNC_SEMA_MASK_1 MULTICORE_SYNC_BASE_ADDRESS + 0x04:RW
SCALER_DISPEOLN_WIDTH 32
USB_GHWCFG4_EN_DESC_DMA_LSB 30
CM_DSI0ECTL_FRAC_LSB 9
USB_GPVNDCTL_NEW_REG_REQ_MSB 25
APERF0_BW1_CTRL_ID_EN_BITS 29:29
CAM0_CAMCAP0 0x7e800034:RW
CAM0_CAMCAP1 0x7e800038:RW
DMA9_TI_SRC_DREQ_CLR 0xfffffbff
A2W_SMPS_C_CTLR_RESET 0000000000
DMA0_TI_DEST_IGNORE_BITS 7:7
USB_DCTL_GMC_CLR 0xffff9fff
USB_GAHBCFG_P_TXF_EMP_LVL_MSB 8
A2W_PLLB_MULTI_WIDTH 0
EMMC_CONTROL1_CLK_FREQ8_BITS 15:8
USB_GINTMSK_SOF_SET 0x00000008
APERF1_BW2_CTRL_LATHALT_LSB 28
SCALER_DISPECTRL_TWOD_SINGLE_CLR 0x01ffffff
TB_JTB_PORTEN 0x7e20b814:RW
AVE_IN_STATUS_INTERLACED_SET 0x00000400
A2W_SMPS_L_SPA_MASK 0x000003ff
MPHI_C0INDCF_LENGTH_RESET 0x0
EMMC_HWCAP1_DDR50_BITS 2:2
HDMI_CEC_TX_DATA_3_WIDTH 32
TB_JTB_CONFIG_OUT_MS_BITS 6:6
HDMI_VERTA1_MASK 0x01ffffff
IC0_FORCE1_SET 0x7e00204c:RW
USB_DOEPINT0_IN_TKN_TXFEMP_LSB 4
ASB_V3D_S_CTRL_EMPTY_CLR 0xfffffffb
FPGA_CTRL0_CAM_CTL2_BITS 2:2
CM_PCMCTL 0x7e101098:RW
L1_L1_SANDBOX_START2_START_ADDR_MSB 29
DMA8_CS_RESET_MSB 31
SCALER_DISPCTRL_IRQ_EN_LSB 0
A2W_PLLD_DSI0_CHENB_BITS 8:8
HDMI_READ_POINTERS_DRFT_FULL_MINUS_SET 0x00100000
USB_GINTMSK_INCOMPL_ISO_OUT_LSB 21
DMA4_TI_WAITS_MSB 25
EMMC_CONTROL2_ACTO_ERR_LSB 1
IC1_FORCE1_SET_RESET 0000000000
PCM_RXC_A_CH1EN_MSB 30
PCM_RXC_A_CH2WID_LSB 0
GP_FSEL6_FSEL64_BITS 14:12
CM_TDCLKEN_MPHIRDFT_MSB 10
EMMC_CONTROL0_HCTL_CRDDET_MSB 6
ST_CS_WIDTH 32
A2W_PLLA_CORE_CHENB_LSB 8
A2W_XOSC_CTRL_DDROK_SET 0x00010000
IC0_PROFILE_MASK 0x0000ffff
SD_DQLCRC2_FALL_MSB 15
ASB_H264_M_CTRL_MASK 0x00ffffff
GP_FSEL1_FSEL12_MSB 8
GP_FSEL5_FSEL56_BITS 20:18
MPHI_OUTDDB_LENGTH_BITS 19:0
EMMC_HWCAP1_MASK 0x03ffef77
APERF0_BW0_ATRANS 0x7e009844:RO
UART_LSR_TEMT_CLR 0xffffffbf
CCP2TX_TSC_WIDTH 4
DMA15_DEST_AD_MASK 0xffffffff
CGMSAE_BOT_DATA 0x7e806058:RW
MPHI_C1INDCF_LENERR_RESET 0x0
GP_FSEL4_FSEL48_BITS 26:24
I2CC_EN (1 << 15)
EMMC_CONTROL0_WAKE_ONINT_EN_MSB 24
PCM_MODE_A_PDMN_MSB 27
CM_UARTCTL_KILL_CLR 0xffffffdf
SD_SE_T_XSR_BITS 5:0
HDMI_VERTA0_MANUAL_VAL0_SET 0x00001fff
SD_SE_T_RTP_LSB 8
IC0_PROFILE_WIDTH 16
USB_GRXSTSP_DEV_FN_MSB 24
PCM_CS_A_TXD_BITS 19:19
HDMI_RAM_PACKET_10_7_WIDTH 32
DMA0_TI_MASK 0x07fffffb
USB_GHWCFG4_EN_SESSIONEND_FILTER_LSB 24
A2W_XOSC_PWR_BYPASS_CLR 0xfffffffe
PWMCTL_RPTL1 2
PWMCTL_RPTL2 10
PWMCTL_RPTL3 18
PWMCTL_RPTL4 26
AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_LSB 29
SD_SA_RFSH_T_SET 0xffff0000
SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_SET 0x00000030
EMMC_CONTROL0_BOOT_EN_SET 0x00200000
USB_DIEPCTL0_SET_D1_PID_LSB 29
CM_UARTCTL_SRC_BITS 3:0
CAM0_CAMCLT_WIDTH 32
SLIM_DCC2_PA1_MASK 0x00ffff3f
DMA11_CS_DREQ_STOPS_DMA_MSB 5
DMA6_STRIDE_D_STRIDE_MSB 31
VPU_ARB_CTRL_L2_ALGORITHM_SET 0x000000c0
JP_C2BA 0x7e005054:RW
DMA2_DEBUG_READ_ERROR_SET 0x00000004
GROPCTR_FBC_CZ_FE_UNUSED 0x2B
ASB_V3D_M_CTRL_RCOUNT_LSB 4
I2C_SPI_SLV_FR_TXFLEVEL_BITS 6:10
CM_DSI0PCTL_SRC_CLR 0xfffffff0
VEC_DAC_MISC 0x7e806214:RW
DMA0_CS_DREQ_LSB 3
L2_CONT_OFF_l2_flush_MSB 2
PM_PADS5_POWOK_BITS 5:5
L1_IC0_PRIORITY_IC0_APRIORITY3_MSB 15
DSI0_PHYC_txulps_clk_sync_CLR 0xfffffdff
L1_D1_WR_MISSES_WIDTH 0
SLIM_DCC5_PA0_WIDTH 24
GP_SET0_WIDTH 32
EMMC_DMA_STATUS_LEN_NOMATCH_BITS 2:2
SH_RSP3_CID_CSD_MSB 31
AVE_IN_CTRL_FRAME_MODE_CLR 0xfffff9ff
DMA2_CS_INT_LSB 2
TB_BOOT_OPT_FAST_OPT_BITS 0:0
HDMI_CPU_CLEAR_WIDTH 32
CM_GP2CTL_BUSY_LSB 7
PCM_RXC_A_CH2WEX_SET 0x00008000
TXP_CTRL_FIELD_SET 0x00000008
A2W_PLLB_SP0R_MASK 0x000003ff
TB_BOOT_OPT_SDC_BEHAV_PHY_CLR 0xffffffdf
AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_CLR 0xfffff000
SMI_L_WIDTH 32
USB_DOEPDMA0 0x7e980b14:RW
DSI0_INT_EN_WIDTH 28
V3D_SLCACTL 0x7ec00000 +0x0024:RW
PM_GNRIC_MRDONE_CLR 0xffffffef
CM_INTEN_LOSSA_BITS 5:5
CAM0_CAMIDI0_MASK 0xffffffff
GP_FEN0_FENn0_BITS 31:0
DMA9_DEBUG_FIFO_ERROR_MSB 1
DSI1_DISP1_CTRL_WIDTH 32
SLIM_DMA_DC8_WIDTH 32
DMA15_CS_ABORT_MSB 30
EMMC_FORCE_IRPT_CARD_OUT_MSB 7
DMA2_TI_DEST_DREQ_LSB 6
DMA9_CS_PAUSED_SET 0x00000010
DSI_DISP0_CTRL 0x7e209000 + 0x18:RW
CM_ISPCTL_GATE_CLR 0xffffffbf
SCALER_DISPCTRL_DSP3_MUX_MSB 19
SPI_CS_RXF_CLR 0xffefffff
A2W_PLLA_CTRL_PDIV_LSB 12
DMA2_TI_INTEN_BITS 0:0
TXP_PROGRESS_LINES_SET 0x00000fff
CCP2TX_TDL_LEN_SET 0x3fffffff
SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_LSB 4
FPGA_CTRL0_SPARE_OUT_BITS 31:20
DMA0_TXFR_LEN 0x7e007014:RO
USB_DOEPINT0_BNA_RESET 0x0
CAM1_CAMIDS 0x7e801148:RW
OTP_STATUS_REG_MASK 0xffffffff
GP_LEN0_LENn0_BITS 31:0
SD_SA_PGEHLDE_LSB 8
CM_DSI0PCTL_ENAB_LSB 4
SH_CMD_MASK 0x0000cfff
A2W_PLLC_DIG2_MASK 0x00ffffff
I2C_SPI_SLV_DR_TXFLEVEL_MSB 26
IMASK5_0 0x7e002024:RW
IMASK5_1 0xffffffff:RW
PCM_GRAY_RXLEVEL_BITS 9:4
EMMC_BLKSIZECNT_SDMA_BLKSIZE_LSB 12
ASB_V3D_S_CTRL_FULL_SET 0x00000008
MPHI_RXAXICFG 0x7e006044:RW
HDMI_RAM_PACKET_12_3_RESET 0000000000
USB_DIEPCTL0_STALL_RESET 0x0
DMA6_CONBLK_AD_SCB_ADDR_BITS 31:5
USB_GGPIO_GPO_SET 0xffff0000
CM_CAM0CTL_RESET 0000000000
SD_CS_EXCEPTION_RESET 0x0
MPHI_OUTDFS_DFIFOLVL_BITS 15:0
DMA13_TI_SRC_WIDTH_CLR 0xfffffdff
USB_DCFG_DEV_ADDR_LSB 4
DMA14_TI_SRC_INC_SET 0x00000100
APERF1_BW2_AMAX_RESET 0000000000
GP_GPTEST_SMPS_LSB 0
DMA14_TI_DEST_WIDTH_CLR 0xffffffdf
A2W_PLLD_DSI1_CHENB_LSB 8
EMMC_TUNE_STEP_RESET 0000000000
IC1START 0xffffffff:RW
MPHI_MOUTFS_RPTR_CLR 0xc00fffff
DMA6_CS_ERROR_LSB 8
USB_DIEPINT0_TXF_EMPTY_BITS 7:7
TE_0TIMER 0x7e20e008:RW
USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_LSB 31
USB_DOEPDMA4 0x7e980b94:RW
SYSAC_L2_ARBITER_CONTROL_RESET 0000000000
SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_MSB 5
A2W_PLLA_ANA0_RESET 0000000000
PM_RSTS_HADDRH_CLR 0xfffffffb
HDMI_SW_RESET_CNTRL 0x7e902004:RW
MPHI_HSINDDA_START_RESET 0x0
PM_PROC_MRDONE_CLR 0xffffffef
SD_SD_T_RCD_CLR 0xfffffff0
SCALER_DISPCTRL_DSP2_IRQ_CTRL_MSB 12
GP_AREN2_ARENn64_CLR 0xffffffc0
EMMC_STATUS_RETUNING_REQ_CLR 0xfffffff7
I2C_SPI_SLV_DR_UE_CLR 0xfffffdff
STC0 0x7e00300c:RW
STC1 0x7e003010:RW
USB_GI2CCTL_BSY_DNE_LSB 31
STC3 0x7e003018:RW
USB_DOEPCTL7_WIDTH 32
DMA4_STRIDE 0x7e007418:RO
EMMC_IRPT_EN_CTO_ERR_CLR 0xfffeffff
CMI_CAM1_HSSRC_LSB 0
V3D_DBQHLT_WIDTH 32
HDMI_RAM_PACKET_5_4_MASK 0xffffffff
PM_HDMI_RSTDR_CLR 0xfff7ffff
DMA7_CONBLK_AD_SCB_ADDR_BITS 31:5
MPHI_C0INDDB_LENGTH_RESET 0x0
GR_PPL_BASE 0x1A005600
DMA15_NEXTCONBK_ADDR_LSB 5
HDMI_TX_PHY_HDMI65_TX_PHY_TMDS_CFG (HDMI_BASE_ADDRESS + 0x2c0) + 20:RW
NOWNT 0x7e008000 + 0x4:RW
STCS 0x7e003000:RW
DMA0_DEBUG_DMA_ID_CLR 0xffff00ff
USB_GINTMSK_INCOMPL_ISO_IN_BITS 20:20
CM_OSCFREQF_FRAC_BITS 19:0
HDMI_RAM_GCP_3_MASK 0xffffffff
USB_DOEPDMA6 0x7e980bd4:RW
USB_GMDIOCSR_MASK 0x0000ffff
GRPCLSZ 0x1A005600 + 0x0C:RW
FPGA_STATUS0_SPARE_IN_SET 0xfff80000
APERF0_BW1_CTRL_BUS_LSB 0
DMA13_DEST_AD_D_ADDR_LSB 0
MPHI_C1INDS_WORDS_RESET 0x0
DMA5_DEST_AD 0x7e007510:RO
CM_TCNTCTL_SRC1_SET 0x00003000
SCALER_DISPBKGND0_MASK 0xffffffff
DMA6_CS_INT_BITS 2:2
CAM0_CAMIVSTA 0x7e80012c:RW
CM_H264CTL_FRAC_SET 0x00000200
MPHI_C1INDDB_TENDINT_LSB 29
DMA_INT_STATUS_MASK 0x0000ffff
DMA13_DEBUG_VERSION_MSB 27
A2W_PLLC_ANA3_MASK 0x00ffffff
EMMC_FORCE_IRPT_CTO_ERR_CLR 0xfffeffff
DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
EMMC_IRPT_MASK_RESET 0000000000
SYSAC_V3D_PRIORITY_PRIORITY_MSB 3
EMMC_CMDTM_CMD_ISDATA_CLR 0xffdfffff
SD_WTC_RESET 0000000000
DMA4_DEBUG_READ_ERROR_SET 0x00000004
PM_AVS_EVENT_ALERT_H264_I_LSB 2
GRPSFCG 0x1A005600 + 0x44:RW
USB_DPTXFSIZ7_MASK 0xffffffff
L1_D_FLUSH_E_WIDTH 30
GP_FSEL2_FSEL28_MSB 26
PCM_INTSTC_A_RXR_BITS 1:1
USB_DIEPINT9_WIDTH 32
MPHI_MOUTFS_UFLOW_LSB 31
GP_FSEL4_FSEL49_CLR 0xc7ffffff
SD_DQLCRC15_FALL_LSB 0
USB_GUSBCFG_USB_TRD_TIM_BITS 13:10
HDMI_VERTB1_WIDTH 22
SYSAC_UC_ARBITER_CONTROL_ALGORITHM_RESET 0x0
SMIDS_PACEALL 15
MPHI_C0INDCF_EMPTY_LSB 31
I2C_SPI_SLV_DMACR_DMAONERR_BITS 2:2
APERF1_BW1_CTRL_ID_CLR 0xffffe0ff
HDMI_DETECTED_HORZA_MANUAL_HAP_LSB 0
PM_AVS_INTEN_ALERT_H264_I_CLR 0xfffffffb
DMA13_DEBUG_FIFO_ERROR_LSB 1
V3D_PCS_MASK 0x0000013f
A2W_PLLB_SP2_CHENB_CLR 0xfffffeff
SYSAC_HOST_PRIORITY_PRIORITY_MSB 3
STC_0 0x7e003004:RO
STC_1 0xffffffff:RO
SD_DQRCRC4_FALL_BITS 15:0
DMA7_TI_SRC_INC_SET 0x00000100
USB_DOEPDMA15_WIDTH 32
MS_SEMA_18_RESET 0000000000
USB_HPRT_CONN_DET_BITS 1:1
MS_SEMA_9_WIDTH 1
USB_DIEPTXF10_WIDTH 32
DMA13_SOURCE_AD_S_ADDR_LSB 0
L1_IC0_CONTROL_BP_DISABLE_MSB 3
USB_HCSPLT6_WIDTH 32
HD_VID_CTL_ERROR_CLR 0xf9ffffff
CM_EVENT_FLOSSD_CLR 0xfffdffff
AVE_IN_STATUS_INTERLACED_LSB 10
MS_MBOX_6_MASK 0xffffffff
MS_SEMA_5_MASK_BITS 0:0
HD_MAI_CTL_PAREN_MSB 8
APHY_CSR_ADDR_SPR0_RW 0x7ee06088:RW
DMA9_TI_PERMAP_SET 0x001f0000
USB_GOTGCTL_B_SES_VLD_BITS 19:19
L1_L1_SANDBOX_START1_CTRL_LSB 0
INTERRUPT_DMA10 ((64) + 26 )
USB_GRSTCTL_AHB_IDLE_MSB 31
CM_GP2CTL_KILL_MSB 5
CPG_Param1_MASK 0xffffffff
DMA5_CONBLK_AD_RESET 0000000000
ASB_H264_M_CTRL 0x7e00a01c:RW
DMA0_CS_DREQ_STOPS_DMA_SET 0x00000020
INTERRUPT_I2SPCM ((64) + 55 )
CM_EVENT_FGAINA_MSB 10
CM_SDCCTL_CTRL_SET 0x0000f000
EMMC_HWCAP1_MULTIPLIER_BITS 23:16
STC_x(x) MACRO
EMMC_HWCAP1_RESET 0x03000777
CM_INTEN_LOSSA_SET 0x00000020
PCM_GRAY_FLUSHED_BITS 15:10
HDMI_RAM_PACKET_12_0_MASK 0xffffffff
USB_DOEPINT0_MASK 0xffffffff
GP_FSEL3_FSEL38_SET 0x07000000
CM_PCMCTL_SRC_LSB 0
USB_DOEPTSIZ0_MC_RESET 0x0
MPHI_C0INDFS_DFIFOLVL_MSB 15
USB_DIEPCTL0_MPS_SET 0x000007ff
USB_DOEPCTL14_WIDTH 32
MS_SEMA_12_MASK_SET 0x00000001
DMA7_TXFR_LEN_XLENGTH_LSB 0
HD_MAI_THR_PANICLOW_BITS 21:16
DMA12_TI_DEST_DREQ_LSB 6
SD_DMRCRC0_WIDTH 32
MS_MBOX_6_MBOX_CLR 0x00000000
APERF0_BW2_CTRL 0x7e0098c0:RW
A2W_PLLC_CORE0R_MASK 0x000003ff
DMA5_DEBUG_OUTSTANDING_WRITES_MSB 7
PCM_CS_A_RXON_SET 0x00000002
CM_TD1CTL_ENAB_CLR 0xffffffef
PM_DUMMY_RESET 0x00000001
INTERRUPT_DMA15 ((64) + 31 )
DPHY_CSR_PHY_FIFO_PNTRS 0x7ee07044:RW
ST_CLO_MASK 0xffffffff
HD_VID_CTL_UFEN_BITS 30:30
EMMC_CONTROL1_SRST_HC_MSB 24
DMA1_STRIDE_D_STRIDE_CLR 0x0000ffff
DMA6_CS_DREQ_STOPS_DMA_BITS 5:5
IC1_MASK0_RESET 0000000000
SCALER_DISPCTRL_DSP1_PANIC_CLR 0xf3ffffff
PWM_STA_GAPO2_MSB 5
DMA0_CS_PAUSED_SET 0x00000010
PM_IMAGE_PERIRSTN_SET 0x00000040
USB_HFNUM_WIDTH 32
EMMC_CONTROL1_DATA_TOUNIT_MSB 19
IC1_FORCE0_CLR_MASK 0xffffffff
DMA4_TI_BURST_LENGTH_BITS 15:12
CM_TIMERCTL_FRAC_CLR 0xfffffdff
CM_H264DIV_DIV_CLR 0xffff000f
PIXELVALVE2_INTSTAT_MASK 0x000003ff
I2C_SPI_SLV_DR_TXDMAPREQ_SET 0x00000400
DMA_INT_STATUS_INT2_MSB 2
CAM1_CAMCLT_RESET 0000000000
DMA_INT_STATUS_INT14_SET 0x00004000
UART_LSR_DR_SET 0x00000001
SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_MSB 15
CM_SLIMDIV 0x7e1010ac:RW
CM_VPUCTL_BUSYD_LSB 8
L1_L1_SANDBOX_PERI_BR_sandbox_peri_MSB 12
EMMC_HWCAP1_SPI_BLOCKMODE_MSB 25
USB_DOEPCTL0_SET_D0_PID_RESET 0x0
USB_DOEPTSIZ13 0x7e980cb0:RW
A2W_PLLC_ANA_STAT_MASK 0x00000fff
USB_DIEPDMA0_WIDTH 32
DMA1_DEBUG_DMA_STATE_MSB 24
A2W_SMPS_L_SCVR 0x7e102bd0:RW
DMA15_CS_DREQ_STOPS_DMA_MSB 5
GRPCLXY 0x1A005600 + 0x08:RW
USB_DIEPDMA0 0x7e980914:RW
USB_DOEPINT0_TXF_EMPTY_CLR 0xffffff7f
SCALER_DISPCTRL_VSCL_DIS_MSB 31
DMA7_TXFR_LEN 0x7e007714:RO
APERF0_BW2_CTRL_ID_EN_BITS 29:29
CCP2TX_TTC_LCN_LSB 0
USB_DOEPTSIZ14 0x7e980cd0:RW
DMA10_CS_DISDEBUG_SET 0x20000000
USB_HCDMA3_MASK 0xffffffff
EMMC_BLKSIZECNT_MASK 0xffffffff
A2W_XOSC_BIAS_HIGHP_CLR 0xffffffef
DMA13_NEXTCONBK 0x7e007d1c:RO
USB_GHWCFG2_NUM_HOST_CHAN_CLR 0xffffffff11
DSI1_INT_EN_RESET 0000000000
A2W_PLLD_ANA_STAT 0x7e102450:RW
USB_DFIFO15_MASK 0xffffffff
A2W_PLLH_DIG2_WIDTH 24
HDMI_CTS_0_RESET 0000000000
DMA8_CS_ACTIVE_BITS 0:0
CM_GNRICCTL_MASH_CLR 0xfffff9ff
A2W_PLLC_ANA0R 0x7e102830:RW
USB_DIEPDMA2 0x7e980954:RW
TE_1VSWIDTH_WIDTH 32
DMA3_NEXTCONBK 0x7e00731c:RO
CSI2_RGSP CSI2_BASE_ADDRESS + 0x0C:RW
SH_HBLC_BLOCKCOUNT_BITS 8:0
INTERRUPT_PWA1 ((64) + 46 )
A2W_PLLB_ARM_BYPEN_BITS 9:9
SLIM_DCC7_STAT_RESET 0000000000
IC1_BASE 0x7e002800
USB_DIEPDMA3 0x7e980974:RW
DMA15_CS_RESET_CLR 0x7fffffff
A2W_SMPS_CTLB0R 0x7e1028b0:RW
TB_JTB_CONFIG_D_HOLD_SET 0x00003000
I2C_SPI_SLV_CR_ENCTRL_CLR 0xffffffbf
HDMI_RAM_GCP_6_RESET 0000000000
APERF0_BW0_WTWAIT_WIDTH 32
TRANSPOSER_BASE_ADDRESS 0x7e004000
STC1_1 0xffffffff:RW
GR_VCACHE_SIZE 0x00002000
HDMI_MAI_CHANNEL_MAP_RESET 0x00fac688
DMA0_TI_SRC_INC_MSB 8
DMA5_TXFR_LEN_XLENGTH_MSB 15
A2W_PLLH_ANA_SCTL_RESET_SET 0x00000010
EMMC_IRPT_EN 0x7e300038:RW
MPHI_C1INDDB_HANDLE_CLR 0xf00fffff
DMA12_DEBUG_FIFO_ERROR_BITS 1:1
CM_SYSDIV 0x7e101014:RO
A2W_PLLC_ANA1R 0x7e102834:RW
USB_DOEPINT0_SETUP_MSB 3
SD_CS_CLKOFF_MSB 14
DMA9_DEST_AD_MASK 0xffffffff
USB_DIEPDMA6 0x7e9809d4:RW
GP_REN1_RENn32_LSB 0
FPGA_STATUS0_NAND_RNB_CLR 0xffffffbf
CM_PLLH_ANARST_CLR 0xfffffeff
GP_GPTEST_WIDTH 4
STC1_0 0x7e003010:RW
HDMI_RAM_PACKET_12_4_RESET 0000000000
PWM_CTL_USEF1_SET 0x00000020
A2W_PLLH_AUX_RESET 0x00000100
USB_GUSBCFG_FS_INTF_CLR 0xffffffdf
A2W_SMPS_CTLB1R 0x7e1028b4:RW
AVE_OUT_CR_COEFF_GREEN_COEFF_SET 0x000ffc00
PWM_STA_GAPO2_CLR 0xffffffdf
AUX_SPI_CNTL1_EMPTYIRQ 0x00000040
DMA15_TXFR_LEN 0x7ee05014:RO
STC1_x(x) MACRO
AVE_OUT_Y_COEFF_BLUE_COEFF_BITS 9:0
PM_GNRIC_ISPOW_CLR 0xfffffffb
DMA7_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
SYSAC_V3D_LIMITER_SPARE_LSB 1
USB_DIEPTXF10_MASK 0xffffffff
USB_GHWCFG3_VENDOR_CTL_INTERFACE_BITS 9:9
DMA9_TI_WAIT_RESP_SET 0x00000008
APERF1_BW2_WMAX 0x7ee080d8:RO
EMMC_INTERRUPT_DMA_ERR_LSB 28
A2W_PLLC_ANA2R 0x7e102838:RW
EMMC_INTERRUPT_DCRC_ERR_SET 0x00200000
A2W_SMPS_L_SCAR_RESET 0000000000
DMA15_CS_END_BITS 1:1
EMMC_CMDTM_CMD_IXCHK_EN_BITS 20:20
DSI0_HS_CLT0_MASK 0xfffffffc
AVE_OUT_STATUS_VFRONT_PORCH_BITS 7:7
CAM1_CAMIBWP_RESET 0000000000
USB_DIEPCTL0_SNAK_BITS 27:27
I2C_SPI_SLV_CR_SPI_LSB 1
EMMC_BLKSIZECNT_BLKSIZE_MSB 11
I2C_SPI_SLV_ICR_OEIC_SET 0x00000008
GP_LEN2_WIDTH 6
ASB_ISP_M_CTRL 0x7e00a014:RW
GP_LEV2_LEVn64_SET 0x0000003f
A2W_SMPS_CTLB2R 0x7e1028b8:RW
USB_DFIFO5_WIDTH 32
MS_ICSET_0_ICSET_0_BITS 0:0
ASB_H264_M_CTRL_CLR_ACK_CLR 0xfffffffd
EMMC_FORCE_IRPT_BLOCK_GAP_SET 0x00000004
HD_MAI_FMT_RESET 0000000000
TIMER_CTRL_FREEDIV_SHIFT 16)
GP_HEN1_HENn32_BITS 31:0
USB_GINTMSK_WK_UP_INT_CLR 0x7fffffff
DMA5_STRIDE_S_STRIDE_CLR 0xffff0000
PM_PADS5_WIDTH 7
PM_RSTS_WIDTH 13
CAM1_CAMIDCD_MASK 0xffffffff
A2W_PLLA_PER_CHENB_LSB 8
USB_DOEPINT0_IN_TKN_EP_MIS_RESET 0x0
VPU1_UNIFORM_MEM_BASE_ADDRESS 0xffffffff:RW
A2W_PLLC_ANA3R 0x7e10283c:RW
GP_FSEL3_RESET 0000000000
SD_CS_STOP_BITS 7:7
DMA3_TI_TDMODE_CLR 0xfffffffd
PM_GNRIC_RSTN_SET 0x00000fc0
SD_VIN_INT_EN_LSB 28
SMI_DSW1_WPACEALL_CLR 0xffff7fff
A2W_PLLD_ANA_SCTLR 0x7e102d50:RW
HDMI_PACKET_FIFO_CFG 0x7e902120:RW
USB_DOEPCTL0_EO_FR_NUM_RESET 0x0
A2W_PLLB_ANA_VCO_RESET 0000000000
USB_DIEPTSIZ2_MASK 0xffffffff
APERF1_BW2_CTRL_EN_LSB 30
A2W_SMPS_C_MULTI 0x7e102fc0:RW
EMMC_BUS_CTRL_BE_PWR_CLR 0x80ffffff
A2W_PLLH_RCAL 0x7e102460:RW
ARM_IF_ENABLE 0x00000080
DMA0_CS_ERROR_BITS 8:8
DMA4_TI_WAIT_RESP_LSB 3
DMA9_TI_SRC_WIDTH_BITS 9:9
USB_DIEPTSIZ12_MASK 0xffffffff
DMA9_CS_ABORT_MSB 30
CCP2TX_TPC_MASK 0x0000ffff
SMI_DSW1_RESET 0x0101000c
SD_DQRCRC5_FALL_SET 0x0000ffff
SLIM_DMA_MC_CON_WIDTH 2
PCM_CS_A_TXSYNC_SET 0x00002000
V3D_DBCFG 0x7ec00000 +0x0e00:RW
USB_DFIFO10_WIDTH 32
PM_AVS_RSTDR_ARM_P_CLR 0xffffffef
USB_DOEPTSIZ0_XFERSIZE_MSB 18
PM_AUDIO_RESET 0x003000ff
DMA2_CONBLK_AD_SCB_ADDR_LSB 5
UART_SCR_MASK 0x000000ff
PM_RSTS_HADSRQ_SET 0x00000100
DMA10_TXFR_LEN_XLENGTH_BITS 15:0
USB_GI2CCTL_DAT_SE0_BITS 28:28
EMMC_CMDTM_TM_MULTI_BLOCK_BITS 5:5
DMA5_TI_SRC_WIDTH_SET 0x00000200
PIXELVALVE2_VERTB_MASK 0xffffffff
CM_GP2DIV_DIV_LSB 0
PM_AUDIO_APSM_SET 0x000fffff
GP_FSEL3_FSEL36_CLR 0xffe3ffff
USB_PCGCR_GATE_HCLK_MSB 1
PM_IMAGE_CFG_BITS 22:16
MS_SEMA_16_WIDTH 1
CM_EVENT_GAIND_SET 0x00000008
CM_PLLTCNT2_CNT_CLR 0xff000000
EMMC_IRPT_MASK_ADMA_ERR_CLR 0xfdffffff
CM_OTPCTL_BUSYD_BITS 8:8
USB_GMDIOGEN 0x7e980084:RW
MPHI_C1INDDB_MTERM_LSB 28
USB_DOEPTSIZ0_RX_DPID_MSB 30
CM_TDCLKEN_IMAGETD_SET 0x00002000
PRM_BASE 0x7e20d000
DMA12_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
CM_GNRICCTL_ENAB_LSB 4
HDMI_PERT_TEST_LENGTH 0x7e902088:RW
A2W_SMPS_C_CLK 0x7e1021c0:RW
PM_IMAGE 0x7e100108:RW
MS_SEMA_19_MASK_SET 0x00000001
DMA1_CS_RESET_SET 0x80000000
SMI_DSR0_RPACEALL_MSB 15
AVE_IN_CTRL_FRAME_RATE_IRQ_EN_MSB 6
A2W_PLLA_ANA_KAIP_RESET 0x0000033a
EMMC_STATUS_DAT_LEVEL0_SET 0x00f00000
A2W_HDMI_CTL_RCALR 0x7e102980:RW
TB_TASK_RXDATA1_MASK 0xffffffff
OTP_JTAG_DEBUG_KEY_SIZE_IN_ROWS 4
USB_HCSPLT0_XACT_POS_LSB 14
CAM0_CAMCLK 0x7e800010:RW
HD_CSC_32_31_MASK 0xffffffff
SD_SECSRT0_ADDR_LS_RESET 0x0
L1_IC1_CONTROL_RAS_DISABLE_LSB 4
HDMI_RAM_PACKET_10_5_MASK 0xffffffff
USB_DIEPINT3_MASK 0xffffffff
SDDELC1 SD_DELC1
SDDELC2 SD_DELC2
SDDELC3 SD_DELC3
DMA15_TXFR_LEN_MASK 0x3fffffff
DMA14_TI_SRC_DREQ_MSB 10
TB_BOOT_OPT_EIGHT_BANK_LSB 1
DMA2_CS_PANIC_PRIORITY_MSB 23
AVE_IN_CURRENT_ADDRESS_CUR_ADDR_LSB 0
SD_PHYC_MDLL_TMODE_CLR 0xfffeffff
TE_2C_WIDTH 32
DMA15_CS_DREQ_BITS 3:3
A2W_PLLA_PER_CHENB_BITS 8:8
CM_EVENT_RESUS_CLR 0xffbfffff
EMMC_INTERRUPT_BOOTACK_SET 0x00002000
DPHY_CSR_BOOT_READ_DQS_GATE_CTRL 0x7ee07040:RW
A2W_SMPS_LDO0R_RESET 0000000000
USB_DIEPCTL0_EO_FR_NUM_CLR 0xfffeffff
PWM_DAT3_MASK 0000000000
SMI_FD_FCNT_SET 0x0000003f
USB_HPTXSTS_HPTXFSPCAVAIL_RESET 0x0
DMA3_DEBUG_DMA_STATE_BITS 24:16
DMA6_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
CM_PLLH_WIDTH 10
PCM_CS_A_RXD_LSB 20
PM_DSI1_CTRLEN_SET 0x00000001
TXP_CTRL_FIELD_BITS 3:3
CM_CAM1DIV_DIV_BITS 15:4
PM_DSI0_CTRLEN_MSB 0
L1_IC1_CONTROL_BP_DISABLE_LSB 3
MPHI_HSINDS_DISCARD_SET 0x80000000
VEC_REVID_WIDTH 32
A2W_PLLC_CORE2_DIV_CLR 0xffffff00
A2W_PLLB_SP0 0x7e1024e0:RW
A2W_PLLB_SP1 0x7e1025e0:RW
A2W_PLLB_SP2 0x7e1026e0:RW
DMA14_CS_INT_CLR 0xfffffffb
USB_HCSPLT0_HUB_ADDR_BITS 13:7
PCM_INTSTC_A_TXERR_CLR 0xfffffffb
EMMC_CONTROL0_HCTL_HS_EN_CLR 0xfffffffb
EMMC_IRPT_EN_INT_B_MSB 10
DMA8_TI_SRC_DREQ_BITS 10:10
USB_GINTMSK_USB_RST_RESET 0x0
PCM_INTEN_A_TXW_MSB 0
PM_CAM1_LDOCTRL_MSB 20
HDMI_RAM_PACKET_5_2_MASK 0xffffffff
USB_DTHRCTL_ISO_THR_EN_RESET 0x0
L1_D_PRIORITY_c0_l2_priority_MSB 3
OTP_HDCP_AES_KEY_ROW (((((((((((8 +4)+4)+1)+1)+1)+4)+4)+1)+4)+4)+1)
USB_DIEPTXF5_MASK 0xffffffff
VPU_ARB_CTRL_UC_DELAY_SET 0x0000000c
PWM_CTL_RPTL4_SET 0x04000000
USB_HPTXFSIZ_WIDTH 32
JP_MOP 0x7e005024:RW
CAM0_CAMIHWIN 0x7e800120:RW
DMA4_TXFR_LEN_MASK 0x3fffffff
SPI_CS_MASK 0x001f07ff
DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
L2_CONT_OFF_l2_flush_flush_limit_CLR 0xfff0ffff
USB_DOEPINT13_MASK 0xffffffff
SD_CMD 0x7ee00034:RO
A2W_PLLD_DSI1_DIV_LSB 0
DMA15_CS_PRIORITY_MSB 19
TB_BOOT_OPT_DONT_SET_VPU_CLK_LSB 10
TXP_CTRL_VSTART_AT_EOF_LSB 15
CCP2TX_TIC_TQIT_LSB 4
GP_GPTEST_SPARE_CLR 0xfffffff1
DMA6_SOURCE_AD_S_ADDR_SET 0xffffffff
TB_JTB_CONFIG_TMS_RISE_CLR 0xfffffeff
SD_VIN_CLEAR_RESET 0x0
HD_MAI_DAT_MASK 0xffffffff
MPHI_C0INDS_HANDLE_LSB 21
A2W_PLLH_CTRL_RESET 0x00010000
SD_DQRCRC0_RISE_MSB 31
USB_DOEPINT0_SETUP_SET 0x00000008
SD_DQLCRC13_RISE_SET 0xffff0000
EMMC_CONTROL1_CLK_STABLE_LSB 1
CM_TECCTL_ENAB_SET 0x00000010
CM_HSMCTL_KILL_LSB 5
CM_ISPCTL_GATE_BITS 6:6
CM_TD0CTL_GATE_LSB 6
PM_AVS_INTEN_ALERT_SYSTEM_A_BITS 1:1
HDMI_RAM_GCP_4_WIDTH 32
APERF1_BW2_CTRL_ID_EN_RESET 0x0
CM_EVENT_FGAIND_SET 0x00002000
PCM_RXC_A_CH2WID_BITS 3:0
DMA14_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
HDCP_KEY_ADR_MASK 0x000000ff
USB_HCFG_LS_SUPP_SET 0x00000004
APERF0_BW1_WTWAIT_RESET 0000000000
DSI_TA_TO_CNT 0x7e209000 + 0x38:RW
SYSAC_DMA_ARBITER_CONTROL_L2 0x7e009054:RW
SPI_CS_RXR_CLR 0xfff7ffff
MPHI_INTSTAT_HSDCFOFLW_RESET 0x0
CM_GP0DIV_WIDTH 24
DMA6_CONBLK_AD_RESET 0000000000
A2W_XOSC_CTRL_HDMIEN_BITS 1:1
CM_AVEODIV_DIV_BITS 15:12
USB_DCFG_DESC_DMA_SET 0x00800000
AUX_MU_STAT_RX_DATA 0x00000001
CM_INTEN_FLOSSD_BITS 17:17
GP_PUDCLK1_PUDCLKn32_LSB 0
CM_UARTCTL_RESET 0000000000
USB_GINTMSK_HCH_INT_BITS 25:25
DMA1_CS_END_SET 0x00000002
ST_C2 0x7e003014:RW
HDMI_RAM_PACKET_12_2_WIDTH 32
DMA7_DEBUG_READ_ERROR_CLR 0xfffffffb
SD_PHYC_MDLL_TMODE_RESET 0x0
EMMC_IRPT_MASK_ATA_ERR_BITS 29:29
CM_TDCLKEN_PLLABYP_MSB 0
CM_PLLC_HOLDCORE0_CLR 0xfffffffd
DSI1_TXPKT1_C 0x7e700004:RW
USB_DIEPINT0_TIMEOUT_BITS 3:3
PM_RSTC_QRCFG_CLR 0xffffcfff
DMA4_TI_NO_WIDE_BURSTS_BITS 26:26
USB_DIEPINT0_XFER_COMPL_RESET 0x0
DMA1_TI_WAITS_CLR 0xfc1fffff
CPG_Param1 0x7e211014:RW
DMA13_CS_DREQ_LSB 3
A2W_SMPS_L_SIA_ANA_SET 0x000003ff
HD_VID_CTL_ENABLE_CLR 0x7fffffff
A2W_PLLB_ANA_SSCS_RESET 0000000000
CM_PLLH_LOADRCAL_MSB 2
SD_DQLCRC3_FALL_SET 0x0000ffff
SD_DQLCRC1_WIDTH 32
USB_APB_ID 0x75736230
USB_DOEPCTL0_NAK_STS_RESET 0x0
A2W_PLLA_CORE_BYPEN_BITS 9:9
DMA9_DEBUG_OUTSTANDING_WRITES_MSB 7
SPI_LTOH_MASK 0x0000000f
USB_GOTGINT_SES_REQ_SUC_STS_CHG_MSB 8
USB_DOEPDMA10 0x7e980c54:RW
SH_CMD_BUSY_CMD_CLR 0xfffff7ff
USB_DOEPDMA12 0x7e980c94:RW
USB_DOEPDMA13 0x7e980cb4:RW
USB_DOEPDMA14 0x7e980cd4:RW
MPHI_AXIPRIV_RXPROT_SET 0x00000070
SD_VIN_INT_EN_BITS 28:28
EMMC_DATA_RESET 0000000000
DMA9_DEBUG_DMA_STATE_LSB 16
AVE_IN_STATUS_FRAME_RATE_DET_MSB 6
L2CACHE_SIZE (1024 * 128)
SYSAC_UC_ARBITER_CONTROL_THRESHOLD_BITS 5:4
USB_GHWCFG2_SINGLE_POINT_SET 0x00000020
CPG_Param3 0x7e21101c:RW
GP_EDS1_EDSn32_MSB 31
ASB_V3D_S_CTRL_CLR_REQ_LSB 0
I2C1_CLKT_RESET 0x00000040
SLIM_CTX_DMA (10*(1<<16))
DMA1_CS_INT_BITS 2:2
CM_PULSECTL_ENAB_BITS 4:4
HDMI_HDCP_CTL_RESET 0000000000
DMA5_DEBUG_VERSION_CLR 0xf1ffffff
USB_DIEPINT0_MASK 0xffffffff
GP_FSEL1_WIDTH 30
SPI_CLK_RESET 0000000000
DSI0_INT_EN 0x7e209028:RW
A2W_PLLA_ANA_STAT_DATA_LSB 0
A2W_PLLB_ANA_VCOR_WIDTH 1
PCM_GRAY_FLUSHED_MSB 15
CAM1_CAMIPIPE_WIDTH 32
SLIM_DMA_DC0_WIDTH 32
USB_GHWCFG3_MODE_SET 0x00000080
DMA15_DEBUG_RESET 0000000000
HDMI_RAM_PACKET_12_0 0x7e9025b0:RW
DMA12_CS_PAUSED_SET 0x00000010
CM_INTEN_FGAINB_CLR 0xfffff7ff
SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_CLR 0xfffffffc
CM_PLLA 0x7e101104:RW
CM_PLLB 0x7e101170:RW
CM_PLLC 0x7e101108:RW
CM_PLLD 0x7e10110c:RW
USB_GOTGINT_A_DEV_TOUT_CHG_LSB 18
CM_PLLH 0x7e101110:RW
DMA8_TI_BURST_LENGTH_MSB 15
L1_L1_SANDBOX_START6_START_ADDR_SET 0x3fffffe0
CM_GNRICCTL_BUSY_BITS 7:7
MPHI_C0INDCF_WIDTH 32
APERF0_BW1_WMAX 0x7e009898:RO
DMA0_STRIDE_D_STRIDE_BITS 31:16
DMA9_CS_RESET_CLR 0x7fffffff
I2C_SPI_SLV_RSR_TXDMABREQ_MSB 3
PM_PXLDO_CTRL_BITS 15:0
CM_TD1CTL_FRAC_SET 0x00000200
PWM_CTL_MODE3_SET 0x00020000
L1_IC0_PRIORITY_IC0_APRIORITY1_BITS 7:4
HDMI_RAM_PACKET_7_6_MASK 0xffffffff
UART_LSR_BI_BITS 4:4
DMA0_SOURCE_AD_S_ADDR_LSB 0
A2W_XOSC_CTRL_PLLDEN_SET 0x00000020
HDMI_RAM_PACKET_1_5_MASK 0xffffffff
USB_GHWCFG1_WIDTH 32
JMOP 0x7e005000 + 0x24:RW
DMA0_DEBUG 0x7e007020:RW
EMMC_IRPT_EN_DTO_ERR_SET 0x00100000
DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
CAM1_CAMCLK_MASK 0xffffffff
FPGA_CTRL0_CAM_CTL2_LSB 2
SD_DQLCRC5_RISE_MSB 31
USB_DIEPDMAB8_MASK 0xffffffff
A2W_SMPS_C_CTL 0x7e1022c0:RW
SH_RSP2_RESET 0000000000
USB_GGPIO_GPI_CLR 0xffff0000
DMA2_CS_ERROR_MSB 8
ASB_CPR_CTRL_CLR_REQ_BITS 0:0
DMA5_CONBLK_AD_SCB_ADDR_LSB 5
USB_DPTXFSIZ1 0x7e980104:RW
A2W_PLLD_DIG0R_RESET 0000000000
HDMI_RAM_PACKET_12_6 0x7e9025c8:RW
DMA12_CS_ABORT_CLR 0xbfffffff
USB_HCTSIZ0_PID_LSB 29
USB_GNPTXSTS_TX_Q_SPC_AVAIL_BITS 23:16
GP_FSEL3_FSEL39_LSB 27
CAM0_CAMCTL 0x7e800000:RW
I2C_SPI_SLV_CR_I2C_SET 0x00000004
EMMC_BUS_CTRL_IRQSEL_BITS 22:20
I2C_SPI_SLV_RIS 0x7e21401c:RW
USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_CLR 0xffff0000
SD_SB_COLBITS_CLR 0xfffffffc
PIXELVALVE0_DSI_HACT_ACT 0x7e206030:RW
USB_DIEPTXF1_FIFO_SIZE_LSB 16
VCE_SEMA_CLEAR_OFFSET 0x40024
DMA11_CS_INT_CLR 0xfffffffb
SMI_DSR3_RSTROBE_CLR 0xffffff80
A2W_PLLB_DIG2_WIDTH 24
A2W_XOSC_CPR_DIV_BITS 1:0
APERF1_BW2_RTWAIT 0x7ee080e0:RO
CM_DSI1PCTL_BUSY_CLR 0xffffff7f
HDMI_RAM_PACKET_12_8 0x7e9025d0:RW
GRTBCOL0 0x1A005200 + 0x0C:RW
GRTBCOL1 0x1A005220 + 0x0C:RW
GRTBCOL2 0x1A005240 + 0x0C:RW
GRTBCOL3 0x1A005260 + 0x0C:RW
GRTBCOL4 0x1A005280 + 0x0C:RW
DMA12_CS_DREQ_LSB 3
GRTBCOL6 0x1A0052C0 + 0x0C:RW
GRTBCOL7 0x1A0052E0 + 0x0C:RW
APERF1_BW0_RMAX_MASK 0x00ffffff
HDMI_READ_POINTERS_DOMAIN_RESYNC_RD_LSB 24
SD_SECSRT1_ADDR_MS_RESET 0x0
A2W_PLLC_CORE2_CHENB_LSB 8
CCP2TX_TAC_ARST_SET 0x00000001
PM_GRAFX_V3DRSTN_CLR 0xffffffbf
DPI_DPIC DPI_BASE_ADDRESS + 0x00:RW
USB_GINTMSK_NP_TXF_EMP_MSB 5
CM_SMICTL_ENAB_CLR 0xffffffef
L2_STALLS_WIDTH 32
MS_ICSET_1_RESET 0000000000
EMMC_CONTROL2_ACCRC_ERR_LSB 2
PM_AVS_RSTDR_V3D_G_LSB 3
APERF1_GEN_CTRL_ENABLE_SET 0x00000001
A2W_PLLH_DIG3_WIDTH 24
SD_VIN_SPLIT_MSB 17
AVE_IN_CTRL_ENABLE_SET 0x80000000
DMA3_DEBUG_READ_ERROR_MSB 2
DMA1_DEBUG_FIFO_ERROR_SET 0x00000002
AUX_MU_SCRATCH (0x7E215000 +0x05C)
GP_FSEL5_WIDTH 30
L1_IC0_RD_MISSES 0x7ee02044:RO
GP_HEN1_RESET 0000000000
USB_DIEPINT0_STS_PHSE_RCVD_CLR 0xffffffdf
HDMI_CPU_MASK_CLEAR 0x7e902354:RW
HD_MAI_CTL_DLATE_CLR 0xffff7fff
USB_DIEPINT0_AHB_ERR_RESET 0x0
SH_RSP2_CID_CSD_BITS 31:0
DSI0_HSTX_TO_C_MASK 0x00ffffff
CM_DPIDIV_MASK 0x0000fff0
CM_PLLB_ANARST_CLR 0xfffffeff
DMA6_CS_PANIC_PRIORITY_MSB 23
HD_MAI_THR_DREQHIGH_CLR 0xffffc0ff
GP_SET1_SETn32_SET 0xffffffff
UART_MSR_TERI_LSB 2
CM_CAM1CTL_MASK 0x000003bf
DMA8_CS_DREQ_STOPS_DMA_SET 0x00000020
PM_AVS_INTEN_ALERT_H264_I_LSB 2
SMI_BASE 0x7e600000
PM_PADS3_HYST_BITS 3:3
USB_GOTGINT_DBNCE_DONE_CLR 0xfff7ffff
HD_MAI_CTL_WHOLSMP_MSB 12
EMMC_IRPT_EN_DMA_LSB 3
SD_SECSRT3_ADDR_LS_SET 0x00001ffe
USB_DPTXFSIZ9 0x7e980124:RW
USB_GINTMSK_INCOMPL_P_SET 0x00200000
IC0_MASK0 0x7e002010:RW
L1_IC0_RAS_UNDERFLOW_MASK 0000000000
TS_TSENSCTL_PRWDW_BITS 0:0
EMMC_DMA_STATUS_ERR_AT_CLR 0xfffffffc
SLIM_DMA_DC_STAT_0_WIDTH 32
CM_LOCK_LOCKA_MSB 0
HDMI_VERTA1_MANUAL_VAL1_BITS 12:0
AVE_IN_STATUS_BUF0_COMPL_SET 0x00000002
SD_DQRCRC7_RISE_MSB 31
MPHI_INTSTAT_OMFUFLW_BITS 28:28
DMA6_CS_MASK 0xf0ff017f
DMA7_TI_SRC_WIDTH_LSB 9
MPHI_OUTDS_MASK 0x5fffffff
IMASK0 0x7e002010:RW
IMASK1 0x7e002014:RW
IMASK2 0x7e002018:RW
IMASK3 0x7e00201c:RW
A2W_PLLD_ANA_VCO_RESET 0000000000
CM_CAM1CTL_FRAC_BITS 9:9
I2C_SPI_SLV_FR_RXFE_MSB 1
MS_SEMA_10_RESET 0000000000
MS_SEMA_1_WIDTH 1
USB_HCCHAR0 0x7e980500:RW
DISP_DMA (0*(1<<16))
HDMI_FIFO_CTL_USE_EMPTY_MSB 13
PM_PADS0_POWOK_MSB 5
HDMI_DETECTED_VERTA1_MANUAL_VFP1_LSB 13
DSI0_CMD_DATAF_WIDTH 8
CM_TCNTCTL_KILL_LSB 6
SPI_CS_RXF_BITS 20:20
USB_HCCHAR1 0x7e980520:RW
DMA12_TI_PERMAP_SET 0x001f0000
SPI_DLEN_LEN_MSB 15
OTP_HDCP_AES_KEY_ROW_REDUNDANT ((((((((((((8 +4)+4)+1)+1)+1)+4)+4)+1)+4)+4)+1)+4)
A2W_PLLD_PER_RESET 0x00000100
SMIDC_REQW 0
CM_TDCLKEN_PLLCDIV2_MSB 6
USB_HCCHAR2 0x7e980540:RW
EMMC_IRPT_EN_SDOFF_ERR_SET 0x00800000
PCM_MODE_A_PDME_BITS 26:26
USB_HPRT_RST_LSB 8
PIXELVALVE2_VC 0x7e807004:RW
TXP_CTRL_ALPHA_INVERT_SET 0x00001000
USB_HCCHAR3 0x7e980560:RW
PWM_CTL_USEF2_LSB 13
SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_SET 0x000000c0
MS_IREQ_0 0x7e000084:RW
SLIM_CON_MASK 0xfffff0ff
HDMI_PACKET_FIFO_CTL 0x7e90211c:RW
CM_EVENT_FGAINC_BITS 12:12
DSI0_HS_DLT4 0x7e209054:RW
DSI0_HS_DLT5 0x7e209058:RW
USB_HCCHAR4 0x7e980580:RW
A2W_SMPS_L_SPA_ANA_SET 0x000003ff
MS_SEMA_5_MASK_LSB 0
DMA15_TI_DEST_DREQ_SET 0x00000040
USB_DIEPTXF2_WIDTH 32
SMI_DC_DMAEN_MSB 28
FPGA_DCM_RD_DATA_WIDTH 16
PCM_CS_A_RXSYNC_BITS 14:14
EMMC_BOOT_TIMEOUT_TIMEOUT_MSB 31
GP_FSEL1_FSEL11_MSB 5
USB_GRSTCTL_DMA_REQ_RESET 0x0
A2W_PLLB_CTRL_PWRDN_SET 0x00010000
HDMI_VERTA1_MANUAL_VAL1_LSB 0
DMA2_CS_DREQ_STOPS_DMA_SET 0x00000020
CAM0_CAMIDCD_WIDTH 32
GP_FSEL3_FSEL32_CLR 0xfffffe3f
DMA9_CS_DREQ_BITS 3:3
HDMI_PERT_LFSR_PRELOAD_MASK 0xffffffff
USB_DOEPTSIZ0_PKT_CNT_BITS 28:19
USB_DCTL_PWRON_PRG_DONE_MSB 11
DMA1_DEBUG_DMA_ID_CLR 0xffff00ff
CM_PLLB_RESET 0x00000300
SD_PRE_MASK 0x0fffffff
CM_TDCLKEN_PLLCBYP_SET 0x00000004
SCALER_DISPSTAT_DMA_IRQ_BITS 31:4
DMA9_DEST_AD_D_ADDR_MSB 31
MS_ICCLR_1_WIDTH 1
DMA15_TI_SRC_DREQ_MSB 10
USB_HCTSIZ1_MASK 0xffffffff
SYSAC_DMA_ARBITER_CONTROL_UC 0x7e009050:RW
A2W_XOSC1_WIDTH 24
CM_VPUDIV_DIV_LSB 4
HDMI_PACKET_FIFO_CTL_MASK 0x00000003
EMMC_FORCE_IRPT_DMA_ERR_BITS 28:28
A2W_PLLH_RCAL_CHENB_MSB 8
CM_PLLB_LOADARM_SET 0x00000001
A2W_PLLA_ANA_KAIP_KI_LSB 4
PM_CAM0_LDOCTRL_CLR 0xffe00007
DMA4_TI_SRC_IGNORE_LSB 11
SD_DQLCRC7_RISE_RESET 0x0
CPG_Config 0x7e211000:RW
USB_DIEPDMAB6_WIDTH 32
ARM_DS_ACTIVE 0x00000004
CAM1_CAMDCS 0x7e801200:RW
SLIM_DCC7_PA1_WIDTH 24
APERF1_BW0_RTRANS_WIDTH 32
MS_SEMA_14_MASK 0x00000001
HDMI_CPU_MASK_STATUS_MASK 0xffffffff
CM_EVENT_BURSTDONE_BITS 23:23
HDMI_PCI_SET (HDMI_BASE_ADDRESS + 0x340) + 0x1c:RW
SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_LSB 6
SYSAC_HOST_PRIORITY 0x7e009000:RW
EMMC_BOOT_TIMEOUT_RESET 0000000000
SD_RWC_RXVAL_LSB 0
SD_DQRCRC15_WIDTH 32
ASB_V3D_S_CTRL_WCOUNT_CLR 0xff003fff
USB_GHWCFG3_PACKET_COUNT_WIDTH_MSB 6
SCALER_DISPCTRL_MASK 0xffffffff
HDMI_KSV_FIFO_1_WIDTH 8
PM_GRAFX_CFG_BITS 22:16
EMMC_HWCAP0_SLOT_TYPE_SET 0xc0000000
GP_FSEL2_FSEL21_SET 0x00000038
DMA3_TI_BURST_LENGTH_CLR 0xffff0fff
USB_DOEPCTL0_USB_ACT_EP_LSB 15
DMA15_STRIDE_WIDTH 32
FPGA_MB_CORE_CLK_FREQ_WIDTH 32
MPHI_C0INDDB_LENGTH_BITS 19:0
ARM_2_BELL1 (0x7E00B000 +0xA00)+0x44:RW
SD_CS_EXCEPTION_BITS 23:23
PM_RSTS_HADDRQ_MSB 0
CM_SDCCTL_ACCPT_CLR 0xfffeffff
SD_SD_WIDTH 32
DSI1_TXPKT1_H_WIDTH 32
HDMI_DETECTED_VERTA0_MANUAL_VFP0_LSB 13
DMA4_CS_DREQ_STOPS_DMA_BITS 5:5
MS_SEMA_21_MASK 0x00000001
ASB_AXI_BRDG_VERSION_RESET 0000000000
MULTICORE_SYNC_SEMA_MASK(num) MACRO
PCM_CS_A_RXTHR_SET 0x00000180
PM_PROC_POWUP_MSB 0
EMMC_ARG1 0x7e300008:RW
HDMI_RAM_PACKET_10_5_RESET 0000000000
DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
DMA13_DEST_AD_WIDTH 32
CM_SLIMDIV_DIV_CLR 0xff000000
PM_XOSC_USESEC_BITS 0:0
DMA0_TI_DEST_IGNORE_CLR 0xffffff7f
CM_DSI1ECTL_WIDTH 10
A2W_SMPS_C_CLKR_MASK 0x0000000f
DMA9_TI_DEST_DREQ_MSB 6
CCP2TX_TBA_WIDTH 30
DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
SMI_CS_RXR_BITS 27:27
APERF0_BW2_ATWAIT 0x7e0098c8:RO
CM_PWMCTL_BUSY_SET 0x00000080
DMA9_DEST_AD_WIDTH 32
PM_PXLDO_CTRL_CLR 0xffff0000
HDMI_DETECTED_VERTA1_MANUAL_VAL1_SET 0x00001fff
PM_PADS3_HYST_CLR 0xfffffff7
USB_DOEPINT0_IN_TKN_EP_MIS_MSB 5
CMI_CAM1_RX2SRC_LSB 6
EMMC_CONTROL0_HCTL_DWIDTH_CLR 0xfffffffd
USB_DIEPEMPMSK_WIDTH 16
SPICS SPI_BASE_ADDRESS + 0x00:RW
DSI0_HS_CLT0_WIDTH 32
SH_RSP0_WIDTH 32
HDMI_RAM_PACKET_11_3_WIDTH 32
DMA14_CS_END_MSB 1
CM_PCMCTL_ENAB_SET 0x00000010
A2W_PLLA_DIG1_RESET 0x00004000
DMA11_TI_SRC_INC_SET 0x00000100
SMI_CS_PXLDAT_CLR 0xffffbfff
FPGA_DCM_CTRL_REMOTE_RST_BITS 4:0
CM_VPUCTL_WIDTH 10
DMA12_TI_DEST_IGNORE_CLR 0xffffff7f
AJBCONF 0x7e2000c0 +0x00:RW
CM_TD1CTL_SRC_MSB 3
DMA2_CS_RESET_BITS 31:31
SH_TOUT_TIME_OUT_LSB 0
MPHI_C0INDCF_LENERR_CLR 0xbfffffff
SDDELS1 SD_DELS1
SDDELS2 SD_DELS2
SDDELS3 SD_DELS3
DMA7_CS_INT_CLR 0xfffffffb
A2W_PLLB_ANA_SSCSR 0x7e1029f0:RW
SMI_CS_TXW_LSB 26
CM_INTEN_A2WDONE_MSB 20
CM_VPUCTL_BUSY_MSB 7
EMMC_IRPT_EN_CBAD_ERR_LSB 19
CCP2TX_TPC_TPP_CLR 0xffffff0f
SD_MR_RDATA_CLR 0xff00ffff
L2_WR_MISSES_MASK 0xffffffff
SMI_CS_START_SET 0x00000008
DMA1_CS_ABORT_BITS 30:30
ARM_C0_BRESP0 0x00000000
ARM_C0_BRESP1 0x00000004
ARM_C0_BRESP2 0x00000008
SD_SC_T_WTR_MSB 6
DMA10_NEXTCONBK_ADDR_CLR 0x0000001f
DMA5_TI_INTEN_SET 0x00000001
L1_L1_SANDBOX_END6_MASK 0x3fffffe0
CM_EVENT_GAIND_CLR 0xfffffff7
TXP_CTRL_PILOT_LSB 24
USB_DCTL_SGOUT_NAK_BITS 9:9
SD_RAC 0x7ee0002c:RO
PM_PADS6_PD_SET 0x00000100
DMA15_DEBUG_FIFO_ERROR_MSB 1
CSI2_DTOV0 CSI2_BASE_ADDRESS + 0x12C:RW
CSI2_DTOV1 CSI2_BASE_ADDRESS + 0x22C:RW
APERF0_BW2_WTRANS 0x7e0098d0:RO
SCALER_OLEDCOEF0 0x7e400084:RW
SCALER_OLEDCOEF1 0x7e400088:RW
SCALER_OLEDCOEF2 0x7e40008c:RW
A2W_SMPS_CTLA0R_MASK 0x00ffffff
HDMI_RAM_PACKET_8_7_WIDTH 32
SD_CS_ASHDN_T_MSB 22
A2W_XOSC_PWR_BYPASS_LSB 0
SD_SECSRT0_ADDR_LS_LSB 1
L1_D_PRIORITY_MASK 0x0fff0fff
CSI2_RDSA_x(x) MACRO
L1_IC0_BP_HITS 0x7ee02048:RO
A2W_PLLD_ANA2R_RESET 0000000000
CM_PCMCTL_MASK 0x000007bf
USB_DOEPCTL0_SET_EVEN_FR_SET 0x10000000
A2W_SMPS_L_SPA_WIDTH 10
PWM_CTL_POLA4_BITS 28:28
SPI_FIFO_WIDTH 8
A2W_PLLD_DSI1_CHENB_SET 0x00000100
DMA5_TI_SRC_WIDTH_BITS 9:9
I2C_SPI_SLV_FR_MASK 0x0000ffff
I2C_SPI_SLV_CR_BRK_CLR 0xffffff7f
L1_IC0_FLUSH_E 0x7ee0200c:RW
CM_PLLH_LOADPIX_LSB 0
USB_DIEPDMAB15_WIDTH 32
UART_MSR_RI_BITS 6:6
CSI2DBGMISC CSI2_BASE_ADDRESS + 0x84:RW
DMA11_DEBUG_DMA_ID_CLR 0xffff00ff
L1_IC0_FLUSH_S 0x7ee02008:RW
USB_HFNUM_REM_RESET 0x0
EMMC_CONTROL0 0x7e300028:RW
DMA10_TI_SRC_WIDTH_BITS 9:9
CM_GNRICDIV_DIV_MSB 23
SPI_FIFO 0x7e204004:RW
SD_SF_POWSAV_T_LSB 9
EMMC_CONTROL1 0x7e30002c:RW
UNICAM_DAT0(x) MACRO
UNICAM_DAT1(x) MACRO
UNICAM_DAT2(x) MACRO
UNICAM_DAT3(x) MACRO
SLIM_DMA_DC_CON_WIDTH 20
HD_HDM_CTL_ENABLE_SET 0x00000001
DMA3_CS_DREQ_BITS 3:3
HD_CSC_CTL_COLORD_RESET 0x0
EMMC_CONTROL2 0x7e30003c:RW
EMMC_FORCE_IRPT_TUNE_ERR_BITS 26:26
EMMC_CONTROL2_ACBAD_ERR_MSB 4
DMA3_TI_SRC_IGNORE_MSB 11
A2W_PLLH_ANA_KAIP_KI_BITS 6:4
USB_GHWCFG2_HSPHY_INTERFACE_SET 0x000000c0
USB_GUSBCFG_TERM_SEL_DL_PULSE_MSB 22
CM_EMMCCTL_BUSY_LSB 7
SCALER_DISPGAMDAT 0x7e4000e0:RW
PWM_CTL_MASK 0xbfbfbfff
VEC_CGMSAE_RESET_WIDTH 32
GP_REN0 0x7e20004c:RW
GP_REN1 0x7e200050:RW
GP_REN2 0x7e200054:RW
SMI_DSW1_WSETUP_MSB 29
SD_SECSRT2_ADDR_MS_CLR 0x00001fff
EMMC_IRPT_MASK_OEM_ERR_CLR 0x3fffffff
GROCFG 0x1A005000 + 4:RW
GP_AFEN0_MASK 0xffffffff
USB_GINTMSK_ISO_OUT_DROP_RESET 0x0
DMA12_CS_ACTIVE_BITS 0:0
DMA6_CS_ABORT_CLR 0xbfffffff
CM_SDCDIV_DIV_LSB 12
UART_LCR_STB_SET 0x00000004
SH_DATA_DATA_LSB 0
L1_IC0_BP_HITS_WIDTH 0
USB_GNPTXFSIZ_IN_EP_TXF0_DEP_RESET 0x0
SLIM_DCC1_PROT_MASK 0xc001ffff
CMPCM 0x7C:RW
A2W_PLLC_ANA_VCOR_WIDTH 1
AVE_OUT_STATUS_PXL_FORMAT_ERROR_BITS 0:0
SD_DQLCRC4_RISE_RESET 0x0
PM_DSI0_LDOHPEN_BITS 2:2
SD_RDC 0x7ee00024:RO
V3D_PCTRS9_WIDTH 5
GP_FSEL0_MASK 0x3fffffff
UART_LSR_BI_CLR 0xffffffef
MS_SEMA_20_WIDTH 1
HDMI_RAM_PACKET_2_1 0x7e90244c:RW
HDMI_RAM_PACKET_2_2 0x7e902450:RW
HDMI_RAM_PACKET_2_3 0x7e902454:RW
HDMI_RAM_PACKET_2_4 0x7e902458:RW
HDMI_RAM_PACKET_2_5 0x7e90245c:RW
HDMI_RAM_PACKET_2_6 0x7e902460:RW
HDMI_RAM_PACKET_2_7 0x7e902464:RW
HDMI_RAM_PACKET_2_8 0x7e902468:RW
SCALER_DISPGAMADR_MASK 0xffffffff
A2W_PLLH_ANA_STATR 0x7e102e60:RW
V3D_DBQHLT 0x7ec00000 +0x0e24:RW
DMA15_DEBUG_LITE_SET 0x10000000
EMMC_IRPT_MASK_DMA_BITS 3:3
I2C_SPI_SLV_DEBUG2_DATA_MSB 23
A2W_PLLA_ANA_SSCLR_RESET 0000000000
DMA3_TI_DEST_INC_BITS 4:4
A2W_PLLH_CTRLR_MASK 0x000370ff
PIXELVALVE0_VERTA_WIDTH 32
CM_PCMCTL_KILL_CLR 0xffffffdf
A2W_PLLD_PER_BYPEN_LSB 9
L1_IC0_PRIORITY_IC0_APRIORITY1_MSB 7
DMA4_TI_DEST_IGNORE_BITS 7:7
I2C2_A_RESET 0000000000
UART_LSR_PE_SET 0x00000004
USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_LSB 5
APERF1_BW1_ATRANS_RESET 0000000000
CM_HSMCTL_MASK 0x000003ff
ASB_H264_S_CTRL_WCOUNT_CLR 0xff003fff
CM_SYSDIV_DIV_CLR 0xffffefff
UNICAM_IBEA0(x) MACRO
UNICAM_IBEA1(x) MACRO
V3D_PCTR14_MASK 0xffffffff
AVE_OUT_STATUS_PXL_OUTPUT_ERROR_SET 0x00000002
CAM1_CAMIDI1_MASK 0xffffffff
CM_SDCCTL_UPDATE_CLR 0xfffdffff
SLIM_FS_WIDTH 14
TB_BOOT_OPT_DONT_SET_VPU_CLK_SET 0x00000400
A2W_PLLC_ANA1_RESET 0x001d0000
VEC_CGMSAE_TOP_CONTROL_MASK 0xffffffff
GROPCTR_TU1_SAME_SET_STALL 0x16
DMA15_CONBLK_AD_SCB_ADDR_MSB 31
FPGA_CTRL0_TV_ACTIVITY_BITS 13:13
USB_DAINTMSK_MASK 0xffffffff
CM_PWMDIV_DIV_LSB 0
USB_DOEPCTL0_NEXT_EP_MSB 14
A2W_SMPS_C_CTLR_MASK 0x00000003
USB_GOTGINT_SES_REQ_SUC_STS_CHG_RESET 0x0
USB_HCINTMSK6_WIDTH 32
EMMC_BASE 0x7e300000
EMMC_IRPT_EN_TUNE_ERR_CLR 0xfbffffff
USB_HCINT0_XACT_ERR_RESET 0x0
DMA14_CS_PRIORITY_SET 0x000f0000
USB_DOEPDMAB0 0x7e980b1c:RW
USB_DOEPDMAB1 0x7e980b1c:RW
USB_DOEPDMAB2 0x7e980b1c:RW
USB_DOEPDMAB3 0x7e980b1c:RW
USB_DOEPDMAB4 0x7e980b1c:RW
USB_DOEPDMAB5 0x7e980b1c:RW
USB_DOEPDMAB6 0x7e980b1c:RW
USB_DOEPDMAB7 0x7e980b1c:RW
USB_DOEPDMAB8 0x7e980b1c:RW
USB_DOEPDMAB9 0x7e980b1c:RW
UART_MSR_DCD_CLR 0xffffff7f
CAM1_CAMDLT 0x7e801028:RW
SMI_CS_ACTIVE_BITS 2:2
TB_BOOT_OPT_DONT_SET_VPU_CLK_MSB 10
EMMC_IRPT_EN_ATA_ERR_CLR 0xdfffffff
AJBTDI 0x7e2000c0 +0x08:RW
SLIM_DCC6_STAT 0x7e2102cc:RW
CM_OSCFREQF_WIDTH 20
USB_HPRT_ENA_CLR 0xfffffffb
PM_RSTS_HADWRQ_LSB 4
USB_GUSBCFG_TERM_SEL_DL_PULSE_BITS 22:22
HDMI_MBIST_TM 0x7e9020e0:RW
CM_TCNTCNT_RESET 0000000000
PCM_TXC_A_CH1EN_LSB 30
EMMC_IRPT_EN_INT_C_BITS 11:11
PWM_CTL_MODE4_LSB 25
I2C_SPI_SLV_CR_TXE_LSB 8
SMI_CS_SETERR_MSB 13
ARM_3_SEM3 (0x7E00B000 +0xB00)+0x0C:RW
L1_L1_SANDBOX_START4_WIDTH 30
PCM_TXC_A_CH2WEX_BITS 15:15
A2W_PLLB_CTRL_NDIV_BITS 9:0
CM_VECCTL_ENAB_CLR 0xffffffef
CM_SDCCTL_FRAC_CLR 0xfffffdff
PM_AUDIO_CTRLEN_LSB 20
V3D_CT0CA_MASK 0xffffffff
CM_EVENT_GAINC_BITS 2:2
PRMCS 0x7e20d000 + 0x00:RW
DMA5_CS_ACTIVE_BITS 0:0
CPG_Param2_WIDTH 32
PRMCV 0x7e20d000 + 0x04:RW
MPHI_C1INDCF_EMPTY_CLR 0x7fffffff
CM_SMICTL_FRAC_SET 0x00000200
DMA4_CS_INT_CLR 0xfffffffb
DMA13_TXFR_LEN_XLENGTH_LSB 0
SMI_CS 0x7e600000:RW
PM_CAM0_LDOHPEN_MSB 2
CM_PLLTCNT3_CNT_SET 0x00ffffff
SD_TMC_IPRD_MSB 15
EMMC_CONTROL2_EN_AINT_MSB 30
CCP2TX_TAC_TPC_CLR 0xfffffff7
EMMC_IRPT_MASK_CBAD_ERR_CLR 0xfff7ffff
FPGA_MB_XSLC1_BUILD_NUM_WIDTH 32
EMMC_IRPT_MASK_CTO_ERR_BITS 16:16
DMA15_CS_INT_MSB 2
DMA10_CS_PANIC_PRIORITY_BITS 23:20
AVE_IN_CURRENT_ADDRESS_MASK 0xffffffff
V3D_SRQCS_MASK 0x00ffffbf
USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_BITS 5:5
PWMDMAC_PANIC_LEN 8
USB_HPRT_CONN_STS_SET 0x00000001
DMA5_DEBUG_DMA_ID_BITS 15:8
SD_DQRCRC0_FALL_MSB 15
SCALER_DISPID 0x7e400008:RW
CM_CAM0CTL_ENAB_MSB 4
SMIDS_FSETUP 22
SD_DQLCRC13_FALL_SET 0x0000ffff
DMA9_DEBUG_LITE_LSB 28
PRM_SCC_WIDTH 32
DMA14_CS_DISDEBUG_LSB 29
MPHI_C1INDCF_ORUN_CLR 0xdfffffff
APERF0_BW2_CTRL_EN_LSB 30
PM_PADS6_PD_LSB 8
DMA_TI_NO_WIDE_BURSTS (1<<26)
MS_SEMA_30_MASK_MSB 0
HDMI_READ_POINTERS_DOMAIN_RESYNC_RD_CLR 0xf8ffffff
USB_DOEPINT12_WIDTH 32
CM_DPICTL_BUSYD_LSB 8
DMA14_CS_MASK 0xf0ff017f
HDCP_KEY_CTL_DISHDCP_LSB 2
HD_VID_CTL_WIDTH 32
SD_DQLCRC6_RISE_BITS 31:16
USB_DPTXFSIZ10 0x7e980128:RW
USB_HCINT0_XFER_COMPL_MSB 0
EMMC_HWCAP0_V3_0_MSB 25
USB_GPVNDCTL_DIS_ULPI_DRVR_SET 0x80000000
TB_TASK_TEXT_FLAG_SET 0x00010000
CAM0_CAMANA_MASK 0xffffffff
USB_GRXSTSP_DEV_BCNT_SET 0x00007ff0
DMA4_NEXTCONBK_ADDR_BITS 31:5
DMA14_CS_INT_BITS 2:2
DMA4_DEBUG_FIFO_ERROR_SET 0x00000002
SLIM_DCC3_CON 0x7e210268:RW
PCM_INTSTC_A_TXERR_BITS 2:2
CM_DPICTL_FRAC_LSB 9
A2W_PLLD_ANA_KAIP_KA_SET 0x00000700
TB_JTB_TDI 0x7e20b808:RW
I2C1_DIV_WIDTH 16
MS_SEMA_14_MASK_MSB 0
TB_JTB_TDO 0x7e20b80c:RO
USB_HPTXSTS_HPTXQTOP_BITS 31:24
CM_TD0CTL_GATE_CLR 0xffffffbf
DMA11_DEBUG_DMA_ID_SET 0x0000ff00
HDMI_READ_POINTERS_DRFT_HOLD_RD_LSB 22
USB_DPTXFSIZ13 0x7e980134:RW
AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_LSB 0
JP_CTRL 0x7e005000:RW
MS_SEMA_20_MASK_LSB 0
CM_TD0CTL_GATE_BITS 6:6
I2C_SPI_SLV_FR_RXFE_CLR 0xfffffffd
GROPCTR_PBE_DPTH_STCL_PASS 0x21
SLIM_DMA_DC0_RESET 0000000000
SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_BITS 15:8
GP_FSEL2_FSEL26_MSB 20
USB_DPTXFSIZ14 0x7e980138:RW
GP_AREN1_ARENn32_CLR 0x00000000
SD_DQRCRC1_RISE_CLR 0x0000ffff
CCP2TX_TDL_MASK 0x3fffffff
ASB_CPR_CTRL_FULL_MSB 3
GP_FSEL4_FSEL47_CLR 0xff1fffff
V3D_DBSSR 0x7ec00000 +0x0e0c:RW
USB_DIEPINT0_STS_PHSE_RCVD_BITS 5:5
USB_DIEPINT0_IN_TKN_TXFEMP_RESET 0x0
A2W_XOSC_CTRL_SMPSEN_BITS 3:3
PM_PADS0_POWOK_BITS 5:5
USB_DOEPDMA8_WIDTH 32
GP_FSEL3_FSEL37_SET 0x00e00000
SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_BITS 1:0
MPHI_CTRL_INVERT_LSB 8
DMA14_CS_PAUSED_CLR 0xffffffef
A2W_PASSWORD 0x5a000000
CM_EVENT_FLOSSC_BITS 16:16
ASB_V3D_M_CTRL_WCOUNT_SET 0x00ffc000
SCALER_DISPID_MASK 0xffffffff
USB_HCINT0_BBL_ERR_BITS 8:8
CCP2TX_TS_TQI_MSB 19
SMIDS_DREQ 7
MPHI_HSINDFS_CFIFOLVL_RESET 0x0
PCM_INTSTC_A_RXR_LSB 1
USB_GAHBCFG_NP_TXF_EMP_LVL_BITS 7:7
I2C_SPI_SLV_FR_TXFLEVEL_LSB 10
DMA13_TI_DEST_INC_BITS 4:4
DMA7_SOURCE_AD_S_ADDR_MSB 31
DMA10_DEBUG_OUTSTANDING_WRITES_LSB 4
CM_DSI0ECTL_MASK 0x000003bf
MPHI_OUTDFS_DFIFOLVL_MSB 15
TS_TSENSSTAT_RESET 0000000000
SD_DQLCRC1_RISE_RESET 0x0
MS_MBOX_3_MASK 0xffffffff
MS_SEMA_22_RESET 0000000000
CM_CCP2DIV 0x7e101054:RO
SCALER_DISPECTRL_PROF_TYPE_MSB 27
HDMI_SCHEDULER_CONTROL_ALWS_REKEY_KEEPOUT_BITS 4:4
DMA3_CS_PRIORITY_BITS 19:16
A2W_XOSC_CTRL_SMPSEN_LSB 3
DMA3_TI_INTEN_LSB 0
FPGA_DCM_RD_DATA_DATA_CLR 0xffff0000
SMICS_WRITE 5
PIXELVALVE2_VERTA_EVEN_WIDTH 32
ARM_3_BELLCLRDBG (0x7E00B000 +0xB00)+0xE4:RW
DMA4_TI_WIDTH 27
CM_PULSECTL_FRAC_LSB 9
USB_HCDMA2_WIDTH 32
CM_HSMCTL_GATE_LSB 6
CM_SDCCTL_BUSYD_CLR 0xfffffeff
PCM_RXC_A_CH1WID_LSB 16
AVE_OUT_CR_COEFF_RED_COEFF_MSB 29
GP_FSEL3_FSEL36_SET 0x001c0000
SCALER_DISPSTAT_RD_IRQ_LSB 6
SD_DQLCRC15_WIDTH 32
HDMI_RAM_PACKET_6_4_WIDTH 32
SMI_CS_AFERR_CLR 0xfdffffff
CM_PLLC_HOLDPER_BITS 7:7
CM_TD1CTL_RESET 0000000000
DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
USB_HCINT6_MASK 0xffffffff
MS_SEMA_18_MASK_BITS 0:0
EMMC_FORCE_IRPT_ACMD_ERR_LSB 24
USB_DIEPTSIZ0_MC_BITS 30:29
SYSAC_DUMMY_STATUS_IDLE_RESET 0x0
GR_PPL_DEBUG_BASE 0x1A005740
SLIM_DCC2_STAT_MASK 0xc0ff00c7
SCALER_DISPECTRL_CR_BUSY_LSB 11
PCM_TXC_A_CH2WID_BITS 3:0
HDMI_CORE_REV_WIDTH 16
L1_D0_WBACKS 0x7ee02160:RO
I2C2_S_MASK 0xffffffff
EMMC_DBG_SEL_SELECT_BITS 0:0
A2W_PLLC_ANA_VCO_RANGE_BITS 0:0
URBR 0x7e201000 + 0x00:RO
EMMC_STATUS_CMD_LEVEL_SET 0x01000000
HDMI_RAM_PACKET_2_6_WIDTH 32
EMMC_INTERRUPT_ENDBOOT_LSB 14
CM_EMMCDIV_DIV_LSB 4
SD_DQLCRC5_FALL_MSB 15
SH_EDM_WRITE_THRESHOLD_CLR 0xffffc1ff
MPHI_C1INDCF_LENERR_CLR 0xbfffffff
DMA0_CS_PAUSED_LSB 4
CM_SLIMDIV_WIDTH 24
CM_CAM0CTL_KILL_CLR 0xffffffdf
I2C_SPI_SLV_CR_BRK_SET 0x00000080
USB_GAHBCFG_DMA_EN_SET 0x00000020
DSI0_HS_DLT4_MASK 0x000003fc
A2W_PLLA_DIG3R_WIDTH 24
A2W_PLLB_ANA_KAIP_KP_CLR 0xfffffff0
GR_VCACHE_ADDR_MASK 0x00001fff
SD_SA_PGEHLD_IDL_SET 0x00008000
VEC_CPS45_CPS67_WIDTH 32
SH_HBCT_BYTECOUNT_BITS 31:0
L1_D_CONTROL_DC_DISABLE_CLR 0xfffffffe
USB_HCSPLT0_PRT_ADDR_LSB 0
SH_CMD_READ_CMD_BITS 6:6
MPHI_RXAXICFG_RXNPRIO_MSB 3
A2W_PLLB_ANA_VCO_RANGE_LSB 0
HDMI_RAM_PACKET_8_1_RESET 0000000000
APERF0_BW1_CTRL_ID_EN_SET 0x20000000
APERF0_BW2_RMAX_MASK 0x00ffffff
HDMI_FIFO_CTL_CAPTURE_POINTER_MSB 2
CM_EMMCCTL 0x7e1011c0:RW
HDMI_SCHEDULER_CONTROL_USE_POSTLN_AVOID_BITS 14:14
DMA8_CS_END_BITS 1:1
DMA11_CS_DREQ_CLR 0xfffffff7
HDMI_PERT_LFSR_FEEDBACK_MASK_WIDTH 32
DMA12_TI_WIDTH 26
CM_CAM0CTL_SRC_BITS 3:0
DSI0_PHYC_dlane_hsen_1_sync_SET 0x00000020
DMA9_CS_DREQ_SET 0x00000008
EMMC_CONTROL2_EN_PSV_LSB 31
SMI_DSW3_WPACE_LSB 8
USB_DIEPTXF13_WIDTH 32
DMA15_BASE 0x7ee05000
HDMI_RAM_PACKET_12_3 0x7e9025bc:RW
DMA8_TI_WAITS_MSB 25
DMA2_CS_DREQ_STOPS_DMA_LSB 5
DMA11_SOURCE_AD_S_ADDR_BITS 31:0
DMA10_CS_PANIC_PRIORITY_SET 0x00f00000
HDMI_RAM_PACKET_4_3_RESET 0000000000
USB_DIEPDMA12_MASK 0xffffffff
DMA14_TI_SRC_IGNORE_SET 0x00000800
DMA1_CS_INT_CLR 0xfffffffb
DMA10_SOURCE_AD 0x7e007a0c:RO
GP_FSEL2_FSEL22_LSB 6
DMA8_BASE 0x7e007800
SH_RSP1_CID_CSD_SET 0xffffffff
PCM_RXC_A_CH1WEX_SET 0x80000000
SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_LSB 0
L1_L1_SANDBOX_END5_WIDTH 30
FPGA_CTRL0_SW_SPI_SDA_O_MSB 7
PM_IMAGE_ENAB_SET 0x00001000
HDMI_DETECTED_HORZA_RESET 0x00000280
SD_DQLCRC6_RISE_CLR 0x0000ffff
DMA0_SOURCE_AD 0x7e00700c:RO
DMA12_CS_INT_MSB 2
IC0_FORCE0_RESET 0000000000
SD_DQLCRC8_RISE_BITS 31:16
DMA6_CS_ACTIVE_MSB 0
EMMC_INTERRUPT_CTO_ERR_SET 0x00010000
APERF0_BW0_RTWAIT_MASK 0xffffffff
V3D_CT01RA0_MASK 0xffffffff
SLIM_DMA_DC9_MASK 0xffffffff
HDMI_CEC_TX_DATA_4_MASK 0xffffffff
I2C_SPI_SLV_RSR_TXDMABREQ_BITS 3:3
AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_CLR 0xfffff000
DMA14_TI_PERMAP_CLR 0xffe0ffff
CM_ARMDIV_DIV_BITS 12:12
DSI0_PR_TO_CNT_WIDTH 32
SD_SECSRT3_ADDR_MS_BITS 31:13
A2W_HDMI_CTL_RCAL_SELAVG_MSB 1
USB_DOEPCTL0_ENA_CLR 0x7fffffff
PCM_MODE_A_FRXP_SET 0x02000000
USB_GI2CCTL_ADDR_RESET 0x0
CM_V3DCTL_FRAC_LSB 9
EMMC_BUS_CTRL_CLK_PINS_MSB 2
SD_DQRCRC7_FALL_MSB 15
SMI_DSW0_WSTROBE_SET 0x0000007f
USB_GRXFSIZ_GRXF_DEP_BITS 15:0
APERF1_BW0_ATRANS 0x7ee08044:RO
DMA1_CS_ERROR_BITS 8:8
AJBTMS 0x7e2000c0 +0x04:RW
MPHI_TXAXICFG_TXPPRIO_SET 0x000000f0
AVE_OUT_CTRL_INVERT_EVEN_FIELD_CLR 0xfffeffff
SMI_CS_PXLDAT_BITS 14:14
CM_TD0CTL_FLIP_SET 0x00000800
CCP2TX_TPC_TPT_SET 0x0000ff00
A2W_PLLB_ANA_SCTL_SEL_SET 0x00000007
CM_PLLC_ANARST_MSB 8
DMA5_STRIDE_D_STRIDE_CLR 0x0000ffff
HDCP_KEY_CTL_DISHDCP_SET 0x00000004
GRMCIL0 0x1A005C80 + 0x00:RW
PCM_WIDTH1(x) MACRO
PCM_WIDTH2(x) MACRO
CM_SDCCTL_ACCPT_BITS 16:16
MPHI_C1INDDA_START_SET 0xffffffff
A2W_PLLD_ANA_KAIP_WIDTH 11
USB_GNPTXFSIZ_NP_TXF_ST_ADDR_LSB 0
DSI1_HS_CLT1_MASK 0xffffffff
USB_DIEPINT0_IN_TKN_EP_MIS_SET 0x00000020
CM_EVENT_GAINH_SET 0x00000010
CM_PULSECTL_FRAC_BITS 9:9
MS_ICSET_1_ICSET_1_BITS 0:0
USB_DOEPCTL0_NEXT_EP_CLR 0xffff87ff
L1_L1_SANDBOX_START6_CTRL_SET 0x00000001
EMMC_INTERRUPT_SDOFF_ERR_CLR 0xff7fffff
HDMI_RAM_PACKET_9_1_WIDTH 32
PM_DFT_ALLOWAUDIOCKSTOP_MSB 0
AVE_OUT_BLOCK_ID 0x7e240060:RW
CM_DSI1PCTL_SRC_MSB 3
CM_PERIIDIV_WIDTH 13
DMA8_DEST_AD_WIDTH 32
TXP_CTRL_ALPHA_ENABLE_CLR 0xffefffff
DMA8_DEBUG_FIFO_ERROR_LSB 1
SH_CDIV_CLOCKDIV_CLR 0xfffff800
SCALER_DISPECTRL_Y_NE_CTRL_SET 0xf0000000
A2W_PLLA_ANA_KAIPR 0x7e102b10:RW
TS_TSENSCTL_RSTB_MSB 1
MS_SEMA_27_MASK_LSB 0
SMI_DSW0_WSETUP_CLR 0xc0ffffff
USB_HPRT 0x7e980440:RW
DMA13_CS_PRIORITY_BITS 19:16
DMA3_STRIDE 0x7e007318:RO
SPI_CS_INTR_SET 0x00000400
A2W_PLLB_ANA_SSCLR_RESET 0000000000
PCM_MODE_A_CLK_DIS_MSB 28
A2W_PLLC_DIG0R_MASK 0x00ffffff
SD_DQRCRC8_RISE_CLR 0x0000ffff
APERF0_BW2_WTWAIT_MASK 0xffffffff
SD_DMRCRC1_LOW_SET 0x0000ffff
DMA2_DEBUG_FIFO_ERROR_MSB 1
AVE_IN_STATUS_AXI_STATE_LSB 20
MPHI_HSINDDA_START_MSB 31
SYSAC_V3D_LIMITER_INCREMENT_BITS 0:0
DMA0_TI_PERMAP_LSB 16
USB_DIEPINT0_BNA_BITS 9:9
DMA11_NEXTCONBK_WIDTH 32
A2W_PLLA_FRAC 0x7e102200:RW
SD_MR_RW_BITS 28:28
SMI_CS_DONE_SET 0x00000002
ASB_H264_M_CTRL_WCOUNT_SET 0x00ffc000
DMA12_SOURCE_AD_S_ADDR_SET 0xffffffff
A2W_PLLA_MULTI_RESET 0000000000
PM_GRAFX 0x7e10010c:RW
SYSAC_SRC_ARBITER_CONTROL_LIMIT_CLR 0xfffffffc
A2W_PLLA_FRACR 0x7e102a00:RW
HDMI_READ_POINTERS_RESET 0000000000
EMMC_CONTROL0_HCTL_DMA_LSB 3
DMA12_TI_DEST_IGNORE_BITS 7:7
AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_BITS 11:0
MPHI_INTSTAT_HSDISC_RESET 0x0
A2W_PLLH_MULTI_WIDTH 0
USB_GOTGINT_HST_NEG_SUC_STS_CHG_MSB 9
SLIM_DCC8_STAT_MASK 0xc0ff00c7
MPHI_INTSTAT_TXEND_LSB 16
DPHY_CSR_DQ_REV_ID 0x7ee07000:RW
CM_EVENT_MASK 0x00ffffff
USB_DTHRCTL_TX_THR_LEN_SET 0x000007fc
DMA2_TI_WAIT_RESP_SET 0x00000008
APERF1_BW2_CTRL_ID_BITS 12:8
GP_LEV0_WIDTH 32
EMMC_CONTROL0_ALT_BOOT_EN_BITS 22:22
DMA11_DEBUG 0x7e007b20:RW
DMA4_DEBUG 0x7e007420:RW
HDMI_RBUS_REGS
I2C_SPI_SLV_DR_DATA_LSB 0
A2W_PLLC_PER_BYPEN_MSB 9
DMA11_CS_RESET_SET 0x80000000
AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_MSB 29
SLIM_DCC2_PROT 0x7e210250:RW
CM_SYSCTL_MASK 0x00000040
USB_DIEPTSIZ1_WIDTH 32
MPHI_RXAXICFG_RXPPRIO_MSB 7
VPU_ARB_CTRL_L2_WIDTH 16
SLIM_DMA_MC_STAT_WIDTH 4
HDMI_VERTA1_WIDTH 25
DMA6_TXFR_LEN_XLENGTH_SET 0x0000ffff
MPHI_AXIPRIV_HSPECEN_SET 0x00000100
TS_TSENSCTL_WIDTH 27
I2C_SPI_SLV_MIS_RXMIS_MSB 0
SH_RSP0_CARD_STATUS_LSB 0
MS_MBOX_2_MBOX_SET 0xffffffff
PWM_DAT4_MASK 0000000000
MPHI_INTSTAT_RX0DISC_LSB 20
EMMC_FORCE_IRPT_OEM_ERR_BITS 31:30
A2W_PLLA_CTRLR 0x7e102900:RW
DSI1_DISP0_CTRL_MASK 0xffffffff
VCE_PC_IF0 0x7f000000 + 0x14000C:RW
SCALER_DISPSTAT_DSP1_STATUS_LSB 16
SD_SECEND1_WIDTH 32
DMA15_DEBUG_VERSION_LSB 25
SD_SECEND2_ADDR_MS_LSB 13
DMA13_CS_DREQ_STOPS_DMA_SET 0x00000020
MPHI_C1INDS_HANDLE_CLR 0xe01fffff
A2W_SMPS_A_VOLTS 0x7e1022a0:RW
USB_DOEPTSIZ3_WIDTH 32
GP_AFEN0_AFENn0_BITS 31:0
MPHI_C0INDDB_LENGTH_MSB 19
CM_PULSECTL_SRC_SET 0x00000003
CM_CAM0CTL_SRC_MSB 3
TXP_CTRL_ABORT_BITS 14:14
MPHI_AXIPRIV_RXPROT_MSB 6
DMA10_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
MPHI_HSINDDB_MASK 0x2fffffff
SD_DQLCRC15_RISE_MSB 31
MPHI_INTCTRL_IMFOFLW_BITS 8:8
HDMI_RAM_PACKET_6_6_MASK 0xffffffff
SD_RTC 0x7ee0001c:RW
DMA4_DEBUG_VERSION_SET 0x0e000000
SMI_DSW1_WFORMAT_MSB 23
VPU_ARB_CTRL_BASE 0x7ee04000
USB_GPVNDCTL_STS_DONE_CLR 0xf7ffffff
HDMI_BKSV0_RESET 0000000000
USB_GPVNDCTL_CTRL_UTMI_LSB 8
GP_CLR2_CLRn64_MSB 5
DMA15_CS_DISDEBUG_LSB 29
EMMC_STATUS_RETUNING_REQ_SET 0x00000008
CM_PLLB_MASK 0x00000303
I2C_SPI_SLV_ICR_WIDTH 4
EMMC_RESP1_WIDTH 32
VEC_STATUS0_MASK 0xffffffff
HDMI_DETECTED_VERTA1_MANUAL_VAL1_BITS 12:0
UART_LCR_OUT1_MSB 2
CM_PERIACTL_GATE_SET 0x00000040
DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
UNICAM_IBWP(x) MACRO
EMMC_STATUS_WRITE_TRANSFER_BITS 8:8
DMA1_CS_RESET_LSB 31
PM_HDMI_CTRLEN_MSB 0
SD_TMC_IPSEL_SET 0x00000070
IC0_SRC0 0x7e002008:RO
SD_SD_T_RPab_CLR 0x0fffffff
CM_VECCTL_FRAC_SET 0x00000200
GP_SET2_SETn64_CLR 0xffffffc0
USB_GRXSTSP_HST_CH_NUM_CLR 0xfffffff0
DMA6_CS_DREQ_LSB 3
PCM_GRAY_RXLEVEL_MSB 9
USB_HCCHAR5_MASK 0xffffffff
ARM_0_MAIL1_WRT (0x7E00B000 +0x800)+0xA0:RW
IC1_PROFILE_WIDTH 16
CM_UARTCTL_BUSY_BITS 7:7
DMA11_CS_PRIORITY_BITS 19:16
ARM_C0_DBG1SYNC 0x00020000
SMI_DSR1_MODE68_SET 0x00800000
GP_FSEL6_FSEL61_MSB 5
PWM_CTL_RPTL2_SET 0x00000400
SD_CS_DPD_MSB 2
DSI0_INT_STAT_WIDTH 32
USB_GPVNDCTL_REG_DATA_BITS 7:0
USB_HCCHAR0_EP_DIR_SET 0x00008000
GPLEV0 0x7e200000 + 0x34:RW
A2W_PLLC_ANA_KAIP_KI_LSB 4
CM_TIMERDIV_MASK 0x0003ffff
CMI_CAM1_RX3SRC_MSB 9
USB_DIEPCTL0_SET_EVEN_FR_LSB 28
USB_GHWCFG3_VENDOR_CTL_INTERFACE_MSB 9
SDHCFG SDCARD_BASE + 0x38:RW
DSI_CMD_PKTC 0x7e209000 + 0x04:RW
EMMC_FORCE_IRPT_DCRC_ERR_CLR 0xffdfffff
DMA0_TXFR_LEN_YLENGTH_MSB 29
USB_DOEPMSK_WIDTH 32
DSI_CMD_PKTH 0x7e209000 + 0x08:RW
AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_MSB 31
SCALER_DISPCTRL_HVS_EN_BITS 31:31
CM_PLLTCNT3_WIDTH 24
AUX_SPI_CNTL0_CS_HIGH 0x000E0000
USB_DIEPCTL0_TXF_NUM_MSB 25
PM_PADS5_DRIVE_LSB 0
SD_HOST_DMA (13*(1<<16))
DMA11_TI_SRC_IGNORE_BITS 11:11
SMI_DSR1_RWIDTH_MSB 31
CM_PCMDIV 0x7e10109c:RW
USB_GHWCFG4_MASK 0xffffc03f
DMA8_CS_INT_MSB 2
EMMC_TUNE_STEP_MASK 0x00000007
CM_SDCDIV_DIV_CLR 0xfffc0fff
USB_DOEPTSIZ14_WIDTH 32
HD_SPARE_WIDTH 32
DMA8_CS_PANIC_PRIORITY_BITS 23:20
HDMI_RAM_PACKET_7_2_WIDTH 32
HDMI_BCH_CONFIGURATION_WIDTH 9
TXP_CTRL_TFORMAT_MSB 5
TXP_XTRA_NOSTBY_LSB 0
DMA6_CS_DREQ_STOPS_DMA_LSB 5
SD_CYC_RESET 0000000000
UART_LCR_WLS_LSB 0
DMA8_DEBUG_RESET 0000000000
FPGA_DCM_WR_DATA 0x7e20b610:RW
USB_GHWCFG2_EN_PERIO_HOST_RESET 0x0
CM_EVENT_FGAINB_SET 0x00000800
USB_HPRT_EN_CHNG_MSB 3
EMMC_CONTROL0_PWCTL_HWRST_BITS 12:12
DMA1_TI_SRC_DREQ_BITS 10:10
DMA10_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
HDMI_VERTA1_MANUAL_VFP1_MSB 19
DMA14_DEBUG_OUTSTANDING_WRITES_LSB 4
HDMI_RAM_PACKET_13_2_MASK 0xffffffff
USB_DTKNQR1_MASK 0xffffffff
USB_DIEPINT15_MASK 0xffffffff
MPHI_OUTDDB_LENGTH_CLR 0xfff00000
MPHI_INTSTAT_RX1DISC_MSB 24
CCP2TX_TPC_TPT_BITS 15:8
DMA11_TI_BURST_LENGTH_MSB 15
A2W_PLLA_ANA_VCO_RANGE_MSB 0
ASB_V3D_M_CTRL_EMPTY_CLR 0xfffffffb
DMA2_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
EMMC_IRPT_EN_CARD_OUT_BITS 7:7
A2W_XOSC_PWR_PWRDN_LSB 1
USB_DIEPTXF4_WIDTH 32
CM_DFTCTL_MASK 0x000003bf
A2W_PLLB_CTRL_PDIV_LSB 12
DMA3_TI_INTEN_BITS 0:0
USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_BITS 23:22
SD_RDC_RESET 0000000000
A2W_PLLB_ANA_KAIP_RESET 0x0000033a
V3D_DBSDR0_MASK 0xffffffff
I2C2_FIFO_RESET 0000000000
V3D_PCTRS1_WIDTH 5
DMA5_DEBUG_OUTSTANDING_WRITES_BITS 7:4
DMA6_TI_SRC_DREQ_MSB 10
SH_ARG_ARGUMENT_MSB 31
HDMI_RAM_PACKET_2_0_RESET 0000000000
V3D_PCTRS10_WIDTH 5
DMA_TI_WAITS(n) MACRO
USB_DIEPINT0_EP_DISBLD_CLR 0xfffffffd
IC_VADDR 0x7e002030:RW
PM_SMPS_UPEN_LSB 2
TS_TSENSCTL_RSTDELAY_LSB 18
HDMI_AUDIO_PACKET_CONFIG_WIDTH 30
GPIO_MAX_PINS 54
CM_ARMCTL_ENAB_BITS 4:4
USB_DOEPINT0_BNA_CLR 0xfffffdff
USB_DCTL_SGOUT_NAK_CLR 0xfffffdff
APERF0_BW1_CTRL_EN_RESET 0x0
DMA_INT_STATUS_INT11_MSB 11
USB_DIEPCTL0_TYPE_SET 0x000c0000
CM_TCNTCTL_SRC0_LSB 0
USB_DOEPTSIZ0_MC_LSB 29
DMA0_DEBUG_DMA_STATE_CLR 0xfe00ffff
CM_TSENSDIV_WIDTH 17
I2C_SPI_SLV_MIS_OEMIS_BITS 3:3
EMMC_CONTROL2_ACEND_ERR_LSB 3
DMA9_CONBLK_AD_RESET 0000000000
DMA14_DEBUG_LITE_LSB 28
APERF1_BW0_CTRL_RESET_SET 0x80000000
CM_HSMDIV 0x7e10108c:RW
CM_DSI1ECTL_BUSY_SET 0x00000080
DMA10_CS_DISDEBUG_MSB 29
DMA4_DEBUG_READ_ERROR_CLR 0xfffffffb
ISRC 0x7e002008:RO
DPHY_CSR_CRC_DATA 0x7ee07804:RW
DSI0_PHYC_forcehsstop_sync_SET 0x00000004
JICST_ERR (1 << 19)
DMA_ENABLE_EN10_MSB 10
AVE_OUT_BLOCK_ID_WIDTH 32
EMMC_INTERRUPT_BLOCK_GAP_MSB 2
FPGA_CTRL0_SD_PSU_EN_CLR 0xffffffef
DMA5_DEBUG_DMA_ID_LSB 8
APERF0_BW1_AMAX 0x7e00988c:RO
SMI_DSR2_RDREQ_MSB 7
HDMI_TST_AN0_MASK 0xffffffff
CMI_CAM0_RX1SRC_SET 0x00000030
MPHI_MINFS_OFLOW_MSB 31
A2W_PLLD_DIG3_WIDTH 24
PCM_CS_A_TXERR_SET 0x00008000
STCLO_0 0x7e003004:RO
CM_PLLTCTL_BUSY_MSB 7
SD_MR_WDATA_SET 0x0000ff00
SMI_DSR0_RHOLD_MSB 21
L1_D_PRIORITY_c0_per_priority_SET 0x00000f00
HDMI_SCHEDULER_CONTROL_ALWS_REKEY_KEEPOUT_LSB 4
DMA13_TI_WAIT_RESP_MSB 3
USB_DOEPINT9_WIDTH 32
A2W_PLLD_CORE_BYPEN_BITS 9:9
HD_CSC_24_23 0x7e808050:RW
CM_OSCFREQF 0x7e10112c:RW
SD_DQLCRC15_RISE_RESET 0x0
EMMC_CONTROL2_TUNEON_LSB 22
CM_OSCFREQI 0x7e101128:RW
USB_HCDMA5_MASK 0xffffffff
A2W_SMPS_A_GAIN_RESET 0000000000
VEC_FREQ1_0_MASK 0xffffffff
AVE_OUT_CTRL_INVERT_VSYNC_MSB 15
MS_SEMA_10_MASK_MSB 0
VPU_ARB_CTRL_UC_CHANNEL_INIBIT_MSB 15
PWM_CTL_MODE1_SET 0x00000002
EMMC_INTERRUPT_ACMD_ERR_BITS 24:24
V3D_PCTR7_WIDTH 32
EMMC_STATUS_CARD_DETECT_SET 0x00040000
DMA12_CS_ERROR_MSB 8
A2W_SMPS_CTLC3R_MASK 0x00ffffff
USB_DOEPCTL0_SET_D0_PID_SET 0x10000000
MPHI_AXIPRIV_TXPROT_RESET 0x2
DMA3_TI_NO_WIDE_BURSTS_LSB 26
HDMI_FIFO_CTL_VB_CNT_LSB 8
SCALER_GAM_DATA 0x7e400000 + 0xE0:RW
PM_AUDIO_APSM_LSB 0
PWM_CTL_USEF4_MSB 29
PM_PXLDO_RSTOSCDR_SET 0x00010000
PIXELVALVE1_VERTA_EVEN_MASK 0xffffffff
SH_HSTS_CRC16_ERROR_MSB 5
CM_CCP2CTL_ENAB_SET 0x00000010
APERF1_BW0_RTWAIT_MASK 0xffffffff
USB_DTXFSTS0 0x7e980918:RW
USB_DTXFSTS1 0x7e980938:RW
USB_DTXFSTS2 0x7e980958:RW
USB_DTXFSTS3 0x7e980978:RW
USB_DTXFSTS4 0x7e980998:RW
USB_DTXFSTS5 0x7e9809b8:RW
USB_DTXFSTS6 0x7e9809d8:RW
USB_DTXFSTS7 0x7e9809f8:RW
USB_DTXFSTS8 0x7e980a18:RW
USB_DTXFSTS9 0x7e980a38:RW
HDCP_KEY_KY0_MASK 0xffffffff
DSI1_PR_TO_CNT_WIDTH 32
DMA13_CS_DREQ_MSB 3
USB_GNPTXSTS_TX_Q_TOP_MSB 30
HW_POINTER_TO_ADDRESS(pointer) MACRO
CM_GP1DIV_DIV_CLR 0xff000000
USB_HPTXSTS_HPTXFSPCAVAIL_CLR 0xffff0000
CDP_PHYC 0x1C00E000 + 0x04:RW
CCP2TX_TS_TEI_CLR 0xfffbffff
TE_0VSWIDTH_MASK 0xffffffff
CM_DSI0EDIV_DIV_CLR 0xffff000f
GP_FSEL3_FSEL37_LSB 21
USB_HCINT3_WIDTH 32
TH0T0UD 0x18011000 + 0x14:RW
SMI_CS_INTT_LSB 10
SD_SECSRT0 0x7ee0003c:RW
SD_TMC_IPSEL_MSB 6
PCM_MODE_A_CLKI_SET 0x00400000
MULTICORE_SYNC_MBOX_2 MULTICORE_SYNC_BASE_ADDRESS + 0xA8:RW
I2C_SPI_SLV_RIS_TXRIS_SET 0x00000002
A2W_PLLH_ANA_KAIP_KI_SET 0x00000070
DMA15_TI_DEST_WIDTH_CLR 0xffffffdf
PM_GNRIC_MEMREP_BITS 3:3
USB_DIEPINT0_AHB_ERR_BITS 2:2
USB_DTXFSTSn(n) MACRO
USB_VBUS_DRV_VBUSVALID (1<<1)
GROPCTR_FEPEZIDLE 0x0A
EMMC_IRPT_MASK_OEM_ERR_SET 0xc0000000
PCM_MODE_A_PDME_SET 0x04000000
CM_PERIADIV_DIV_BITS 12:12
HDMI_RAM_PACKET_4_5_RESET 0000000000
SMI_DSW1_WSWAP_MSB 22
CM_GP1CTL_MASH_CLR 0xfffff9ff
MS_SEMA_31_WIDTH 1
SD_DQLCRC13_MASK 0xffffffff
MPHI_HSINDCF_EMPTY_LSB 31
SD_DQLCRC15_RISE_BITS 31:16
RNG_BASE 0x7e104000
USB_DTHRCTL_RX_THR_LEN_LSB 17
USB_GRXFSIZ_GRXF_DEP_SET 0x0000ffff
I2C2_BASE 0x7e805000
CM_SYSDIV_WIDTH 13
HDMI_DETECTED_VERTA0_MASK 0x01ffffff
APHY_CSR_DDR_PLL_MDIV_VALUE 0x7ee06034:RW
MS_MBOX_5_MBOX_BITS 31:0
IC0_WAKEUP 0x7e002034:RW
A2W_PLLB_FRAC_FRAC_MSB 19
CMI_CAM0_RESET 0000000000
L1_DESCRIPTION "VC4-L1 control"
EMMC_CMDTM_CMD_IXCHK_EN_CLR 0xffefffff
SPI_CS_CPOL_BITS 3:3
PM_USB_CTRLEN_CLR 0xfffffffe
DMA1_STRIDE_S_STRIDE_SET 0x0000ffff
USB_DIEPDMA14_WIDTH 32
V3D_SCRATCH_MASK 0xffffffff
MPHI_C1INDDB_LENGTH_RESET 0x0
SMI_DSW1_WSWAP_SET 0x00400000
JICST_SDONE (1 << 17)
ARM_3_MY_IRQS (0x7E00B000 +0xB00)+0xFC:RW
I2C_SPI_SLV_DMACR_DMAONERR_SET 0x00000004
DMA11_TI_SRC_DREQ_BITS 10:10
CM_UARTCTL_BUSY_CLR 0xffffff7f
TE_1C_WIDTH 32
EMMC_IRPT_EN_DMA_CLR 0xfffffff7
CM_PERIICTL_GATE_SET 0x00000040
DMA_ENABLE_EN3_BITS 3:3
MPHI_CTRL_SOFT_RST_DNE_SET 0x00020000
PM_AVS_STAT_ALERT_PERI_A_BITS 0:0
DMA5_CS_INT_MSB 2
MS_SEMA_17_MASK 0x00000001
A2W_PLLA_ANA_SSCS_MODE_BITS 16:16
SMI_DSR0_FSETUP_SET 0x00400000
APERF1_BW2_WTWAIT_MASK 0xffffffff
PM_GRAFX_ENAB_SET 0x00001000
EMMC_FORCE_IRPT_WRITE_RDY_CLR 0xffffffef
EMMC_STATUS_DAT_ACTIVE_CLR 0xfffffffb
DMA10_CS_ABORT_SET 0x40000000
PM_GNRIC_ISFUNC_CLR 0xffffffdf
MS_SEMA_3_MASK_SET 0x00000001
DMA13_DEBUG_DMA_STATE_MSB 24
USB_DOEPDMA0_WIDTH 32
UART_MSR_DDSR_MSB 1
L1_IC1_PRIORITY_IC1_APRIORITY2_BITS 11:8
SD_DMRCRC0_LOW_RESET 0x0
CM_PLLA_LOADCORE_LSB 4
AVE_OUT_STATUS 0x7e240004:RW
USB_GI2CCTL_ADDR_MSB 22
USB_DVBUSDIS_WIDTH 16
A2W_PLLC_FRAC_RESET 0000000000
HDMI_RAM_PACKET_4_2_MASK 0xffffffff
PIARBCTL_CAM_THRESHOLD_LSB 4
MPHI_HSINDDB_LENGTH_CLR 0xfff00000
USB_DIEPCTL13_WIDTH 32
USB_GRSTCTL_H_SFT_RST_BITS 1:1
AVE_IN_LINE_LENGTH_WIDTH 12
DMA5_CS_RESET_SET 0x80000000
HDMI_HOTPLUG_MASK 0x00000001
USB_DOEPCTL0_DPID_RESET 0x0
USB_DOEPCTL0_DIS_SET 0x40000000
SLIM_DMA_DC2_RESET 0000000000
A2W_SMPS_C_CLK_OSCDIV_LSB 0
CAM0_CAMIBEA0_MASK 0xffffffff
DSI0_LP_DLT7_WIDTH 10
I2C_SPI_SLV_CR_ENCTRL_SET 0x00000040
DMA9_CS_PAUSED_BITS 4:4
CAM1_CAMDAT0 0x7e801018:RW
SD_VAD_WIDTH 32
HDMI_HORZB_MANUAL_HSP_MSB 19
USB_GOTGCTL_WIDTH 20
USB_DIEPCTL0_SET_D0_PID_LSB 28
EMMC_INTERRUPT_TUNE_ERR_SET 0x04000000
MS_SEMA_31_MASK_CLR 0xfffffffe
HDMI_DETECTED_HORZB_MANUAL_HSP_SET 0x000ffc00
CM_DSI1PDIV_WIDTH 13
DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
SMI_DSW2_WFORMAT_BITS 23:23
APERF0_BW2_WTWAIT 0x7e0098d4:RO
PM_PXBG_CTRL_BITS 15:0
USB_HCTSIZ0_XFER_SIZE_BITS 18:0
EMMC_HWCAP0_TCLKFREQ_SET 0x0000003f
USB_HCINT0_XACT_ERR_SET 0x00000080
DMA15_DEBUG_DMA_ID_LSB 8
L1_IC0_CONTROL_MASK 0x0000007f
IC0_WAKEUP_MASK 0xfffffffe
SMI_DSR0_RWIDTH_BITS 31:30
PM_DSI1_CTRLEN_BITS 0:0
VEC_FCW_SECAM_B_WIDTH 32
USB_HPRT_WIDTH 19
HD_MAI_THR_DREQLOW_MSB 5
AUX_SPI_CNTL0_VARWID 0x00004000
UNICAM_IVWIN(x) MACRO
DMA1_TI_SRC_INC_SET 0x00000100
MS_IREQ_1_WIDTH 32
HDMI_RAM_PACKET_13_7_RESET 0000000000
CAM0_CAMDBG3_WIDTH 32
DMA8_DEBUG_READ_ERROR_LSB 2
L1_D_PRIORITY_c1_l2_priority_LSB 16
MPHI_HSINDDB_LENGTH_MSB 19
AVE_IN_FRAME_NUM_FRAME_NUM_BITS 11:0
GP_FSEL3_FSEL30_CLR 0xfffffff8
SYSAC_V3D_LIMITER_MAX_PRIORITY_MSB 7
CAM0_CAMDBEA0_RESET 0000000000
DMA0_TI_SRC_WIDTH_LSB 9
A2W_PLLH_ANA2_RESET 0000000000
DMA7_CS_DREQ_MSB 3
FPGA_MB_XSLC3_BUILD_NUM_WIDTH 32
VEC_SCHPH_MASK 0xffffffff
DMA14_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
HD_VID_CTL_MASK 0xfffc0000
USB_GHWCFG4_EN_DESC_DMA_MSB 30
CM_DSI0ECTL_FRAC_MSB 9
PCM_RXC_A_CH2WEX_BITS 15:15
CM_ISPCTL_KILL_SET 0x00000020
DMA14_DEBUG_MASK 0x1ffffff7
A2W_PLLA_DIG3_WIDTH 24
DMA15_TI_TDMODE_BITS 1:1
APERF1_BW2_RMAX 0x7ee080e4:RO
SD_DQLCRC5_MASK 0xffffffff
FPGA_CTRL0_DIS_SW_SPI_BITS 5:5
CM_DSI0ECTL_BUSYD_LSB 8
MPHI_HSINDCF_LENGTH_BITS 19:0
APERF1_BW2_CTRL_LATHALT_MSB 28
SMI_DCS_START_SET 0x00000002
UART_LSR_RFE_BITS 7:7
USB_PCGCR_STOP_PCLK_CLR 0xfffffffe
CM_EVENT_LOSSA_LSB 5
GP_AREN0_ARENn0_SET 0xffffffff
CM_GP1CTL_ENAB_LSB 4
SMI_CS_EDREQ_LSB 15
SD_DQLCRC12_RISE_RESET 0x0
DMA13_DEBUG_LITE_LSB 28
CM_OTPCTL_KILL_CLR 0xffffffdf
PM_AVS_RSTDR_SYSTEM_A_BITS 1:1
USB_DOEPINT0_IN_TKN_TXFEMP_MSB 4
UART_LCR_RTS_BITS 1:1
MPHI_CTRL_HATVAL_LSB 0
USB_GINTMSK_CUR_MOD_BITS 0:0
SLIM_DCC1_PA1_MASK 0x00ffff3f
HDMI_VERTB1_MANUAL_VSPO1_MSB 21
CMI_CAM0_HSSRC_BITS 1:0
EMMC_CMDTM_CMD_TYPE_BITS 23:22
SCALER_DISPCTRL_IRQ_EN_MSB 6
CM_PWMCTL_BUSY_BITS 7:7
I2C_SPI_SLV_CR_SPI_BITS 1:1
CM_DSI1PCTL_FRAC_CLR 0xfffffdff
CM_TD1CTL_STEP_LSB 12
EMMC_CONTROL2_ACTO_ERR_MSB 1
HDMI_READ_POINTERS_DRFT_ALMOST_MT_BITS 18:18
DMA7_DEST_AD_WIDTH 32
USB_DOEPTSIZ2_MASK 0xffffffff
PCM_RXC_A_CH2WID_MSB 3
DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
CM_OTPCTL_SRC_BITS 1:0
ARM_3_BELL2 (0x7E00B000 +0xB00)+0x48:RW
CM_TD0CTL_FRAC_SET 0x00000200
TB_JTB_CONFIG_TRSTN_CLR 0xffffbfff
VCE_BASE 0x7f100000
CM_DSI0HSCK_MASK 0x00000001
A2W_PLLD_ANA_KAIP_KI_LSB 4
EMMC_IRPT_EN_DMA_ERR_MSB 28
V3D_PCS 0x7ec00000 +0x0130:RW
IC0_MASK6_RESET 0000000000
L1_D_CONTROL_DC1_FLUSH_CLR 0xfffffffb
SD_SB_REORDER_LSB 7
APERF0_BW1_RPEND_WIDTH 8
SD_SECEND1_ADDR_LS_SET 0x00001fff
SD_DQLCRC8_FALL_BITS 15:0
UART_LCR_DTR_CLR 0xfffffffe
CM_PLLD_LOADDSI1_CLR 0xfffffffb
DMA_ENABLE_EN8_CLR 0xfffffeff
PIXELVALVE1_HORZA_WIDTH 32
EMMC_INTERRUPT_ATA_ERR_MSB 29
L2_CONT_OFF_l2_flush_core_limit_LSB 20
DMA4_TI_TDMODE_CLR 0xfffffffd
IC1_FORCE0_SET_RESET 0000000000
DSI_TST_SEL 0x7e209000 + 0x6C:RW
SD_SE_T_RTP_MSB 10
HDMI_RAM_PACKET_9_3_RESET 0000000000
IC1_MASK1_MASK 0x77777777
DMA14_CS_PANIC_PRIORITY_BITS 23:20
HD_CSC_CTL_PADMSB_LSB 4
SD_SECSRT2_ADDR_LS_RESET 0x0
A2W_PLLC_ANA_VCO_RESET 0000000000
USB_GHWCFG4_EN_SESSIONEND_FILTER_MSB 24
A2W_SMPS_L_SCAR_MASK 0x00000fff
DMA0_DEBUG_READ_ERROR_CLR 0xfffffffb
USB_DOEPTSIZ0_SUP_CNT_CLR 0x9fffffff
DMA5_TI_WAITS_CLR 0xfc1fffff
CCP2TX_TAC_APD_LSB 1
CM_PULSECTL_KILL_LSB 5
ASB_ISP_S_CTRL_RCOUNT_SET 0x00003ff0
DMA5_TI_NO_WIDE_BURSTS_BITS 26:26
MPHI_C1INDS_WORDS_CLR 0xffe00000
V3D_DBGE 0x7ec00000 +0x0f00:RW
I2C_SPI_SLV_RSR_RXDMABREQ_SET 0x00000020
SD_SE_T_FAW_CLR 0xfffc0fff
SD_DQLCRC6_FALL_CLR 0xffff0000
UART_MSR_RESET 0000000000
MPHI_HSINDS_HANDLE_BITS 28:21
A2W_XOSC_CTRL_WIDTH 20
USB_DIEPCTL0_SET_D1_PID_MSB 29
DMA4_DEST_AD 0x7e007410:RO
IC0_SRC1 0x7e00200c:RO
DMA2_CS_ACTIVE_BITS 0:0
DMA14_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
CCP2TX_TAC_RESET 0x77434307
CM_LOCK_FLOCKD_CLR 0xfffff7ff
OTP_BITSEL_REG_WIDTH 5
APHY_CSR_DDR_PLL_MISC_CNTRL 0x7ee0603c:RW
TXP_PROGRESS_MASK 0x00000fff
USB_GHWCFG2_NUM_EPS_BITS 10:13
ASB_V3D_M_CTRL_RCOUNT_MSB 13
USB_DIEPMSK_WIDTH 32
DMA15_TI_INTEN_SET 0x00000001
DMA0_CS_DREQ_MSB 3
EMMC_BUS_CTRL_BUS_WIDTH_BITS 14:8
A2W_PLLH_ANA_SCTL_SEL_CLR 0xfffffff8
AVE_OUT_CB_COEFF_BLUE_COEFF_BITS 9:0
SYSAC_HOST_PRIORITY_WIDTH 4
CM_TECCTL_FRAC_BITS 9:9
A2W_PLLC_ANA_SCTL_WIDTH 5
DMA6_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
CM_VECCTL_BUSYD_CLR 0xfffffeff
AVE_IN_STATUS_CAPTURING_CLR 0x7fffffff
USB_GHWCFG4_EN_B_VALID_FILTER_LSB 23
DMA2_CS_INT_MSB 2
CM_GP2CTL_BUSY_MSB 7
USB_GUSBCFG_SRP_CAP_BITS 8:8
CM_INTEN_RESET 0000000000
USB_HPRT_OVR_CURR_ACT_CLR 0xffffffef
V3D_SQRSV0_WIDTH 32
CM_EVENT_GAINB_CLR 0xfffffffd
AUX_ENABLES (0x7E215000 +0x004)
GP_EDS2_EDSn64_LSB 0
A2W_PLLD_DIG3R_MASK 0x00ffffff
APERF1_BW1_RTWAIT 0x7ee080a0:RO
A2W_PLLA_PERR 0x7e102d00:RW
A2W_PLLC_ANA_SSCL_RESET 0000000000
SMI_DC_REQW_SET 0x0000003f
IPROFILE_0 0x7e002038:RW
IPROFILE_1 0xffffffff:RW
DMA2_TI_DEST_DREQ_MSB 6
L1_IC1_CONTROL_DISABLE_CLR 0xfffffffe
TB_BOOT_OPT_FPGA_MSB 2
MS_SEMA_2_MASK_SET 0x00000001
A2W_PLLA_CTRL_PDIV_MSB 14
USB_DIEPCTL0_MPS_BITS 10:0
AJB_D0_FALL 0x000000
SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_MSB 5
SLIM_DCC4_PA0_WIDTH 24
PWM_CTL_RPTL3_LSB 18
SLIM_CON_WIDTH 32
CM_PERIIDIV_DIV_SET 0x00001000
SMI_CS_PAD_RESET 0x0
MS_MBOX_5_MASK 0xffffffff
APERF0_GEN_CTRL_RESET_RESET 0x0
CM_DSI0PCTL_ENAB_MSB 4
SH_HSTS_SDIO_IRPT_LSB 8
GP_AFEN2_AFENn64_SET 0x0000003f
IMASK6_0 0x7e002028:RW
USB_DPTXFSIZ3_WIDTH 32
MPHI_HSINDS_DISCARD_BITS 31:31
A2W_PLLH_ANA2R_RESET 0000000000
L1_L1_SANDBOX_END7_WIDTH 30
SMI_DCS_DONE_BITS 2:2
CM_TSENSCTL_KILL_LSB 5
EMMC_SLOTISR_VER_VENDOR_BITS 31:24
MPHI_C0INDDB_TENDINT_RESET 0x0
DMA5_TI_DEST_IGNORE_MSB 7
EMMC_HWCAP0_SDMA_CLR 0xffbfffff
CCP2TX_TC_SWR_SET 0x80000000
DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
IS_1 0xffffffff:RW
USB_DCFG_DEV_ADDR_MSB 10
DMA10_TI_SRC_WIDTH_LSB 9
SD_DQRCRC8_FALL_CLR 0xffff0000
SMI_A_DEVICE_CLR 0xfffffcff
SD_RWC_RXOVR_LSB 7
A2W_PLLD_DSI1_CHENB_MSB 8
USB_HCINT0_NAK_BITS 4:4
PM_AVS_RSTDR_H264_I_CLR 0xfffffffb
USB_GHWCFG4_EN_IDDIG_FILTER_SET 0x00100000
TXP_CTRL_GO_CLR 0xfffffffe
DMA15_CONBLK_AD_SCB_ADDR_BITS 31:5
DMA3_NEXTCONBK_ADDR_MSB 31
SMI_DC_PANICW_CLR 0xfffc0fff
PM_AVS_RSTDR_PERI_A_MSB 0
A2W_PLLB_DIG2_MASK 0x00ffffff
USB_GPVNDCTL_REG_ADDR_SET 0x003f0000
CM_EVENT_FGAINC_LSB 12
EMMC_IRPT_MASK_INT_A_MSB 9
A2W_PLLH_ANA_STAT_CNTLENB_CLR 0xffefffff
HDMI_KSV_FIFO_1_MASK 0x000000ff
V3D_PCTRS9_MASK 0x0000001f
MS_MBOX_6_WIDTH 32
EMMC_TUNE_STEPS_DDR 0x7e300090:RW
A2W_PLLD_ANA_SCTL_RESET_CLR 0xffffffef
DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
CM_PLLC_HOLDCORE2_SET 0x00000020
EMMC_IRPT_MASK_CTO_ERR_LSB 16
DMA1_DEST_AD_D_ADDR_MSB 31
INTERRUPT_SDCARDHOST ((64) + 56 )
PIXELVALVE2_VERTA_EVEN_MASK 0xffffffff
DMA6_DEBUG_LITE_LSB 28
HDMI_CEC_TX_DATA_2_WIDTH 32
CMI_CAM1_HSSRC_MSB 1
USB_GOTGCTL_MASK 0x000f0f03
AVE_IN_STATUS_MAX_HIT_BITS 16:16
DMA11_DEBUG_MASK 0x1ffffff7
DMA15_NEXTCONBK_ADDR_MSB 31
SD_SECSRT0_EN_CLR 0xfffffffe
A2W_PLLD_DSI0_CHENB_LSB 8
USB_DTHRCTL_RX_THR_EN_SET 0x00010000
SH_EDM 0x7e202034:RW
USB_DIEPINT0_TXF_EMPTY_LSB 7
DSI0_PHY_AFEC0_WIDTH 8
A2W_PLLB_CTRL_PRSTN_BITS 17:17
SLIM_DCC_BASE(n) MACRO
OTP_DATA_REG_MASK 0x0000001f
MPHI_C0INDDB_MENDINT_BITS 30:30
TXP_PROGRESS_LINES_BITS 11:0
CM_CCP2CTL_SRC_CLR 0xfffffff8
PWM_CTL_MSEN4_CLR 0x7fffffff
CM_CAM1CTL_FRAC_LSB 9
DMA13_DEST_AD_D_ADDR_MSB 31
SCALER_DISPECTRL_CR_NE_CTRL_SET 0xc0000000
SLIM_DCC9_PROT_RESET 0x000093a0
DMA11_DEBUG_WIDTH 29
V3D_CT00RA0 0x7ec00000 +0x0118:RW
MPHI_INTCTRL_HSDCOFLW_BITS 20:20
CM_OTPCTL_MASK 0x000003b3
MPHI_C1INDDB_TENDINT_MSB 29
FPGA_CTRL0_TV_ACTIVITY_LSB 13
USB_DTHRCTL_RX_THR_LEN_SET 0x07fe0000
DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
SPI_CS_RXF_LSB 20
CM_TD1CTL_BUSYD_SET 0x00000100
ASB_CPR_CTRL_EMPTY_SET 0x00000004
DMA14_TI_PERMAP_BITS 20:16
CMI_CAM0_HSSRC_LSB 0
DMA7_TI_SRC_WIDTH_CLR 0xfffffdff
L1_IC1_CONTROL_ENABLE_STATS_SET 0x00000004
USB_HCINT0_NAK_LSB 4
MPHI_HSINDS_HANDLE_LSB 21
JP_NCB 0x7e005014:RW
PWM_STA_GAPO4_BITS 7:7
CAM1_CAMSTA 0x7e801004:RW
A2W_HDMI_CTL_RCAL_MANR_LSB 8
HDMI_READ_POINTERS_DRFT_ALMOST_MT_LSB 18
USB_HPRT_TST_CTL_BITS 16:13
USB_GHWCFG3_SYNC_RESET_TYPE_BITS 11:11
MPHI_CTRL_STBY_BITS 27:27
SD_DQLCRC15_FALL_MSB 15
DMA13_TI_SRC_WIDTH_BITS 9:9
ARM_I0_MAIL 0x00000002
CAM0_CAMISTA_MASK 0xffffffff
USB_DOEPCTL0_TXF_NUM_RESET 0x0
MPHI_C0INDDB_MTERM_LSB 28
CAM0_CAMICS_MASK 0xffffffff
CM_TIMERCTL_ENAB_BITS 4:4
RSTFD RS_BASE + 0xc:RW
MPHI_C0INDCF_EMPTY_MSB 31
A2W_SMPS_L_SPAR_RESET 0000000000
CM_INTEN_FGAIND_SET 0x00002000
V3D_ERRSTAT_WIDTH 32
CCP2TX_TS_TFE_LSB 4
SD_VIN_WRITE_BITS 16:16
IC0_BASE 0x7e002000
SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_RESET 0x0
SD_DAT 0x7ee00038:RO
A2W_PLLB_ANA3_MASK 0x00ffffff
A2W_PLLD_CTRLR 0x7e102940:RW
MPHI_C0INDCF_ORUN_SET 0x20000000
DMA7_CS_INT_BITS 2:2
L1_L1_SANDBOX_START7_RESET 0000000000
USB_GI2CCTL_RW_CLR 0xbfffffff
DMA13_SOURCE_AD_S_ADDR_MSB 31
HD_VID_CTL_FULRGB_BITS 21:21
AVE_OUT_CTRL_INVERT_CSYNC_SET 0x00020000
RNG_DATA 0x7e104008:RW
MPHI_C1INDDA_MASK 0xffffffff
AVE_IN_STATUS_INTERLACED_MSB 10
DMA4_STRIDE_MASK 0xffffffff
CAM0_CAMDCS 0x7e800200:RW
EMMC_IRPT_EN_DCRC_ERR_SET 0x00200000
OTP_DECRYPTION_ENABLE_FOR_DEBUG 22
A2W_PLLD_ANA_SSCLR_RESET 0000000000
DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
USB_GUSBCFG_ULPI_EXT_VBUS_IND_SET 0x00200000
L1_IC0_CONTROL_ENABLE_STATS_CLR 0xfffffffb
A2W_SMPS_A_GAIN_WIDTH 3
USB_PCGCR_PWR_CLMP_RESET 0x0
CM_AVEOCTL_BUSY_BITS 7:7
SD_SECSRT3_ADDR_MS_MSB 31
USB_DOEPINT0_XFER_COMPL_RESET 0x0
HDMI_RAM_PACKET_11_4_RESET 0000000000
PM_PADS5_POWOK_SET 0x00000020
SMI_CS_RXR_RESET 0x0
PWM_CTL_MODE2_LSB 9
L1_D1_WR_MISSES_MASK 0000000000
A2W_PLLD_DSI1_BYPEN_CLR 0xfffffdff
A2W_PLLB_SP1_CHENB_CLR 0xfffffeff
SPI_CS_TA_BITS 7:7
CAM1_CAMIHWIN_WIDTH 32
AVE_OUT_CTRL_NTSC_PAL_IDENT_BITS 13:13
INTERRUPT_DUMMY ((64) + 63 )
IC0_MASK4_WIDTH 31
A2W_XOSC_CPRR 0x7e102a90:RW
CM_HSMCTL_GATE_BITS 6:6
CM_AVEOCTL_FRAC_LSB 9
HDMI_FIFO_CTL_ON_VB_BITS 7:7
CM_PCMCTL_SRC_MSB 3
APERF0_BW1_RMAX 0x7e0098a4:RO
EMMC_INTERRUPT_CARD_CLR 0xfffffeff
V3D_PCTR5_MASK 0xffffffff
DMA7_TXFR_LEN_XLENGTH_MSB 15
MS_SEMA_4_MASK_BITS 0:0
DMA12_TI_DEST_DREQ_MSB 6
DMA4_CS_ABORT_CLR 0xbfffffff
ASB_ISP_M_CTRL_WCOUNT_BITS 23:14
CM_DSI0PCTL_SRC_BITS 3:0
DMA12_DEBUG_FIFO_ERROR_CLR 0xfffffffd
USB_DOEPCTL0_TXF_NUM_BITS 25:22
TB_HDMI 0x7e20b100:RW
SMI_DSW1_WFORMAT_BITS 23:23
CM_TD1CTL 0x7e1010d8:RW
SD_DQRCRC2_WIDTH 32
CSI2TRIG CSI2_BASE_ADDRESS + 0x40:RW
ASB_V3D_S_CTRL_RCOUNT_LSB 4
DMA2_CS_ABORT_SET 0x40000000
USB_DOEPDMAB8_MASK 0xffffffff
DMA13_CS_PAUSED_SET 0x00000010
A2W_HDMI_CTL_RCAL_MANR_BITS 11:8
SLIM_DCC0_PA0_MASK 0x00ffff1f
SMI_DSR1_RPACEALL_BITS 15:15
GRFSCV 0x1A005400 + 0x28:RW
DMA3_CS_RESET 0000000000
A2W_PLLH_DIG1R_MASK 0x00ffffff
DMA7_TI_PERMAP_BITS 20:16
APERF1_BW0_CTRL_RESET 0000000000
GROPCTR_FBC_CZ_PBE_STALLS 0x25
IC1_VADDR_WIDTH 32
DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
SD_CARCRC_FALL_BITS 15:0
A2W_PLLC_ANA_STAT_RESET 0000000000
APERF0_BW1_ATWAIT 0x7e009888:RO
INTERRUPT_VECTOR_BASE 0
DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
FPGA_DCM_WR_DATA_DATA_BITS 15:0
DMA8_TI_DEST_IGNORE_BITS 7:7
RSTID RS_BASE + 0x8:RW
SD_SECEND0_ADDR_MS_CLR 0x00001fff
DMA6_NEXTCONBK_ADDR_SET 0xffffffe0
PCM_GRAY_EN_CLR 0xfffffffe
USB_DTHRCTL_RX_THR_EN_CLR 0xfffeffff
SH_RSP1_MASK 0xffffffff
CMI_CAM1_RX1SRC_LSB 4
DMA_ENABLE_EN13_SET 0x00002000
CM_TIMERDIV_DIV_BITS 17:0
SCALER_DISPECTRL_POSTED_STATUS_LSB 12
SCALER_DITHER 0x7e400000 + 0x14:RW
PCM_RXC_A_CH1WEX_BITS 31:31
ARM_MC_ERROVERFLW 0x00000200
CM_VPUCTL_BUSYD_MSB 8
CCP2TX_TC_TIP_SET 0x0000ff00
L1_D1_RD_THRUS_WIDTH 0
PIXELVALVE0_VERTA 0x7e206014:RW
PIXELVALVE0_VERTB 0x7e206018:RW
SLIM_DCC1_CON 0x7e210228:RW
TB_JTB_CONFIG_SPEED_CLR 0xff00ffff
DMA4_DEST_AD_D_ADDR_SET 0xffffffff
CM_TDCLKEN_MPHIWDFT_CLR 0xfffffdff
EMMC_CONTROL2_TUNEON_BITS 22:22
USB_GOTGINT_SES_END_DET_RESET 0x0
ISP_RC_MASK 0xffffffff
SCALER_DISPCTRL_DSP0_PANIC_CLR 0xfcffffff
I2C_SPI_SLV_DEBUG1_DATA_BITS 25:0
DSI1_HS_CLT2_RESET 0000000000
CCP2TX_TDL_LEN_BITS 29:0
A2W_PLLD_MULTI 0x7e102f40:RW
CCP2TX_TTC_LCN_MSB 3
USB_MDIO_GEN 0x7e980000 + 0x84:RW
IC1_APB_ID 0x494e5445
SLIM_DCC1_PA0_MASK 0x00ffff1f
SD_RTC_WIDTH 32
EMMC_HWCAP1_SDR50_TUNE_LSB 13
SD_SB_REORDER_RESET 0x0
ARM_0_SEM0 (0x7E00B000 +0x800)+0x00:RW
ARM_0_SEM1 (0x7E00B000 +0x800)+0x04:RW
ARM_0_SEM2 (0x7E00B000 +0x800)+0x08:RW
USB_DTHRCTL_NON_ISO_THR_EN_SET 0x00000001
ARM_0_SEM4 (0x7E00B000 +0x800)+0x10:RW
ARM_0_SEM5 (0x7E00B000 +0x800)+0x14:RW
ARM_0_SEM6 (0x7E00B000 +0x800)+0x18:RW
ARM_0_SEM7 (0x7E00B000 +0x800)+0x1C:RW
GP_FSEL2_FSEL24_MSB 14
A2W_PLLC_CORE1_BYPEN_BITS 9:9
DMA8_DEBUG_DMA_ID_SET 0x0000ff00
CM_TDCLKEN_RESET 0000000000
DMA15_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
USB_GHWCFG2_HSPHY_INTERFACE_LSB 6
CM_PLLTCNT1_CNT_CLR 0xff000000
AVE_OUT_CTRL_SOFT_RESET_SET 0x40000000
EMMC_FORCE_IRPT_DEND_ERR_SET 0x00400000
GROPCTR_TU0_AXI_REQ_FIFO_FULL 0x10
PM_AVS_RSTDR_ROSC_CLR 0xffffffdf
ARM_0_SEMS (0x7E00B000 +0x800)+0x00:RW
USB_HCINT0_NYET_CLR 0xffffffbf
CM_H264CTL_ENAB_SET 0x00000010
A2W_SMPS_CTLC0R 0x7e1028c0:RW
A2W_PLLA_ANA_STATR 0x7e102c10:RW
A2W_PLLB_ANA_SCTL_UPDATE_SET 0x00000008
DMA11_CS_RESET 0000000000
A2W_SMPS_CTLC0_MASK 0x00ffffff
CGMSAE_TOP_DATA 0x7e806054:RW
APERF1_BW0_WMAX_RESET 0000000000
APERF0_BW2_CTRL_LATHALT_SET 0x10000000
STC2_0 0x7e003014:RW
STC2_1 0xffffffff:RW
SD_SECSRT2_ADDR_MS_RESET 0x0
USB_DOEPINT1_WIDTH 32
A2W_SMPS_C_CLK_TDEN_CLR 0xfffffff7
A2W_PLLB_ANA2_RESET 0000000000
L1_IC1_PRIORITY 0x7ee02084:RW
DMA6_DEBUG_VERSION_CLR 0xf1ffffff
DMA4_CS_DREQ_CLR 0xfffffff7
DMA13_TI_INTEN_LSB 0
DMA12_NEXTCONBK 0x7e007c1c:RO
SD_SECSRT1_WIDTH 32
DMA12_CS_RESET_LSB 31
CAM1_APB_ID 0x7563616d
A2W_PLLD_ANA1R_RESET 0x001d0000
GP_REN1_RENn32_MSB 31
GP_FSEL4_FSEL46_SET 0x001c0000
DMA2_NEXTCONBK 0x7e00721c:RO
TB_JTB_CONFIG_BITCNT_CLR 0xc07fffff
USB_DOEPINT14_MASK 0xffffffff
EMMC_CONTROL0_SPI_MODE_LSB 20
DMA0_CS_PRIORITY_LSB 16
ST_C3_WIDTH 32
A2W_SMPS_CTLC1R 0x7e1028c4:RW
GP_FSEL3_FSEL33_BITS 11:9
USB_HPTXSTS_HPTXQSPCAVAIL_SET 0x00ff0000
MS_MBOX_2_MASK 0xffffffff
USB_GINTMSK_CON_ID_STS_CHNG_MSB 28
A2W_HDMI_CTL1R_MASK 0x00ffffff
STC2_x(x) MACRO
PCM_INTEN_A_RXERR_SET 0x00000008
EMMC_IRPT_MASK_SDOFF_ERR_LSB 23
SYSAC_V3D_LIMITER_SPARE_MSB 3
DMA10_TI_SRC_INC_BITS 8:8
EMMC_CMDTM_CMD_ISDATA_BITS 21:21
PM_CAM0_LDOCTRL_BITS 20:3
MPHI_HSINDCF_LENGTH_MSB 19
HDMI_CEC_CNTRL_2_RESET 0x508d63d5
MS_VPU_STAT_VPU_STAT_CLR 0xfffffffe
AVE_OUT_OFFSET_BLUE_OFFSET_SET 0x000000ff
CM_CCP2DIV_DIV_SET 0x00001000
ISRC0_0 0x7e002008:RO
ISRC0_1 0xffffffff:RW
TB_PRINTER_CTRL_OFFSET_LSB 0
USB_GINTMSK_EOPF_LSB 15
A2W_PLLC_CORE1_DIV_CLR 0xffffff00
USB_DOEPCTL0_NEXT_EP_BITS 14:11
DMA7_DEBUG_VERSION_BITS 27:25
DMA7_DEBUG_MASK 0x1ffffff7
GP_FSEL1_FSEL17_BITS 23:21
L1_L1_SANDBOX_START0_START_ADDR_SET 0x3fffffe0
MS_SEMA_11_MASK_SET 0x00000001
A2W_SMPS_CTLC2R 0x7e1028c8:RW
FPGA_VERSION_WIDTH 32
DMA9_TI_INTEN_SET 0x00000001
GP_LEV2_MASK 0x0000003f
SCALER_PROFILE 0x7e400000 + 0x10:RW
SCALER_DISPSTAT_RD_IRQ_BITS 31:6
EMMC_HWCAP0_V1_8_LSB 26
DMA5_CS_PANIC_PRIORITY_CLR 0xff0fffff
PIXELVALVE0_BASE 0x7e206000
USB_HCCHAR0_DEV_ADDR_LSB 22
GP_FSEL0_FSEL09_BITS 29:27
HDMI_HORZB_RESET 0x03018010
HD_MAI_CTL_ERRORE_SET 0x00000004
DSI1_HS_DLT5_MASK 0xffffffff
CM_HSMCTL_BUSY_LSB 7
DMA4_TI_DEST_DREQ_CLR 0xffffffbf
A2W_PLLA_CTRLR_RESET 0x00010000
DMA13_TI_PERMAP_SET 0x001f0000
CM_TECDIV_DIV_SET 0x0003f000
VEC_WSE_VPS_DATA_1_WIDTH 32
SD_VIN_INT_EN_MSB 28
I2C_SPI_SLV_IFLS_RXIFLSEL_CLR 0xffffffc7
A2W_PLLH_AUXR_MASK 0x000003ff
HDMI_SCHEDULER_CONTROL_ALWS_VERT_KEEPOUT_BITS 3:3
SD_DMRCRC1_HIGH_BITS 31:16
APERF0_BW1_CTRL_ID_SET 0x00001f00
A2W_PLLD_DSI0_DIV_LSB 0
USB_GUSBCFG_ULPI_CLK_SUS_M_SET 0x00080000
USB_GOTGCTL_HST_SET_HNP_EN_SET 0x00000400
A2W_SMPS_CTLC3R 0x7e1028cc:RW
DPHY_CSR_DQ_PVT_COMP_CTRL 0x7ee07054:RW
APERF0_BW2_CTRL_RESET 0000000000
CAM0_CAMIBWP_MASK 0xffffffff
CM_TSENSCTL_BUSY_BITS 7:7
A2W_PLLA_ANA_VCO_MASK 0x00000001
DMA1_CS_ACTIVE_CLR 0xfffffffe
L2_CONT_OFF_l2_flush_flush_limit_BITS 19:16
A2W_PLLH_DIG2R 0x7e102868:RW
HDMI_SCHEDULER_CONTROL_USE_PREDICTS_SET 0x00000004
DMA2_CONBLK_AD_SCB_ADDR_BITS 31:5
MS_SEMA_14_WIDTH 1
SD_SECEND0_ADDR_MS_BITS 31:13
CM_TDCLKEN_PLLDDIV2_BITS 7:7
L1_D1_WR_HITS_MASK 0000000000
PM_IMAGE_MRDONE_LSB 4
EMMC_IRPT_EN_CARD_OUT_CLR 0xffffff7f
DMA2_CONBLK_AD_SCB_ADDR_MSB 31
APERF1_BW2_RTRANS 0x7ee080dc:RO
AVE_OUT_STATUS_PXL_OUTPUT_ERROR_CLR 0xfffffffd
ARM_C0_SIZ512M 0x00000002
CCP2TX_TPC_TPP_BITS 7:4
CAM1_CAMIDCD_WIDTH 32
SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_SET 0x0000ff00
USB_GAHBCFG_P_TXF_EMP_LVL_BITS 8:8
HD_VID_CTL_CLRRGB_CLR 0xff7fffff
CM_GP2DIV_DIV_MSB 23
GP_HEN1_MASK 0xffffffff
PCM_RXC_A_CH1WID_BITS 19:16
SD_DQRCRC14_FALL_SET 0x0000ffff
USB_DIEPINT0_IN_TKN_TXFEMP_SET 0x00000010
SMI_D 0x7e60000c:RW
GP_FSEL2_FSEL20_LSB 0
DMA12_TXFR_LEN_XLENGTH_SET 0x0000ffff
SYSAC_V3D_LIMITER_MAX_PRIORITY_RESET 0x0
USB_HPRT_RES_CLR 0xffffffbf
AVE_IN_CTRL_HSYNC_IRQ_EN_CLR 0xffffffdf
MPHI_C1INDDB_MTERM_MSB 28
CM_EMMCCTL_KILL_MSB 5
DMA5_DEBUG_LITE_LSB 28
DMA12_CS_DISDEBUG_MSB 29
A2W_PLLD_DIG0 0x7e102040:RW
A2W_PLLD_DIG1 0x7e102044:RW
DSI0_PHYC_dlane_hsen_0_sync_BITS 0:0
CM_GNRICCTL_ENAB_MSB 4
CM_DFTCTL_SRC_CLR 0xfffffff0
DMA15_TI_BURST_LENGTH_CLR 0xffff0fff
APERF1_BW2_CTRL_BUS_SET 0x0000001f
SLIM_NUM_DCC 10
SD_DQRCRC4_MASK 0xffffffff
HDMI_RAM_PACKET_11_2_WIDTH 32
V3D_CT1CS 0x7ec00000 +0x0104:RW
GP_FSEL4_FSEL48_SET 0x07000000
PCM_TXC_A_CH2POS_SET 0x00003ff0
USB_GUSBCFG_IND_PASS_THRU_CLR 0xfeffffff
OTP_BOOTMODE_REG_MASK 0xffffffff
MS_MBOX_0_RESET 0000000000
USB_GINTMSK_RXF_LVL_BITS 4:4
L1_D_CONTROL_DC0_FLUSH_BITS 1:1
HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT_MSB 15
USB_HCSPLT0_XACT_POS_MSB 15
USB_GI2CCTL_EN_RESET 0x0
MS_SEMA_25_MASK_SET 0x00000001
USB_GI2CCTL_REG_ADDR_MSB 15
DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
APERF0_BW2_WMAX_RESET 0000000000
CAM0_CAMDLT 0x7e800028:RW
L1_IC1_CONTROL_RAS_DISABLE_MSB 4
USB_GINTMSK_ISO_OUT_DROP_CLR 0xffffbfff
USB_GUSBCFG_OTG_I2C_SEL_BITS 16:16
VEC_CLMP0_START_MASK 0xffffffff
CM_LOCK_FLOCKH_SET 0x00001000
SLIM_DCC7_PA0_MASK 0x00ffff1f
CM_ARMCTL_FRAC_BITS 9:9
APERF0_BW0_AMAX 0x7e00984c:RO
TB_BOOT_OPT_EIGHT_BANK_MSB 1
EMMC_IRPT_MASK_CARD_IN_LSB 6
AVE_IN_CALC_LINE_STEP_MASK 0x00000fff
PM_AUDIO_APSM_BITS 19:0
MS_SEMA_6_MASK 0x00000001
CM_SMIDIV_WIDTH 16
USB_DOEPCTL0_ENA_BITS 31:31
SPI_DLEN_WIDTH 16
EMMC_CONTROL1_WIDTH 27
EMMC_IRPT_MASK_DEND_ERR_LSB 22
FPGA_MB_XSLC1_BUILD_NUM_MASK 0xffffffff
APERF1_BW1_CTRL_RESET_CLR 0x7fffffff
USB_HCCHAR0_MC_EC_LSB 20
CM_SMICTL_BUSYD_BITS 8:8
AVE_OUT_STATUS_HFRONT_PORCH_LSB 4
USB_HCINTMSK3_MASK 0xffffffff
USB_GRSTCTL_C_SFT_RST_MSB 0
GP_LEN0_LENn0_CLR 0x00000000
DMA3_TI_SRC_WIDTH_SET 0x00000200
FPGA_CTRL0_TERMEN_CLK_BITS 17:17
TS_TSENSSTAT_INTERUPT_CLR 0xfffff7ff
DMA12_CS_PANIC_PRIORITY_LSB 20
DSI1_PHY_AFEC0_WIDTH 32
A2W_PLLC_CTRL_PRSTN_BITS 17:17
USB_GHWCFG4_NUM_CRL_EPS_BITS 19:16
SPI_CS_INTR_LSB 10
AVE_IN_LINE_NUM_INT_MASK 0x00000fff
A2W_SMPS_B_STAT_POK_BITS 12:12
VCE_REGISTERS_COUNT 63
I2C_SPI_SLV_FR_RXFE_BITS 1:1
DMA14_DEST_AD_WIDTH 32
PM_PADS5_HYST_LSB 3
DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
HDMI_CP_INTEGRITY_RESET 0000000000
SCALER_DISPECTRL_PROF_TYPE_LSB 26
HD_MAI_CTL_BUSY_LSB 14
USB_DCTL_GMC_SET 0x00006000
A2W_SMPS_A_MODE_WIDTH 1
EMMC_DBG_SEL 0x7e300074:RW
USB_GINTMSK_CON_ID_STS_CHNG_LSB 28
DMA4_SOURCE_AD_S_ADDR_CLR 0x00000000
SCALER_DISPECTRL_TWOD_SINGLE_SET 0xfe000000
EMMC_CONTROL1_SRST_HC_BITS 24:24
MS_SEMA_29_WIDTH 1
CM_VECCTL_SRC_SET 0x0000000f
DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
DSI1_HS_CLT0_WIDTH 32
ASB_V3D_S_CTRL_EMPTY_SET 0x00000004
A2W_PLLD_DSI1_DIV_MSB 7
CM_TSENSCTL_SRC_CLR 0xfffffffc
TXP_CTRL_VSTART_AT_EOF_MSB 15
CM_TDCLKEN_PLLADIV2_LSB 4
SLIM_DCC9_CON_WIDTH 32
CCP2TX_TIC_TQIT_MSB 7
GP_EDS2_RESET 0000000000
CM_GP2CTL_KILL_SET 0x00000020
DMA3_CS_RESET_BITS 31:31
USB_GHWCFG4_EN_SESSIONEND_FILTER_BITS 24:24
A2W_PLLA_ANA_SCTL_RESET_LSB 4
DMA5_TI_SRC_IGNORE_LSB 11
TH0CS 0x18011000 + 0x00:RW
CM_CAM1DIV_WIDTH 16
SCALER_BASE 0x7e400000
PCM_TXC_A_CH1POS_SET 0x3ff00000
AUX_MU_FCR_TXCLR 0x04
SCALER_DISPSTAT_DSP2_STATUS_SET 0x3f000000
SH_EDM_WIDTH 19
MPHI_C0INDDB_HANDLE_SET 0x0ff00000
DMA0_CS_ABORT_LSB 30
DMA_INT_STATUS_INT1_MSB 1
A2W_PLLH_MULTI_MASK 0000000000
EMMC_CONTROL1_CLK_STABLE_MSB 1
AC_HUFFTABLE_OFFSET(t) MACRO
EMMC_CONTROL2_NOTC12_ERR_MSB 7
CM_HSMCTL_KILL_MSB 5
APERF0_BW1_AMAX_RESET 0000000000
SMI_DSR2_WIDTH 32
GRDCS 0x1A005A00 + 0x00:RW
A2W_PLLD_ANA_SSCS_WIDTH 17
EMMC_CONTROL2_SIGTYPE_MSB 19
GROPCTR_FBC_EZ_PBE_STALLS 0x35
FPGA_MB_SDC_ISP_FREQ_WIDTH 32
SD_SD_T_RPpb_BITS 7:4
SYSAC_JPEG_PRIORITY_P_PRIORITY_CLR 0xffffff0f
UART_LSR_TEMT_SET 0x00000040
A2W_PLLB_ANA0_WIDTH 24
PCM_DREQ_A_TX_PANIC_BITS 30:24
SYSAC_V3D_LIMITER_MAX_PRIORITY_LSB 3
CM_CKSM_CFG_BITS 17:16
USB_DIEPINT0_SETUP_BITS 3:3
USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_RESET 0x0
SMIFD_FLVL 8
DMA4_DEBUG_MASK 0x1ffffff7
AVE_OUT_CTRL_ENABLE_MSB 31
MS_ICCLR_0 0x7e000098:RW
CM_UARTCTL_KILL_SET 0x00000020
GP_PUDCLK1_PUDCLKn32_MSB 31
V3D_FDBG0 0x7ec00000 +0x0f04:RW
USB_DIEPCTL2_WIDTH 32
MS_ICCLR_1_ICCLR_1_CLR 0xfffffffe
USB_GUSBCFG_PHY_IF_RESET 0x0
USB_DIEPCTL0_NEXT_EP_SET 0x00007800
DMA1_TI_BURST_LENGTH_BITS 15:12
SCALER_DISPECTRL_BUSY_STATUS_CLR 0x000000ff
A2W_XOSC_PWR_BYPASS_SET 0x00000001
V3D_FDBGB 0x7ec00000 +0x0f08:RW
APERF0_BW0_CTRL 0x7e009840:RW
USB_HCSPLT0_SPLT_ENA_CLR 0x7fffffff
USB_HCTSIZ0_XFER_SIZE_LSB 0
USB_DOEPCTL0_SNAK_BITS 27:27
VIDEOCODEC_BASE_ADDRESS 0x7f000000
V3D_FDBGR 0x7ec00000 +0x0f0c:RW
V3D_FDBGS 0x7ec00000 +0x0f10:RW
DSI1_TST_SEL_RESET 0000000000
VEC_FCW_SECAM_B 0x7e806198:RW
DMA7_TI_BURST_LENGTH_CLR 0xffff0fff
GRSDMAX 0x1A005800 + 0x30:RW
USB_HCCHAR0_DEV_ADDR_RESET 0x0
HD_MAI_CTL_RST_MAI_LSB 0
PCM_CH1WEX (1 << 31)
USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_RESET 0x0
DMA7_CS_ACTIVE_SET 0x00000001
CAM0_CAMIBEA1_RESET 0000000000
CM_GNRICCTL_SRC_BITS 3:0
DMA12_CS_DISDEBUG_LSB 29
DSI0_PHYC_txulps_clk_sync_SET 0x00000200
SD_PHYC_IOB_TMODE_SET 0x00001000
ARM_0_MAIL0_POL (0x7E00B000 +0x800)+0x90:RW
CM_TCNTCTL_BUSY_LSB 7
UART_LSR_OE_BITS 1:1
DMA7_DEBUG_FIFO_ERROR_LSB 1
HDMI_MISC_CONTROL_WIDTH 31
DMA9_CS_DISDEBUG_BITS 29:29
MULTICORE_SYNC_SEMA_MASK_3 MULTICORE_SYNC_BASE_ADDRESS + 0x0C:RW
I2C_SPI_SLV_DR_TXFE_CLR 0xffefffff
CM_CKSM_STEP_LSB 21
L1_L1_SANDBOX_PERI_BR_sandbox_bootrom_LSB 0
HD_MAI_CTL_RST_MAI_BITS 0:0
CAM0_CAMIBEA0_WIDTH 32
SCALER_DISPLIST2_WIDTH 32
TB_BOOT_OPT_SDC_BEHAV_PHY_SET 0x00000020
JP_NSB 0x7e00501c:RW
SYSAC_UC_ARBITER_CONTROL_LIMIT_CLR 0xfffffffc
PM_CAM1_WIDTH 21
APERF0_BW2_ATRANS 0x7e0098c4:RO
A2W_PLLA_ANA_STAT_DATA_MSB 11
DMA5_CS_MASK 0xf0ff017f
AUX_SPI_CNTL1_INMS 0x00000002
EMMC_CMDTM_TM_DMA_EN_LSB 0
DMA14_TI_DEST_WIDTH_BITS 5:5
I2C_SPI_SLV_DR_RXFE_SET 0x00020000
EMMC_IRPT_EN_ENDBOOT_LSB 14
CM_ISPCTL_GATE_SET 0x00000040
CAM1_CAMDAT1_RESET 0x00000002
PM_RSTS_HADPOR_LSB 12
DMA8_DEST_AD_D_ADDR_LSB 0
SPI_CS_RXF_SET 0x00100000
SCALER_DISPECTRL_PANIC_CTRL_BITS 6:0
USB_GOTGINT_A_DEV_TOUT_CHG_MSB 18
PIARBCTL_CAM_ALGORITHM_LSB 6
MPHI_INTCTRL_RX0DISC_LSB 0
ARM_3_MAIL0_STA (0x7E00B000 +0xB00)+0x98:RW
PCM_CS_A_RXD_BITS 20:20
A2W_PLLA_DIG2R_WIDTH 24
SD_SA_PGEHLDE_MSB 8
I2C_SPI_SLV_TDR_MASK 0x000000ff
CAM1_CAMIVWIN_WIDTH 32
USB_GRSTCTL_RXF_FLSH_LSB 4
DMA4_TI_TDMODE_BITS 1:1
CM_TDCLKEN_PLLBDIV2_MSB 5
MPHI_HSINDFS_CFIFOLVL_LSB 16
GRTMPM0 0x1A005E00 + 0x00:RW
GRTMPM1 0x1A005F00 + 0x00:RW
I2C_SPI_SLV_DMACR_DMAONERR_CLR 0xfffffffb
DMA0_SOURCE_AD_S_ADDR_MSB 31
VEC_WSE_RESET_MASK 0xffffffff
PWM_RNG3_WIDTH 0
DMA2_NEXTCONBK_ADDR_BITS 31:5
DMA_CB_DA(n) MACRO
TB_BOOT_OPT_TB_PRESENT_SET 0x80000000
DMA13_TI_SRC_WIDTH_SET 0x00000200
DMA7_CS_END_MSB 1
UART_LCR_SBC_CLR 0xffffffbf
CM_TECCTL_BUSY_BITS 7:7
CM_CCP2CTL_WIDTH 10
DSI1_PHY_AFEC0 0x7e700070:RW
DMA7_TI_INTEN_LSB 0
ASB_ISP_S_CTRL_EMPTY_LSB 2
RSTWD RS_BASE + 0x4:RW
DMA4_DEBUG_LITE_LSB 28
DMA14_TI_DEST_WIDTH_SET 0x00000020
ASB_CPR_CTRL_FULL_BITS 3:3
I2C2_S 0x7e805004:RW
SLIM_STAT_RESET 0000000000
MPHI_MOUTFS_RPTR_SET 0x3ff00000
USB_DTXFSTS8_MASK 0xffffffff
CM_EVENT_FGAINB_BITS 11:11
TB_BOOT_STATUS_CPRMAN_PROGRAMMED_LSB 0
CM_PCMCTL_ENAB_BITS 4:4
CM_INTEN_LOSSB_MSB 6
L1_IC0_RAS_PUSHES 0x7ee02050:RO
TXP_CTRL_DITHER_CLR 0xffffdfff
GPHEN0 0x7e200000 + 0x64:RW
GPHEN1 0x7e200000 + 0x68:RW
GPHEN2 0x7e200000 + 0x6C:RW
USB_HCTSIZ0_PID_MSB 30
GP_FSEL3_FSEL39_MSB 29
ASB_ISP_M_CTRL_WCOUNT_CLR 0xff003fff
FPGA_DCM_WR_DATA_DATA_CLR 0xffff0000
DMA1_TI_TDMODE_CLR 0xfffffffd
CCP2TX_TC_RESET 0x0000ff00
PM_PROC_MRDONE_SET 0x00000010
SD_SD_T_RCD_SET 0x0000000f
GP_AREN2_ARENn64_SET 0x0000003f
HD_VID_CTL_CLRSYNC_SET 0x01000000
ARM_IF_VP0HALT 0x00000044
CM_SLIMDIV_RESET 0000000000
A2W_XOSC_CTRL_HDMIOK_LSB 13
DMA1_CS_PRIORITY_LSB 16
SD_DQRCRC2_FALL_BITS 15:0
DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
PM_HDMI_RSTDR_SET 0x00080000
V3D_DBQGHH_MASK 0xffffffff
CM_PWMCTL_WIDTH 11
EMMC_CONTROL2_DRVTYPE_MSB 21
DMA6_CS_PAUSED_BITS 4:4
HDMI_READ_POINTERS_DRFT_EMPTY_MINUS_CLR 0xfffdffff
USB_GINTMSK_USB_RST_LSB 12
PIXELVALVE1_HORZB_MASK 0xffffffff
DSI1_STAT_WIDTH 32
CM_SLIMCTL_BUSYD_CLR 0xfffffeff
EMMC_HWCAP1_DATA_RETUNE_BITS 15:14
UART_LCR_SP_CLR 0xffffffdf
A2W_PLLA_CTRL_NDIV_LSB 0
DMA8_CS 0x7e007800:RW
HDMI_SCHEDULER_CONTROL_ALWS_REKEY_KEEPOUT_MSB 4
SD_DQLCRC1_RISE_LSB 16
PM_AVS_RSTDR_V3D_G_MSB 3
ASB_H264_S_CTRL_CLR_ACK_BITS 1:1
HDMI_DETECTED_HORZB 0x7e90213c:RW
DMA11_CS_DISDEBUG_MSB 29
OTP_DATA_REG_WIDTH 5
MPHI_C1INDFS_CFIFOLVL_RESET 0x0
DMA3_CS_ERROR_CLR 0xfffffeff
SD_PT1_T_INIT3_LSB 8
IMASK6_1 0xffffffff:RW
DMA_ENABLE_EN14_LSB 14
EMMC_FORCE_IRPT_CTO_ERR_SET 0x00010000
DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
EMMC_CMDTM_CMD_ISDATA_SET 0x00200000
AVE_IN_STATUS_AXI_STATE_SET 0x00700000
EMMC_INTERRUPT_CTO_ERR_BITS 16:16
UART_MSR_TERI_MSB 2
PM_AVS_INTEN_ALERT_H264_I_MSB 2
FPGA_STATUS0_SD_WP_MSB 4
APERF1_BW0_CTRL_BUS_LSB 0
USB_HCSPLT0_HUB_ADDR_RESET 0x0
EMMC_IRPT_EN_DMA_MSB 3
A2W_PLLH_ANA_VCO_WIDTH 1
A2W_PLLC_CORE1_CHENB_LSB 8
DMA2_CS_PRIORITY_SET 0x000f0000
SCALER_DISPLSTAT 0x7e40002c:RW
GP_FSEL4_FSEL49_SET 0x38000000
CAM1_CAMDBEA1_RESET 0000000000
SLIM_DCC9_PA1_WIDTH 24
SD_DQRCRC11_MASK 0xffffffff
PWM_STA_STA2_BITS 10:10
AVE_OUT_CB_COEFF_RESET 0x3a9d5900
CM_CCP2CTL_ENAB_CLR 0xffffffef
DMA5_TXFR_LEN_YLENGTH_LSB 16
APERF1_BW1_CTRL_ID_SET 0x00001f00
SCALER_DISPSTAT2_MASK 0xffffffff
ASB_ISP_M_CTRL_CLR_REQ_LSB 0
SCALER_ALT_CONTROL 0x7e400000 + 0x0C:RW
A2W_PLLB_SP2_CHENB_SET 0x00000100
USB_GOTGCTL_DEV_HNP_EN_LSB 11
DMA7_TI_SRC_WIDTH_MSB 9
ARM_ID_SECURE 0x7E00B000 +0x00C:RW
A2W_PLLA_ANA_SSCLR 0x7e102a10:RW
AUX_SPI_STAT_BITCNT 0x0000003F
DMA10_TI_DEST_IGNORE_CLR 0xffffff7f
DMA1_DEBUG_MASK 0x1ffffff7
SYSAC_PERI_ARBITER_CONTROL_DELAY_BITS 3:2
A2W_SMPS_LDO1_MASK 0x00ffffff
SD_VER_WIDTH 32
GP_EDS0_WIDTH 32
HD_VID_CTL_ERROR_SET 0x06000000
DMA11_CS_PRIORITY_LSB 16
CAM1_CAMIBEA0 0x7e801114:RW
DMA2_STRIDE 0x7e007218:RO
MPHI_INTCTRL_RX1DISC_MSB 4
DMA10_DEBUG_LITE_LSB 28
CM_TCNTCTL_KILL_MSB 6
DSI0_TST_SEL_MASK 0x000000ff
PIXELVALVE1_VSYNCD_EVEN_WIDTH 17
CM_EVENT_LOSSH_CLR 0xfffffdff
AVE_OUT_Y_COEFF_WIDTH 30
FPGA_DCM_CTRL_PERI_WR_EN_CLR 0x0fffffff
SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_BITS 7:6
ARM_1_BELL1 (0x7E00B000 +0x900)+0x44:RW
ARM_1_BELL2 (0x7E00B000 +0x900)+0x48:RW
HDMI_VERTB0_MASK 0x003fffff
USB_HPRT_RST_MSB 8
USB_GHWCFG2_MODE_CLR 0xfffffff8
HDMI_DVO_TIMING_ADJUST_B_MASK 0xffffffff
UDLL 0x7e201000 + 0x00:RW
UDLM 0x7e201000 + 0x04:RW
GP_HEN0_HENn0_CLR 0x00000000
USB_DCFG_EP_MIS_CNT_CLR 0xff83ffff
PWM_CTL_USEF2_MSB 13
DMA13_CS_DISDEBUG_MSB 29
EMMC_HWCAP1_SDR104_CLR 0xfffffffd
USB_DIEPINT11_WIDTH 32
ARM_SD_SEM0 0x00010000
ARM_SD_SEM1 0x00020000
ARM_SD_SEM2 0x00040000
ARM_SD_SEM3 0x00080000
ARM_SD_SEM4 0x00100000
ARM_SD_SEM5 0x00200000
ARM_SD_SEM6 0x00400000
ARM_SD_SEM7 0x00800000
I2C_SPI_SLV_CR_HOSTCTRLEN_SET 0x00001000
DMA10_DEBUG 0x7e007a20:RW
EMMC_FORCE_IRPT_ACMD_ERR_BITS 24:24
PM_IMAGE_CFG_MSB 22
EMMC_IRPT_EN_WRITE_RDY_LSB 4
MS_MBOX_6_MBOX_SET 0xffffffff
DMA14_DEBUG_READ_ERROR_LSB 2
SD_SC_T_WR_CLR 0xfffff0ff
A2W_PLLC_PER_RESET 0x00000100
CM_TD1CTL_ENAB_SET 0x00000010
HDMI_VERTA1_MANUAL_VAL1_MSB 12
EMMC_IRPT_MASK_DTO_ERR_MSB 20
VPU_ARB_CTRL_L2_THRESHOLD_BITS 5:4
GRSDMIN 0x1A005800 + 0x2C:RW
CM_HSMCTL_SRC_CLR 0xfffffff0
GP_FSEL3_FSEL35_LSB 15
DMA1_STRIDE_D_STRIDE_SET 0xffff0000
DMA15_CS_PAUSED_CLR 0xffffffef
SCALER_DISPCTRL_DSP1_PANIC_SET 0x0c000000
USB_DIEPCTL0_NAK_STS_BITS 17:17
AVE_IN_STATUS_HSYNC_DET_LSB 5
A2W_PLLC_CORE2_BYPEN_CLR 0xfffffdff
DSI0_PHYC_dlane_hsen_0_sync_CLR 0xfffffffe
ARM_0_MAIL0_RD (0x7E00B000 +0x800)+0x80:RW
AUX_MU_IER_TXIRQEN 0x02
GP_CLR0_CLRn0_BITS 31:0
SMI_DA_ADDR_SET 0x0000003f
SCALER_DISPSTAT_DSP0_STATUS_CLR 0xffffc0ff
CM_VPUDIV_DIV_MSB 23
CM_H264DIV_DIV_SET 0x0000fff0
SLIM_DCC6_CON_MASK 0xffff0070
HDMI_RAM_PACKET_7_7_WIDTH 32
CCP2TX_TS_TXB_BITS 0:0
DMA4_TI_SRC_IGNORE_MSB 11
DMA4_DEBUG_DMA_STATE_CLR 0xfe00ffff
SMI_DSW2_WHOLD_LSB 16
HD_MAI_CTL_ERRORF_LSB 1
DMA6_DEBUG_DMA_ID_BITS 15:8
SD_SE_T_RTP_BITS 10:8
SYSAC_UC_ARBITER_CONTROL 0x7e009044:RW
DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
DMA9_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
VEC_CPS89_CPS1011 0x7e806128:RW
EMMC_IRPT_EN_ADMA_ERR_LSB 25
SMI_CS_SETERR_CLR 0xffffdfff
SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_MSB 7
CM_TD0CTL_SRC_SET 0x0000000f
HDMI_TX_PHY_TX_PHY_CTL_0_RESET 0x8e000000
A2W_PLLD_CTRL_PRSTN_BITS 17:17
SD_RWC_RXVAL_MSB 4
SD_MR_HI_Z_RESET 0x0
CCP2TX_TTC_LSC_LSB 4
DMA5_TI_TDMODE_BITS 1:1
USB_GNPTXSTS_TXF_SPC_AVAIL_BITS 15:0
VEC_CPS1213_CPS1415_MASK 0xffffffff
V3D_PCTR8_MASK 0xffffffff
SMI_CS_RXF_LSB 31
L1_L1_SANDBOX_START2_CTRL_CLR 0xfffffffe
MPHI_C0INDFS_CFIFOLVL_CLR 0x0000ffff
USB_GHWCFG2_NUM_HOST_CHAN_SET 0x0000000000
EMMC_IRPT_EN_RETUNE_MSB 12
TB_BOOT_OPT_ELPIDA_LSB 4
SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_LSB 8
ASB_H264_S_CTRL_EMPTY_LSB 2
ARM_C0_UNUSED78 0x00000180
USB_DOEPCTL0_USB_ACT_EP_MSB 15
CM_PLLB_HOLDARM_CLR 0xfffffffd
HDMI_RAM_PACKET_9_4_RESET 0000000000
USB_GINTMSK_GIN_N_NAK_EFF_CLR 0xffffffbf
APERF0_BW2_AMAX_WIDTH 24
HDCP_APB_ID 0x48444350
DMA15_CS_RESET_SET 0x80000000
IS_0 0x7e002004:RO
PIXELVALVE0_VERTB_MASK 0xffffffff
APERF0_BW1_ATWAIT_RESET 0000000000
APERF0_BW0_CTRL_RESET_CLR 0x7fffffff
HDMI_DETECTED_VERTA0_MANUAL_VFP0_MSB 19
DMA12_DEBUG_READ_ERROR_BITS 2:2
PM_DSI1_LDOHPEN_LSB 2
GRP_FDBGB 0x1A005740 + 0x04:RW
CM_DSI0ECTL_ENAB_LSB 4
EMMC_STATUS_CMD_LEVEL_CLR 0xfeffffff
DMA1_CS_PAUSED_LSB 4
I2C_SPI_SLV_RIS_RXRIS_CLR 0xfffffffe
DMA14_DEBUG_LITE_CLR 0xefffffff
HDMI_RAM_PACKET_5_6_RESET 0000000000
GRP_FDBGO 0x1A005740 + 0x00:RW
USB_DOEPDMA12_MASK 0xffffffff
GRP_FDBGS 0x1A005740 + 0x0C:RW
USB_GHWCFG3_SYNC_RESET_TYPE_MSB 11
APERF0_BW0_RPEND_MASK 0x000000ff
MPHI_C1INDDB_HANDLE_SET 0x0ff00000
DMA0_TI_WIDTH 27
MPHI_C1INDS_DISCARD_CLR 0x7fffffff
DMA1_TI_SRC_WIDTH_CLR 0xfffffdff
SMI_DC_DMAEN_BITS 28:28
SH_HCFG_DATA_IRPT_EN_MSB 4
GP_CLR2_CLRn64_BITS 5:0
HDMI_BKSV1 0x7e902014:RW
I2C_SPI_SLV_CR_EN_CLR 0xfffffffe
FPGA_STATUS0_NAND_RNB_SET 0x00000040
SLIM_DMA_MC_STAT 0x7e210088:RW
CM_PLLH_ANARST_SET 0x00000100
APERF1_BW2_RMAX_MASK 0x00ffffff
SCALER_DISPECTRL_SECURE_MODE_LSB 31
HDMI_READ_POINTERS_DOMAIN_HALF_FULL_LSB 30
CM_PERIIDIV_DIV_MSB 12
USB_DIEPTSIZ15_WIDTH 32
USB_GUSBCFG_FS_INTF_SET 0x00000020
L1_L1_SANDBOX_START1_MASK 0x3fffffff
HDMI_RAM_PACKET_1_8_RESET 0000000000
AVE_OUT_CTRL_INVERT_EVEN_FIELD_BITS 16:16
EMMC_INTERRUPT_DEND_ERR_CLR 0xffbfffff
EMMC_IRPT_EN_READ_RDY_BITS 5:5
PM_PROC_ARMRSTN_BITS 6:6
PM_GNRIC_ISPOW_SET 0x00000004
APERF0_BW1_CTRL_LATHALT_CLR 0xefffffff
DMA13_DEBUG_DMA_ID_CLR 0xffff00ff
SD_SECSRT1_ADDR_LS_RESET 0x0
SH_TOUT_TIME_OUT_MSB 31
SD_SA_POWSAVE_BITS 0:0
DSI1_PHY_AFEC1_RESET 0000000000
PCM_GRAY_FLUSH_CLR 0xfffffffb
HDCP_KEY_CTL_DONE_MSB 1
SMI_CS_TXW_MSB 26
SD_DQLCRC8_RISE_LSB 16
SMI_CS_TXD_BITS 28:28
CM_DSI0ECTL_WIDTH 10
SD_RWC_MARGIN_CLR 0xff3fffff
DSI0_PHYC_dlane_hsen_0_sync_SET 0x00000001
I2C1_A_RESET 0000000000
USB_DOEPCTL0_STALL_RESET 0x0
A2W_PLLB_MULTI_MASK 0000000000
EMMC_CMDTM_CMD_INDEX_CLR 0xc0ffffff
GP_LEN2_MASK 0x0000003f
GROPCTR_TU0_CACHE_RCV_WAITS 0x15
APERF1_BW1_WMAX 0x7ee08098:RO
ASB_H264_M_CTRL_CLR_ACK_SET 0x00000002
CM_TIMERCTL_FRAC_BITS 9:9
DMA7_CS_ACTIVE_MSB 0
TXP_CTRL_PILOT_MSB 31
SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_BITS 3:2
USB_GINTMSK_WK_UP_INT_SET 0x80000000
ASB_H264_S_CTRL_WIDTH 24
DMA5_STRIDE_S_STRIDE_SET 0x0000ffff
DMA5_DEST_AD_WIDTH 32
SD_DQLCRC9_WIDTH 32
DMA8_DEST_AD_D_ADDR_SET 0xffffffff
DMA15_TI_PERMAP_CLR 0xffe0ffff
HDMI_HORZA_MANUAL_HAP_BITS 12:0
DMA3_TI_TDMODE_SET 0x00000002
CM_PERIADIV_DIV_CLR 0xffffefff
PM_RSTS_HADDRH_LSB 2
A2W_PLLD_FRAC_FRAC_LSB 0
A2W_PLLA_ANA_SSCSR 0x7e102910:RW
DSI0_CMD_PKTH_WIDTH 32
TB_BOOT_OPT_FPGA_CLR 0xfffffffb
SD_SECSRT0_ADDR_LS_MSB 12
DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
HD_MAI_CTL_CHNUM_BITS 7:4
SCALER_DISPSTAT_WR_IRQ_CLR 0x0000001f
SCALER_DISPECTRL_MASK 0xffffffff
SPIFIFO SPI_BASE_ADDRESS + 0x04:RW
PCM_FIFO_DEPTH 64
L1_L1_SANDBOX_END5_RESET 0000000000
EMMC_BOOT_TIMEOUT 0x7e300070:RW
USB_DIEPTSIZ12_WIDTH 32
DMA14_DEBUG_FIFO_ERROR_BITS 1:1
CM_GP0CTL_RESET 0x00000200
CSI2_RWP1 CSI2_BASE_ADDRESS + 0x214:RW
MPHI_C0INDS_WORDS_SET 0x001fffff
HDMI_RAM_PACKET_5_1_MASK 0xffffffff
MPHI_MOUTFS_RPTR_BITS 29:20
DMA11_TI_PERMAP_BITS 20:16
CM_PLLH_LOADPIX_MSB 0
PCM_TXC_A_CH1WEX_BITS 31:31
PM_AVS_RSTDR_ARM_P_SET 0x00000010
EMMC_HWCAP1_DATA_RETUNE_CLR 0xffff3fff
CM_EMMCDIV 0x7e1011c4:RW
CAM0_CAMCLT 0x7e800014:RW
DMA7_DEBUG_LITE_CLR 0xefffffff
EMMC_INTERRUPT_DMA_LSB 3
A2W_PLLC_ANA_VCO_RANGE_LSB 0
SMI_DSW3_WWIDTH_LSB 30
DMA1_TI_SRC_DREQ_LSB 10
HDMI_TX_PHY_SPREAD_SPECTRUM 0x7e9022dc:RW
I2C_SPI_SLV_CR_I2C_MSB 2
SD_SF_POWSAV_T_MSB 18
A2W_PLLB_ANA0 0x7e1020f0:RW
SD_SB_BANKLOW_BITS 6:5
A2W_PLLB_ANA2 0x7e1020f8:RW
A2W_PLLB_ANA3 0x7e1020fc:RW
EMMC_IRPT_MASK_ADMA_ERR_SET 0x02000000
SD_WDC_WIDTH 28
V3D_PCTRS12 0x7ec006e4:RW
CM_ARMCTL_FRAC_LSB 9
EMMC_BLKSIZECNT_RESET 0000000000
CAM0_CAMDAT2_MASK 0xffffffff
USB_DOEPCTL0_SNAK_LSB 27
USB_DVBUSPULSE_MASK 0x00000fff
DMA2_TI_DEST_WIDTH_LSB 5
USB_DCTL_GNP_IN_NAK_STS_BITS 2:2
CM_EMMCCTL_BUSY_MSB 7
SH_TOUT 0x7e202008:RW
USB_DIEPINT0_TIMEOUT_RESET 0x0
USB_DCFG_PER_FR_INT_RESET 0x0
DMA15_TI_WAITS_CLR 0xfc1fffff
TB_BOOT_OPT_BANK_MODE_MSB 9
TXP_CTRL_TEST_MODE_CLR 0xffffffef
EMMC_TUNE_STEPS_DDR_RESET 0000000000
DMA_ENABLE_EN6_CLR 0xffffffbf
EMMC_IRPT_EN_TUNE_ERR_SET 0x04000000
USB_DOEPINT4_MASK 0xffffffff
EMMC_CONTROL1_SRST_HC_CLR 0xfeffffff
I2C_SPI_SLV_CR_EN_SET 0x00000001
SH_DATA_DATA_MSB 31
DMA10_NEXTCONBK_ADDR_BITS 31:5
L2CACHE_BASE 0x7ee01000
USB_DIEPTSIZ10_WIDTH 32
PWM_STA_GAPO1_LSB 4
DSI1_TXPKT2_C_WIDTH 32
APERF1_BW2_ATWAIT_WIDTH 32
IC0_FORCE1_CLR_RESET 0000000000
HDMI_CPU_MASK_STATUS 0x7e90234c:RW
SD_RWC_MASK 0x9fdf9f9f
SYSAC_L2_ARBITER_CONTROL_ALGORITHM_LSB 6
DPHY_CSR_DQ_PHY_MISC_CTRL 0x7ee07048:RW
HDMI_RAM_PACKET_3_0 0x7e90246c:RW
SPI_FIFO_DATA_CLR 0xffffff00
HDMI_RAM_PACKET_3_2 0x7e902474:RW
HDMI_RAM_PACKET_3_3 0x7e902478:RW
HDMI_RAM_PACKET_3_4 0x7e90247c:RW
HDMI_RAM_PACKET_3_5 0x7e902480:RW
HDMI_RAM_PACKET_3_6 0x7e902484:RW
HDMI_RAM_PACKET_3_7 0x7e902488:RW
SD_PHYC_MDLL_TMODE_SET 0x00010000
TH1CFG 0x1A008000 + 0x04:RW
CM_EVENT_RESUS_SET 0x00400000
CM_HSMCTL_BUSYD_BITS 8:8
USB_DIEPINT11_MASK 0xffffffff
USB_DIEPCTL0_EO_FR_NUM_SET 0x00010000
USB_HPRT_OVR_CURR_CHNG_RESET 0x0
CM_LOCK_FLOCKB_CLR 0xfffffdff
A2W_PLLH_DIG0_MASK 0x00ffffff
DMA2_CS_PRIORITY_LSB 16
INTERRUPT_VEC ((64) + 59 )
GP_SEN0_MASK 0xffffffff
SMI_DSW2_RESET 0x0101000c
VEC_WSE_CONTROL 0x7e8060c4:RW
AVE_OUT_STATUS_VBACK_PORCH_SET 0x00000100
A2W_PLLD_PER_BYPEN_MSB 9
I2C2_CLKT_WIDTH 16
A2W_PLLC_CORE2_DIV_SET 0x000000ff
USB_DIEPTSIZ0_RX_DPID_CLR 0x9fffffff
SLIM_DCC0_PROT_MASK 0xc001ffff
USB_DIEPDMAB13_MASK 0xffffffff
DMA12_TI_SRC_INC_BITS 8:8
PM_AVS_EVENT_ALERT_ARM_P_BITS 4:4
USB_DCTL_SFT_DISCON_CLR 0xfffffffd
PCM_INTSTC_A_TXERR_SET 0x00000004
PCMCS_EN (1 << 0)
EMMC_CONTROL0_HCTL_HS_EN_SET 0x00000004
UART_EN_MASK 0x00000002
USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_MSB 5
DMA_INT_STATUS_INT10_BITS 10:10
DSI1_TST_MON_MASK 0xffffffff
CM_PULSEDIV_DIV_LSB 12
SD_SC_T_RFC_MSB 30
USB_DIEPCTL11_MASK 0xffffffff
TB_JTB_BITCNT_MASK 0x0000003f
DMA9_TI_SRC_WIDTH_CLR 0xfffffdff
PM_PADS3_SLEW_MSB 4
DMA4_TI_PERMAP_BITS 20:16
USB_HCCHAR0_EP_TYPE_MSB 19
CM_PWMDIV_DIV_MSB 23
PWM_CTL_POLA4_CLR 0xefffffff
SYSAC_DMA_ARBITER_CONTROL_UC_RESET 0000000000
APERF1_BW2_CTRL_ID_EN_LSB 29
EMMC_FORCE_IRPT_TUNE_ERR_CLR 0xfbffffff
USB_DIEPTSIZ0_MC_CLR 0x9fffffff
DMA4_DEBUG_WIDTH 29
MPHI_MINFS_LEVEL_BITS 9:0
SYSAC_USB_PRIORITY_MASK 0x0000000f
ARM_IF_MAIL 0x00000041
CPG_APB_ID 0x67706320
SH_HCFG_BLOCK_IRPT_EN_BITS 8:8
FPGA_CTRL0_SPI1_SEL_LSB 10
HDMI_TEST_MASK 0x00000fff
GP_GPTEST_SPARE_SET 0x0000000e
UNICAM_DBWP(x) MACRO
TB_JTB_CONFIG_TMS_RISE_SET 0x00000100
IC0_FORCE0_SET 0x7e002048:RW
PM_RSTS_HADWRQ_MSB 4
PM_AVS_INTEN_ALERT_V3D_G_CLR 0xfffffff7
CM_SMICTL_BUSYD_CLR 0xfffffeff
SMI_CS_EDREQ_BITS 15:15
I2C_SPI_SLV_CR_INV_RXF_LSB 10
INTERRUPT_DMA11_12_13_14 ((64) + 27 )
PCM_TXC_A_CH1EN_MSB 30
I2C2_DLEN_RESET 0000000000
HDMI_RAM_PACKET_9_2_WIDTH 32
PWM_CTL_MODE4_MSB 25
I2C_SPI_SLV_CR_TXE_MSB 8
L1_IC1_FLUSH_S_MASK 0xffffffe0
HDMI_RAM_PACKET_9_3 0x7e902550:RW
A2W_PLLB_ANA0R_WIDTH 24
USB_DIEPTSIZ2_WIDTH 32
EMMC_CONTROL1_SRST_CMD_BITS 25:25
SYSAC_H264_PRIORITY_PRIORITY_RESET 0x0
PM_AUDIO_CTRLEN_MSB 20
TE_0C_WIDTH 32
CM_CAM0CTL_BUSY_CLR 0xffffff7f
A2W_PLLA_ANA_SCTL_SEL_CLR 0xfffffff8
SD_CS_DPD_BITS 2:2
DMA1_CONBLK_AD_SCB_ADDR_LSB 5
DMA13_TXFR_LEN_XLENGTH_MSB 15
A2W_PLLH_ANA1_MASK 0x00ffffff
SLIM_DCC7_PA0_RESET 0000000000
HDMI_RAM_PACKET_5_4_WIDTH 32
DMA11_CS_ACTIVE_LSB 0
AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_BITS 11:0
CCP2TX_TAC_CLAC_LSB 16
PCM_TXC_A_CH2WEX_LSB 15
EMMC_IRPT_MASK_ACMD_ERR_LSB 24
CM_TIMERDIV_RESET 0000000000
TB_BOOT_OPT_BANK_MODE_BITS 9:8
PCM_TXC_A_CH1WID_BITS 19:16
CM_EVENT_FGAINA_LSB 10
HDMI_RAM_PACKET_9_7 0x7e902560:RW
DMA8_TI_WAIT_RESP_CLR 0xfffffff7
HDMI_RAM_PACKET_9_3_MASK 0xffffffff
DMA7_DEBUG_READ_ERROR_SET 0x00000004
V3D_CT1LC_WIDTH 32
CM_PLLC_HOLDCORE0_SET 0x00000002
USB_DIEPTXF14_MASK 0xffffffff
HDMI_RAM_PACKET_1_6_WIDTH 32
PM_RSTC_QRCFG_SET 0x00003000
DSI1_TST_MON 0x7e70007c:RW
APERF1_BW0_WTWAIT_RESET 0000000000
USB_GINTMSK_ENUM_DONE_RESET 0x0
L1_D_CONTROL_DC_EN_STATS_MSB 3
EMMC_HWCAP0_V3_3_BITS 24:24
DMA1_TI_WAITS_SET 0x03e00000
SMI_DSW3_WSTROBE_LSB 0
EMMC_INTERRUPT_CMD_DONE_BITS 0:0
USB_GHWCFG3_MODE_RESET 0x0
HD_VID_CTL_ENABLE_SET 0x80000000
EMMC_HWCAP1_DRV18_TYPEA_MSB 4
L1_IC0_RAS_POPS_WIDTH 0
JP_HADDR 0x7e005028:RW
CM_CCP2CTL_FRAC_SET 0x00000200
HDMI_TX_PHY_TX_PHY_CTL_1_WIDTH 32
CM_DPICTL_BUSYD_MSB 8
CAM0_CAMIDPO_MASK 0xffffffff
APERF1_BW2_CTRL_RESET_RESET 0x0
HDMI_SCHEDULER_CONTROL_IGN_VSYNC_PREDS_CLR 0xffffffdf
USB_DIEPTXF1_FIFO_SIZE_RESET 0x0
MPHI_C0INDDB_MORUN_CLR 0x7fffffff
ARM_C0_JTAGMASK 0x00000E00
HDMI_RAM_PACKET_7_1_RESET 0000000000
VCE_BUSY_SLEEP 0x0b
A2W_XOSC_CTRL_PLLBOK_LSB 19
PWM_CTL_MSEN2_CLR 0xffff7fff
SCALER_DISPECTRL_GT8_BURST_LSB 24
I2CDLEN_x(x) MACRO
SH_CMD_BUSY_CMD_SET 0x00000800
CM_DPICTL_FRAC_MSB 9
DMA13_CS_RESET_LSB 31
DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
APERF0_BW1_CTRL_RESET_CLR 0x7fffffff
DMA1_CS_END_CLR 0xfffffffd
USB_GUSBCFG_PHY_IF_LSB 3
PIXELVALVE1_VSYNCD_EVEN 0x7e207008:RW
APERF0_BW1_WTWAIT 0x7e009894:RO
DMA5_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
HDMI_READ_POINTERS_DRFT_HOLD_RD_MSB 22
PIARBCTL_CAM_MASK 0x0000ffff
PM_PROC_POWUP_BITS 0:0
HDMI_RAM_PACKET_3_3_RESET 0000000000
AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_MSB 11
A2W_PLLB_ANA_KAIP_KI_MSB 6
MS_SEMA_20_MASK_MSB 0
CM_INTEN_FGAINC_LSB 12
USB_DIEPTSIZ6_MASK 0xffffffff
DMA1_TI_WAIT_RESP_CLR 0xfffffff7
DMA5_DEBUG_VERSION_SET 0x0e000000
HDMI_TX_PHY_TX_PHY_CTL_2_MASK 0xffffffff
CM_INTEN_FGAINA_BITS 10:10
AVE_OUT_CR_COEFF_RESET 0x100ca7d6
DMA8_TI 0x7e007808:RO
SD_DQLCRC5_RISE_BITS 31:16
I2C_SPI_SLV_DR_TXFF_BITS 18:18
IC1_MASK5_MASK 0x77777777
USB_DOEPINT0_OUT_TKN_EP_DIS_BITS 4:4
MPHI_RXAXICFG_RXNPRIO_LSB 0
DMA12_DEBUG_DMA_STATE_CLR 0xfe00ffff
GRFZCFG 0x1A005400 + 0x1C:RW
MPHI_C1INDFS_DFIFOLVL_LSB 0
HDMI_SCHEDULER_CONTROL_MASK 0x003fff7f
USB_DOEPCTL0_SNP_LSB 20
A2W_PLLA_CORER_RESET 0x00000100
USB_HCCHAR0_MASK 0xffffffff
SLIM_DMA_DC2_MASK 0xffffffff
CM_GP2DIV_DIV_BITS 23:0
CM_INTEN_FGAINB_SET 0x00000800
SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_SET 0x00000003
DMA4_TI_INTEN_BITS 0:0
EMMC_IRPT_EN_CTO_ERR_LSB 16
V3D_CT00RA0_MASK 0xffffffff
I2C0_DIV_WIDTH 16
DMA1_CS_INT_MSB 2
TB_JTB_CONFIG_SPEED_BITS 23:16
SD_DQRCRC10_RISE_CLR 0x0000ffff
DSI0_HS_DLT3_RESET 0000000000
INTERRUPT_EXCEPTION_OFFSET 0
FPGA_CTRL0_TERMEN_DO_BITS 16:16
DMA8_TI_DEST_DREQ_LSB 6
HDMI_DETECTED_VERTB0_MANUAL_VSPO0_BITS 21:9
PCM_INTSTC_A_RXR_MSB 1
DMA9_CS_RESET_SET 0x80000000
I2C_SPI_SLV_FR_TXFLEVEL_MSB 6
USB_DOEPDMAB2_WIDTH 32
MS_SEMA_10_MASK_LSB 0
USB_GNPTXSTS_TXF_SPC_AVAIL_SET 0x0000ffff
DMA10_DEBUG_OUTSTANDING_WRITES_MSB 7
DMA3_SOURCE_AD_S_ADDR_MSB 31
ALIAS_L1L2_NONALLOCATING(x) MACRO
USB_DOEPCTL0_CNAK_BITS 26:26
L1_IC0_RD_MISSES_MASK 0000000000
HDMI_VERTB1_MANUAL_VSPO1_LSB 9
A2W_HDMI_CTL3_MASK 0x00ffffff
A2W_XOSC_CTRL_SMPSEN_MSB 3
PM_AVS_INTEN_ALERT_V3D_G_SET 0x00000008
SLIM_DCC0_CON_MASK 0xffff0070
DMA3_TI_INTEN_MSB 0
CM_PLLC_LOADCORE0_LSB 0
USB_DIEPCTL3_WIDTH 32
DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
USB_GGPIO_GPI_SET 0x0000ffff
MPHI_CTRL_SOFT_RST_DNE_BITS 17:17
SCALER_DISPCTRL_DSP0_PANIC_BITS 25:24
FPGA_CTRL0_DIS_SW_SPI_MSB 5
PM_PADS2_HYST_SET 0x00000008
SMICS_ACTIVE 2
CM_HSMCTL_GATE_MSB 6
RNG_CTRL_MASK 0xffffffff
DMA4_CS_DREQ_STOPS_DMA_SET 0x00000020
HDMI_DETECTED_VERTA0_MANUAL_VAL0_LSB 0
HD_VID_CTL_CLRSYNC_BITS 24:24
PCM_RXC_A_CH1WID_MSB 19
A2W_PLLD_ANA0_MASK 0x00ffffff
SCALER_DISPSTAT_RD_IRQ_MSB 31
MPHI_C1INDCF_MTERM_LSB 28
CM_H264CTL_SRC_LSB 0
USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_SET 0x0000ffff
SD_SB_COLBITS_SET 0x00000003
DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
EMMC_HWCAP1_DRV18_TYPEA_BITS 4:4
EMMC_FORCE_IRPT_ACMD_ERR_MSB 24
DMA11_CS_INT_SET 0x00000004
SMI_DSR3_RSTROBE_SET 0x0000007f
SD_DMRCRC0 0x7ee00104:RO
SD_DMRCRC1 0x7ee00108:RO
GP_PUD_PUD_LSB 0
USB_GINTMSK_GOUT_NAK_EFF_BITS 7:7
V3D_DBQITC 0x7ec00000 +0x0e30:RW
EMMC_HWCAP0_RESUME_LSB 23
V3D_DBQITE 0x7ec00000 +0x0e2c:RW
L1_D0_WR_SNOOPS_MASK 0000000000
SMI_CS_INTR_BITS 11:11
DMA1_DEBUG_READ_ERROR_LSB 2
SYSAC_V3D_LIMITER_INCREMENT_MSB 0
FPGA_DCM_WR_DATA_ADDRESS_LSB 16
TIMER_CTRL_FREEDIV_MASK 0xff
CM_TDCLKEN_MPHIWDFT_BITS 9:9
HDMI_READ_POINTERS_DRFT_EMPTY_MINUS_BITS 17:17
SD_CYC_MASK 0x0fffffff
CM_SDCCTL_ENAB_CLR 0xffffffef
FPGA_STATUS0_SD_WP_LSB 4
DSI1_LPRX_TO_CNT 0x7e700040:RW
CM_EMMCDIV_DIV_MSB 15
A2W_SMPS_B_STAT_WIDTH 13
USB_GHWCFG4_HSPHY_DWIDTH_BITS 15:14
DMA9_CONBLK_AD_MASK 0xffffffe0
CM_GNRICCTL_GATE_CLR 0xffffffbf
PWM_FIF1_WIDTH 32
USB_DOEPINT0_STS_PHSE_RCVD_CLR 0xffffffdf
ARM_C1_MAIL 0x00000002
EMMC_IRPT_EN_RETUNE_LSB 12
A2W_PLLD_ANA3_RESET 0x00000180
DMA3_TI_NO_WIDE_BURSTS_BITS 26:26
SD_DMRCRC0_LOW_SET 0x0000ffff
A2W_XOSC_CTRL_PLLAOK_CLR 0xfffbffff
DMA14_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
DMA14_TI_BURST_LENGTH_BITS 15:12
SMI_DSW0_WIDTH 32
USB_HCSPLT0_PRT_ADDR_MSB 6
DMA2_DEBUG_DMA_STATE_SET 0x01ff0000
MS_SEMA_17_MASK_BITS 0:0
TXP_CTRL_POWERDOWN_LSB 21
DMA12_TI_SRC_WIDTH_BITS 9:9
USB_DIEPDMA10_WIDTH 32
DMA_ENABLE_EN11_SET 0x00000800
CM_LOCK_LOCKD_BITS 3:3
HDMI_RAM_PACKET_5_6_MASK 0xffffffff
GROPCTR_TU1_CACHE_RCV_WAITS 0x1D
PCM_CH2WID_LSB 0
HD_MAI_THR_DREQHIGH_SET 0x00003f00
USCR 0x7e201000 + 0x1C:RW
HD_MAI_CTL_ENABLE_SET 0x00000008
USB_DIEPTXF9_MASK 0xffffffff
EMMC_CONTROL2_EN_PSV_MSB 31
APERF1_BW0_CTRL_LATHALT_LSB 28
USB_GOTGINT_DBNCE_DONE_SET 0x00080000
EMMC_INTERRUPT_WRITE_RDY_BITS 4:4
DMA1_TI_DEST_WIDTH_MSB 5
DMA2_CS_DREQ_STOPS_DMA_MSB 5
GROPCTR_FEPEZRDY 0x09
MPHI_C0INDDB_MTERM_BITS 28:28
A2W_SMPS_CTLC2_MASK 0x00ffffff
CSI2_TREN CSI2_BASE_ADDRESS + 0x10:RW
UART_LCR_DLAB_LSB 7
EMMC_DMA_STATUS_ERR_AT_SET 0x00000003
GPREN2 0x7e200000 + 0x54:RW
SMI_DA_RESET 0000000000
DMA2_CS_WIDTH 32
SD_DQLCRC1_FALL_LSB 0
A2W_PLLH_ANA_STAT_WIDTH 21
CMI_USBCTL_GATE_BITS 6:6
GP_FSEL2_FSEL22_MSB 8
SMI_DCS_WRITE_CLR 0xfffffff7
SD_DMRCRC0_HIGH_RESET 0x0
L1_IC0_FLUSH_S_MASK 0xffffffe0
APERF0_BW1_RMAX_MASK 0x00ffffff
APERF1_GEN_CTRL_RESET_SET 0x00000002
A2W_SMPS_L_SCV_VOLTS_BITS 4:0
CCP2TX_TC_TEN_LSB 0
CM_DPICTL_ENAB_LSB 4
DMA15_TXFR_LEN_WIDTH 30
HDMI_V_RESET 0000000000
USB_DCFG_DEV_SPD_RESET 0x0
APERF1_BW0_RTWAIT 0x7ee08060:RO
SMI_DSW2_WPACE_LSB 8
EMMC_FORCE_IRPT_DTO_ERR_BITS 20:20
ASB_H264_M_CTRL_WIDTH 24
EMMC_INTERRUPT_INT_C_SET 0x00000800
TS_TSENSSTAT_DATA_LSB 0
A2W_PLLC_FRAC_FRAC_MSB 19
A2W_PLLA_ANA_SCTL_SEL_BITS 2:0
UART_LSR_PE_LSB 2
DMA2_TI_SRC_DREQ_LSB 10
EMMC_HWCAP1_SPI_BLOCKMODE_BITS 25:25
CM_V3DCTL_FRAC_MSB 9
DMA3_STRIDE_S_STRIDE_LSB 0
CM_PERIICTL_GATE_BITS 6:6
DMA11_TI_WAIT_RESP_CLR 0xfffffff7
SD_DQLCRC10 0x7ee00174:RO
SD_DQLCRC11 0x7ee00178:RO
SD_DQLCRC12 0x7ee0017c:RO
SD_DQLCRC13 0x7ee00180:RO
SD_DQLCRC14 0x7ee00184:RO
SD_DQLCRC15 0x7ee00188:RO
SD_SA_WIDTH 32
MPHI_C0INDCF 0x7e006018:RW
UART_MSR_RI_LSB 6
SCALER_DISPECTRL_Y_BUSY_BITS 31:9
TXP_XTRA_NOSTBY_BITS 0:0
HDMI_FIFO_CTL_VB_CNT_BITS 11:8
A2W_PLLH_RCAL_BYPEN_BITS 9:9
A2W_PLLA_ANA_SSCS_WIDTH 17
SH_VDD_POWER_ON_CLR 0xfffffffe
HD_VID_CTL_RST_FRAMEC_MSB 29
AVE_IN_BLOCK_ID_RESET 0x61766530
USB_HCTSIZ2 0x7e980550:RW
A2W_PLLC_CTRL_WIDTH 18
USB_GNPTXFSIZ_NP_TXF_ST_ADDR_MSB 15
CM_PERIIDIV_MASK 0x00001000
CAM0_CAMCMP0_WIDTH 32
EMMC_IRPT_EN_BOOTACK_SET 0x00002000
CM_OTPCTL_WIDTH 10
SD_PHYC_BIST_MODE_RESET 0x0
SD_CS_RESTRT_SET 0x00000001
SD_PHYC_CRC_CLR_SET 0x01000000
DMA1_DEBUG_DMA_ID_SET 0x0000ff00
AVE_OUT_BLOCK_ID_RESET 0x61766538
AVE_IN_STATUS_VFORM_FIELD_MSB 12
CAM1_CAMIHWIN_MASK 0xffffffff
SD_DQLCRC6_RISE_MSB 31
USB_HFIR 0x7e980404:RW
USB_GNPTXSTS 0x7e98002c:RW
PM_DSI0_LDOLPEN_CLR 0xfffffffd
APERF0_BW1_RTWAIT_WIDTH 32
SD_DQRCRC3_FALL_LSB 0
PCM_CS_A_RXSYNC_LSB 14
INTERRUPT_DSI0 ((64) + 36 )
INTERRUPT_DSI1 ((64) + 44 )
PM_CAM0_LDOCTRL_SET 0x001ffff8
SYSAC_USB_PRIORITY_PRIORITY_RESET 0x0
DMA10_SOURCE_AD_S_ADDR_CLR 0x00000000
EMMC_DBG_SEL_SELECT_CLR 0xfffffffe
A2W_XOSC_CPR_WIDTH 5
TB_BOOT_SECURE_MODE_WIDTH 2
SYSAC_L2_ARBITER_CONTROL_DELAY_CLR 0xfffffff3
DMA3_CS_PRIORITY_LSB 16
GRPBCFG 0x1A005600 + 0x50:RW
GP_AREN0_ARENn0_LSB 0
AUX_SPI_STAT_TXFILL 0x0F000000
CAM1_CAMIBEA0_MASK 0xffffffff
DMA7_TI_DEST_IGNORE_CLR 0xffffff7f
DSI1_LP_DLT7_WIDTH 32
AVE_IN_STATUS_AXI_STATE_MSB 22
DMA0_TI_PERMAP_MSB 20
PCMMODE_FRXP (1 << 25)
USB_DIEPINT4_MASK 0xffffffff
IC0_SRC1_MASK 0xffffffff
HD_HDM_CTL_SW_RST_CLR 0xfffffffb
SD_TMC_TSTPAT_CLR 0x0000ffff
CCP2TX_TC_CLKM_MSB 2
HDMI_RAM_PACKET_3_1_WIDTH 32
A2W_PLLB_ANA_KAIP_KP_LSB 0
PWMDAT2 0x7e20c000 + 0x24:RW
PWMDAT3 0x7e20c000 + 0x34:RW
PWMDAT4 0x7e20c000 + 0x44:RW
TB_JTB_CONFIG_ENABLE_BITS 11:11
PIARBCTL_CAM_DELAY_BITS 3:2
EMMC_CONTROL0_HCTL_DMA_MSB 4
CM_OTPDIV_DIV_CLR 0xfffe0fff
DMA10_CS_PAUSED_BITS 4:4
GP_FSEL5_FSEL52_CLR 0xfffffe3f
UNICAM_ICTL(x) MACRO
USB_GGPIO_GPO_BITS 31:16
EMMC_IRPT_MASK_BOOTACK_LSB 13
ASB_V3D_S_CTRL_WCOUNT_SET 0x00ffc000
INTERRUPT_HOSTINTERFACE ((64) + 32 )
DMA5_NEXTCONBK_ADDR_CLR 0x0000001f
MS_SEMA_17_MASK_LSB 0
SD_SF_PHYHOLD_RESET 0x0
DMA3_TI_BURST_LENGTH_SET 0x0000f000
DMA4_TXFR_LEN_XLENGTH_CLR 0xffff0000
FPGA_MB_XPERI_BUILD_NUM 0x7e20b70c:RO
USB_GOTGCTL_DBNC_TIME_CLR 0xfffdffff
DMA10_CS_END_LSB 1
CAM1_CAMDBG3_WIDTH 32
SH_CMD_LONG_RESPONSE_BITS 9:9
EMMC_BLKSIZECNT_SDMA_BLKSIZE_MSB 14
DMA3_DEST_AD_D_ADDR_CLR 0x00000000
CAM0_CAMSTA 0x7e800004:RW
CM_PWMCTL_ENAB_CLR 0xffffffef
USB_GHWCFG2_SINGLE_POINT_RESET 0x0
SLIM_DCC7_CON_MASK 0xffff0070
CM_EVENT_GAIND_BITS 3:3
APHY_CSR_ADDR_REV_ID 0x7ee06000:RW
PIXELVALVE_STAT_0 0x7e20602c:RW
PIXELVALVE_STAT_1 0x7e20702c:RW
MS_SEMA_6_MASK_CLR 0xfffffffe
GP_SEN0_SEN_BITS 31:0
A2W_HDMI_CTL_RCAL_WIDTH 17
SH_RSP0_CARD_STATUS_MSB 31
CM_SLIMDIV_DIV_SET 0x00ffffff
MPHI_INTSTAT_RX0DISC_MSB 20
PWM_CTL_SBIT3_CLR 0xfff7ffff
DMA0_TI_DEST_IGNORE_SET 0x00000080
PCM_CS_A_TXON_LSB 2
USB_DIEPINT14_MASK 0xffffffff
SCALER_DISPSTAT_DSP1_STATUS_MSB 21
SLIM_DCC7_STAT_MASK 0xc0ff00c7
DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
SMI_DSR2_RPACEALL_LSB 15
UART_LCR_PEN_LSB 3
SD_SECEND2_ADDR_MS_MSB 31
A2W_PLLB_ANA_SCTL 0x7e1025f0:RW
HDMI_RAM_PACKET_STATUS_MASK 0x00003fff
PM_PXLDO_CTRL_SET 0x0000ffff
TB_JTB_CONFIG 0x7e20b800:RW
CM_TD1DIV_RESET 0000000000
CM_SLIMCTL_MASH_CLR 0xfffff9ff
DMA9_CS_END_LSB 1
USB_GI2CCTL_BSY_DNE_MSB 31
CAM0_CAMDBSA1_MASK 0xffffffff
USB_GNPTXFSIZ_IN_EP_TXF0_DEP_BITS 31:16
HDMI_RAM_PACKET_1_0_RESET 0000000000
SMI_DSR0_RSTROBE_LSB 0
A2W_PLLH_PIX_DIV_LSB 0
HDMI_RAM_GCP_7 0x7e90241c:RW
SMI_CS_PXLDAT_SET 0x00004000
USB_HPRT_ENA_RESET 0x0
PIXELVALVE_STAT_x(x) MACRO
V3D_MEM2_BASE_ADDRESS 0x1A00C000
EMMC_CONTROL1_CLK_FREQ8_CLR 0xffff00ff
DMA12_TI_DEST_IGNORE_SET 0x00000080
VEC_DAC_CONFIG 0x7e806210:RW
DMA0_DEST_AD_D_ADDR_BITS 31:0
MPHI_C0INDCF_LENERR_SET 0x40000000
A2W_PLLD_CORER 0x7e102c40:RW
TIMER_CTRL_DBGHALT (1 << 8)
JCTRL_RESET (1 << 3)
DMA7_CS_INT_SET 0x00000004
EMMC_BUS_CTRL_IRQSEL_CLR 0xff8fffff
PIXELVALVE0_C 0x7e206000:RW
HDMI_TST_AN0_WIDTH 32
CCP2TX_TPC_TPP_SET 0x000000f0
A2W_PLLH_ANA_STAT_CNTLENB_LSB 20
AVE_IN_CALC_LINE_STEP_RESET 0000000000
FPGA_DCM_CTRL_REMOTE_RST_CLR 0xffffffe0
USB_GPVNDCTL_CTRL_UTMI_MSB 11
CM_PLLC_HOLDPER_CLR 0xffffff7f
OTP_PRIVATE_KEY_ROW (((((((((((((((((8 +4)+4)+1)+1)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)
CM_CCP2CTL_BUSY_BITS 7:7
DMA15_CS_DISDEBUG_MSB 29
USB_DCTL_GOUT_NAK_STS_LSB 3
A2W_SMPS_CTLC1_RESET 0000000000
SPI_CS_RXR_LSB 19
DMA5_TI_WAIT_RESP_CLR 0xfffffff7
DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
DMA10_NEXTCONBK_ADDR_SET 0xffffffe0
I2C1_CLKT 0x7e80401c:RW
DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
CM_V3DCTL_ENAB_LSB 4
DMA7_CS_RESET_LSB 31
SYSAC_HVSM_PRIORITY_P_PRIORITY_LSB 4
A2W_PLLH_RCAL_BYPEN_SET 0x00000200
DSI_CMD_DATA_FIFO 0x7e209000 + 0x14:RW
AVE_IN_CTRL_LOW_PRIORITY_BITS 19:16
DMA10_CS_ACTIVE_MSB 0
CM_TD1CTL_KILL_BITS 5:5
MPHI_C0INDS_WORDS_CLR 0xffe00000
A2W_PLLD_ANA1_WIDTH 24
APERF1_BW2_CTRL_RESET 0000000000
APERF1_BW1_WMAX_MASK 0x0000ffff
SH_CMD_COMMAND_CLR 0xffffffc0
DMA3_CS_PAUSED_BITS 4:4
DMA6_CS_DREQ_MSB 3
EMMC_INTERRUPT_DATA_DONE_LSB 1
DMA5_TI_TDMODE_CLR 0xfffffffd
PCM_GRAY 0x7e203020:RW
DMA0_CS_DISDEBUG_LSB 29
ASB_H264_S_CTRL_CLR_ACK_CLR 0xfffffffd
USB_GHWCFG4_EN_DED_TX_FIFO_BITS 25:25
SD_DQLCRC11_RISE_LSB 16
DMA9_CS_WIDTH 32
SD_DQLCRC8_FALL_LSB 0
CM_H264CTL_BUSY_BITS 7:7
APERF1_BW0_AMAX 0x7ee0804c:RO
MS_MBOX_1_MBOX_MSB 31
DMA2_CS_ERROR_BITS 8:8
CM_GP0CTL_BUSYD_LSB 8
A2W_PLLB_CTRL_PRSTN_SET 0x00020000
SD_SD_T_XP_CLR 0xfff8ffff
USB_GINTMSK_FET_SUSP_CLR 0xffbfffff
GRTMPM0_BASE 0x1A005E00
VPU_ARB_CTRL_UC_DELAY_BITS 3:2
GP_GPTEST_SPARE_BITS 3:1
APERF0_BW0_ATWAIT 0x7e009848:RO
FPGA_VERSION 0x7e20b600:RO
USB_DIEPCTL0_SET_EVEN_FR_MSB 28
DMA10_CS_ABORT_LSB 30
CMI_CAM0_RX1SRC_CLR 0xffffffcf
APERF1_GEN_CTRL_ENABLE_MSB 0
CM_DFTCTL_KILL_LSB 5
SH_HCFG_SDIO_IRPT_EN_LSB 5
DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
I2CC_0 0x7e205000 + 0x00:RW
I2CC_1 0x7e804000 + 0x00:RW
I2CC_2 0x7e805000 + 0x00:RW
I2CC_3 I2C_BASE_3 + 0x00:RW
EMMC_BLKSIZECNT_BLKCNT_BITS 31:16
PM_PADS5_DRIVE_MSB 2
AVE_IN_CTRL_FRAME_MODE_SET 0x00000600
PCMCS_RXTHR_3_QUARTER (2 << 7)
ARM_IF_BELL0 0x00000042
ARM_IF_BELL1 0x00000043
A2W_PLLD_CORE_CHENB_LSB 8
TB_BOOT_OPT_FAST_OPT_CLR 0xfffffffe
SPI_CS_CPHA_LSB 2
I2C_SPI_SLV_FR_TXFF_MSB 2
TXP_XTRA_NOSTBY_MSB 0
DMA6_CS_DREQ_STOPS_DMA_MSB 5
DMA_INT_STATUS_INT2_BITS 2:2
MS_IREQ_1_IREQ_1_LSB 0
UART_LCR_WLS_MSB 1
USB_HPRT_OVR_CURR_CHNG_CLR 0xffffffdf
USB_DTHRCTL 0x7e980830:RW
USB_HCTSIZ0_DO_PNG_CLR 0x7fffffff
GRSLW 0x1A005800 + 0x38:RW
VEC_BASE_ADDRESS 0x7e806000
FPGA_CTRL0_LV_SPARE_OUT_LSB 18
DMA0_TXFR_LEN_XLENGTH_MSB 15
SD_SECSRT2_ADDR_MS_SET 0xffffe000
V3D_SQCSTAT 0x7ec00000 +0x041c:RW
DMA14_DEBUG_OUTSTANDING_WRITES_MSB 7
DMA3_CS_DREQ_STOPS_DMA_BITS 5:5
I2CC_x(x) MACRO
DMA6_CS_ABORT_SET 0x40000000
DMA10_TI_DEST_INC_LSB 4
PM_PADS4_DRIVE_LSB 0
CM_ISPCTL_BUSY_SET 0x00000080
MPHI_C0INDCF_MTERM_CLR 0xefffffff
A2W_XOSC_PWR_PWRDN_MSB 1
DMA8_DEBUG_DMA_STATE_BITS 24:16
TB_PRINTER_CTRL_TASKNO_BITS 15:4
DSI1_RXPKT1_H_MASK 0xffffffff
AVE_IN_STATUS_WIDTH 32
PIARBCTL_CAM_ALGORITHM_RESET 0x0
SCALER_DISPSTAT_DSP1_IRQ_CLR 0x00000003
FPGA_STATUS0_SW_SPI_SPI_IN_SET 0x00000080
CM_PLLC_HOLDCORE1_LSB 3
PWM_CTL_RPTL1_SET 0x00000004
ALIAS_COHERENT(x) MACRO
VEC_CPS2829_CPS3031 0x7e80613c:RW
CM_TDCLKEN_PLLDBYP_BITS 3:3
SYSAC_PERI_ARBITER_CONTROL_LIMIT_BITS 1:0
V3D_DBSDR3_WIDTH 32
UART_LSR_BI_SET 0x00000010
DMA11_DEBUG_VERSION_BITS 27:25
DMA3_DEBUG_OUTSTANDING_WRITES_BITS 7:4
HDMI_FIFO_CTL_WIDTH 16
MPHI_C1INDCF_EMPTY_SET 0x80000000
CAM0_APB_ID 0x7563616d
A2W_PLLD_ANA0R_RESET 0000000000
CM_TDCLKEN 0x7e101144:RW
USB_DIEPTSIZ11_MASK 0xffffffff
PM_SMPS_UPEN_MSB 2
DMA3_DEBUG_FIFO_ERROR_BITS 1:1
TS_TSENSCTL_RSTDELAY_MSB 25
A2W_PLLD_DIG2R_MASK 0x00ffffff
CM_SLIMCTL_ENAB_LSB 4
IC1_MASK3_RESET 0000000000
MPHI_HSINDDB_LENGTH_BITS 19:0
USB_HCTSIZ5_MASK 0xffffffff
CCP2TX_TTC_FSP_LSB 12
SMI_DSR1_RDREQ_BITS 7:7
SLIM_MC_IN_STAT_WIDTH 4
ARM_2_MY_IRQS (0x7E00B000 +0xA00)+0xFC:RW
PM_PADS3_POWOK_CLR 0xffffffdf
MS_VPUSEMA_0_VPUSEMA_0_CLR 0xfffffffe
CM_TCNTCTL_SRC0_MSB 3
AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_MSB 11
USB_DOEPTSIZ0_MC_MSB 30
PM_AVS_INTEN_ALERT_ARM_P_BITS 4:4
MS_SEMA_16_MASK_BITS 0:0
DMA14_TI_PERMAP_MSB 20
ASB_H264_S_CTRL_WCOUNT_SET 0x00ffc000
CM_SYSDIV_DIV_SET 0x00001000
APERF0_BW2_RTWAIT_RESET 0000000000
DMA0_DEBUG_LITE_LSB 28
EMMC_RESP1_MASK 0xffffffff
SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_BITS 15:8
CM_SDCCTL_UPDATE_SET 0x00020000
CSI2_RSA_x(x) MACRO
DSI0_LP_DLT6_MASK 0x000003fc
CAM0_CAMICC_MASK 0xffffffff
USB_HCCHAR0_LSPD_DEV_BITS 17:17
USB_DIEPDMA3_WIDTH 32
DMA12_CS_ACTIVE_SET 0x00000001
HD_FRAME_CNT_RESET 0000000000
DMA5_DEBUG_DMA_ID_MSB 15
CPG_Debug3_MASK 0xffffffff
CAM1_CAMIBEA0_WIDTH 32
PM_CAM0_MASK 0x001fffff
HD_HDM_CTL_CECOVR_BITS 8:8
USB_DIEPTSIZ4 0x7e980990:RW
AVE_OUT_OFFSET_MASK 0x80ffffff
MPHI_OUTDFS_DFIFOLVL_RESET 0x0
DMA3_TI_DEST_INC_LSB 4
DMA1_BASE 0x7e007100
SPI_CS_RXD_SET 0x00020000
UART_MSR_DCD_SET 0x00000080
A2W_PLLH_AUX_DIV_CLR 0xffffff00
AVE_OUT_CTRL_COEFF_IRQ_EN_LSB 1
MPHI_C1INDDB_MTERM_BITS 28:28
EMMC_IRPT_EN_ATA_ERR_SET 0x20000000
SD_DMRCRC1_HIGH_MSB 31
EMMC_CONTROL2_TUNEON_MSB 22
SD_CS_DLLCAL_SET 0x00000c00
USB_HPRT_ENA_SET 0x00000004
DMA0_TI_DEST_DREQ_BITS 6:6
USB_DIEPCTL0_SET_D1_PID_BITS 29:29
DMA2_TI_TDMODE_BITS 1:1
DMA6_CS_END_LSB 1
USB_GHWCFG3_MASK 0xffff0fff
VPU_ARB_CTRL_L2 0x7ee04004:RW
SMI_DSW1_WPACEALL_MSB 15
SD_VIN_VIO_CLR 0xffefffff
GP_REN2_RENn64_LSB 0
L1_L1_SANDBOX_PERI_BR_sandbox_bootrom_BITS 4:0
CM_VECCTL_ENAB_SET 0x00000010
CM_SDCCTL_FRAC_SET 0x00000200
AVE_OUT_STATUS_VFRONT_PORCH_MSB 7
DMA3_TI_NO_WIDE_BURSTS_MSB 26
HDMI_FIFO_CTL_VB_CNT_MSB 11
PM_AUDIO_APSM_MSB 19
SMI_DSR1_RDREQ_MSB 7
USB_DIEPTSIZ0 0x7e980910:RW
USB_DIEPTSIZ1 0x7e980930:RW
USB_DIEPTSIZ2 0x7e980950:RW
USB_DIEPTSIZ3 0x7e980970:RW
GROPCTR_REVCULLEDPRIMS 0x03
USB_DIEPTSIZ5 0x7e9809b0:RW
USB_DIEPTSIZ6 0x7e9809d0:RW
USB_DIEPTSIZ7 0x7e9809f0:RW
USB_DIEPTSIZ8 0x7e980a10:RW
USB_DIEPTSIZ9 0x7e980a30:RW
SPIDLEN SPI_BASE_ADDRESS + 0x0C:RW
DMA4_CS_INT_SET 0x00000004
TS_TSENSCTL_DIRECT_LSB 6
SD_SB_EIGHTBANK_LSB 4
SMI_DSW1_WHOLD_CLR 0xffc0ffff
DMA2_CS_DISDEBUG_BITS 29:29
USB_GI2CCTL_SUSP_CTL_RESET 0x0
EMMC_FORCE_IRPT_ATA_ERR_SET 0x20000000
TIMER_CTRL_IE (1 << 5)
EMMC_INTERRUPT_CBAD_ERR_MSB 19
CCP2TX_TAC_TPC_SET 0x00000008
EMMC_IRPT_MASK_CBAD_ERR_SET 0x00080000
APERF1_BW1_RTRANS 0x7ee0809c:RO
UART_LCR_OUT1_BITS 2:2
I2C_SPI_SLV_FR_TXFE_BITS 4:4
CCP2TX_TSPARE_WIDTH 32
EMMC_SLOTISR_VER_SLOT_STATUS_CLR 0xffffff00
SYSAC_DUMMY_STATUS_WIDTH 1
HDMI_RAM_PACKET_12_7_RESET 0000000000
DMA3_TI_SRC_DREQ_LSB 10
CM_OTPCTL_BUSY_CLR 0xffffff7f
JPEG_BASE 0x7e005000
GP_FSEL3_FSEL37_MSB 23
HD_MAI_THR_DREQLOW_SET 0x0000003f
SH_HCFG_SLOW_CARD_CLR 0xfffffff7
DMA11_DEBUG_LITE_CLR 0xefffffff
SMI_CS_TEEN_RESET 0x0
AVE_OUT_CTRL_RESET 0x40000100
GP_FSEL5_FSEL58_CLR 0xf8ffffff
USB_GRXSTSP_DEV_EP_NUM_CLR 0xfffffff0
DMA2_TI_DEST_IGNORE_BITS 7:7
A2W_PLLA_ANA1_WIDTH 24
SD_SA_PGEHLD_IDL_RESET 0x0
PM_RSTS_HADDRH_BITS 2:2
SMI_DSR0_RDREQ_LSB 7
MPHI_C1INDCF_ORUN_SET 0x20000000
IMASK1_0 0x7e002014:RW
DMA_TI_S_128 (1<<9)
GP_FSEL0_FSEL08_MSB 26
USB_DOEPDMAB11_MASK 0xffffffff
PM_AVS_STAT_ALERT_SYSTEM_A_MSB 1
I2C_SPI_SLV_IMSC_RXIM_BITS 0:0
DMA_CS_ERROR (1<<8)
HD_VID_CTL_UFEN_LSB 30
CAM0_CAMCAP0_MASK 0xffffffff
DMA13_CS_ERROR_CLR 0xfffffeff
APERF1_BW2_RPEND 0x7ee08068:RO
SMI_DSR0_FSETUP_BITS 22:22
MPHI_HSINDCF_EMPTY_MSB 31
DMA7_DEBUG_LITE_MSB 28
PM_PADS2_MASK 0x0000003f
USB_DTHRCTL_RX_THR_LEN_MSB 26
AVE_IN_STATUS_EVEN_FIELD_CLR 0xfffff7ff
AM_HO_PERPRI 0x1800d010:RW
EMMC_TUNE_STEPS_STD_STEPS_LSB 0
DMA0_TI_DEST_WIDTH_BITS 5:5
USB_GVBUSDRV_MASK 0x0000ffff
V3D_CT1EA_WIDTH 32
APERF1_BW2_WMAX_MASK 0x0ff0ffff
AUX_MU_CNTL_TRN_ENBL 0x02
USB_GINTMSK_FET_SUSP_BITS 22:22
CCP2TX_TAC_BPD_SET 0x00000004
SD_PT1_T_INIT1_LSB 0
CM_VPUCTL_FRAC_LSB 9
UART_LSR_BI_MSB 4
I2C_SPI_SLV_CR 0x7e21400c:RW
GRP_FDBGR 0x1A005740 + 0x08:RW
USB_DIEPTXF7_WIDTH 32
GP_FSEL6_RESET 0000000000
ARM_C0_FULLPERI 0x00000040
A2W_PLLC_ANA_VCO_RANGE_MSB 0
AVE_OUT_CTRL_BYTE_SWAP_BITS 23:19
EMMC_IRPT_MASK_CEND_ERR_CLR 0xfffbffff
SMI_DSW0_WSWAP_MSB 22
I2C_SPI_SLV_FR_RXFE_SET 0x00000002
USB_DTXFSTS2_WIDTH 32
MPHI_C1INDDB_MENDINT_BITS 30:30
SYSAC_DMA_DREQ_CONTROL_MASK 0x0000000f
DMA4_CS_PRIORITY_LSB 16
DMA_TI_TDMODE (1<<1)
GP_AREN1_ARENn32_SET 0xffffffff
SD_DQRCRC1_RISE_SET 0xffff0000
SD_DQLCRC14_RISE_BITS 31:16
EMMC_IRPT_MASK_WRITE_RDY_MSB 4
DMA5_STRIDE_D_STRIDE_BITS 31:16
DMA2_TXFR_LEN_YLENGTH_SET 0x3fff0000
TB_TASK_RXDATA2_MASK 0xffffffff
CAM0_CAMCAP0_RESET 0000000000
TXP_DIM_HEIGHT_RESET 0x0
CCP2TX_TSC_MASK 0x0000000f
DMA5_SOURCE_AD_S_ADDR_LSB 0
DMA14_TI_SRC_INC_BITS 8:8
SD_RWC_RXVAL_BITS 4:0
L1_L1_SANDBOX_PERI_BR_sandbox_peri_SET 0x00001f00
CM_PLLA_LOADCORE_MSB 4
AVE_OUT_STATUS_VSYNC_SET 0x00000200
DMA6_NEXTCONBK_ADDR_BITS 31:5
SD_VIN_ID_LSB 0
USB_DFIFO13_WIDTH 32
PIARBCTL_CAM_THRESHOLD_MSB 5
USB_DTHRCTL_ARB_PRK_EN_BITS 27:27
AVE_OUT_CTRL_INVERT_HSYNC_BITS 14:14
DMA14_TI_SRC_WIDTH_BITS 9:9
ARM_T_RELOAD 0x7E00B000 +0x418:RW
SD_BASE 0x7ee00000
MPHI_C0INDCF_LENGTH_LSB 0
PWM_CTL_RPTL4_BITS 26:26
MS_SEMA_19_WIDTH 1
EMMC_RESP2_RESET 0000000000
CM_INTEN_GAINA_LSB 0
CM_PERIICTL_RESET 0000000000
USB_GINTMSK_ULPI_CK_INT_SET 0x00000100
HDMI_READ_POINTERS_DRFT_FULL_MINUS_BITS 20:20
DMA4_DEBUG_LITE_CLR 0xefffffff
UART_LSR_RESET 0000000000
USB_HCCHAR0_MC_EC_CLR 0xffcfffff
PIXELVALVE2_INTEN_WIDTH 10
JCTRL_MODE (1 << 0)
DMA3_DEST_AD 0x7e007310:RO
USB_GUSBCFG_USB_TRD_TIM_LSB 10
DMA15_TI_DEST_WIDTH_LSB 5
I2CC_INTT (1 << 9)
A2W_PLLA_DIG2R_MASK 0x00ffffff
EMMC_CONTROL0_GAP_STOP_MSB 16
DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
EMMC_IRPT_MASK_ATA_ERR_LSB 29
TS_TSENSCTL_PRWDW_LSB 0
CM_SDCCTL_BUSYD_SET 0x00000100
SD_DQRCRC10_FALL_CLR 0xffff0000
DMA14_CS_ABORT_MSB 30
DMA15_DEBUG_DMA_ID_MSB 15
DMA4_TI_DEST_IGNORE_LSB 7
USB_DVBUSPULSE_PULSE_LSB 0
USB_DIEPDMA3_MASK 0xffffffff
DMA14_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
PIXELVALVE1_STAT_WIDTH 10
GP_FSEL4_MASK 0x3fffffff
EMMC_INTERRUPT_ENDBOOT_BITS 14:14
SMI_DC_DMAEN_SET 0x10000000
USB_DIEPINT0_AHB_ERR_LSB 2
SD_VIN_MULT_BITS 24:24
USB_HCSPLT1_MASK 0xffffffff
HDMI_AN0_RESET 0000000000
DMA8_DEBUG_READ_ERROR_MSB 2
DSI1_STAT 0x7e700038:RW
SH_RSP2_CID_CSD_CLR 0x00000000
USB_HPRT_TST_CTL_LSB 13
HDMI_TX_PHY_HDMI_TX_PHY_CTL_0 (HDMI_BASE_ADDRESS + 0x2c0) + 4:RW
GP_FSEL3_FSEL33_LSB 9
CM_TSENSCTL_BUSY_LSB 7
DMA0_TI_SRC_WIDTH_MSB 9
A2W_PLLD_ANA_SCTL_UPDATE_LSB 3
DMA3_CS_ERROR_MSB 8
TB_TASK_PARAM3_WIDTH 32
DMA1_TI_BURST_LENGTH_LSB 12
SD_SECSRT3_ADDR_MS_RESET 0x0
DMA2_NEXTCONBK_ADDR_LSB 5
MS_SEMA_21_MASK_CLR 0xfffffffe
SH_EDM_WRITE_THRESHOLD_SET 0x00003e00
CM_DSI0PDIV_WIDTH 13
CM_TIMERCTL_FRAC_LSB 9
CM_CAM0CTL_KILL_SET 0x00000020
CM_TD1DIV 0x7e1010dc:RW
SCALER_OLEDCOEF0_MASK 0xffffffff
HDMI_TX_PHY_TX_PHY_PLL_CFG_WIDTH 32
CM_HSMDIV_RESET 0000000000
USB_GINTMSK_MODE_MIS_CLR 0xfffffffd
USB_DCTL_SGNP_IN_NAK_RESET 0x0
PIXELVALVE_INTSTAT_0 0x7e206028:RW
USB_DIEPCTL0 0x7e980900:RW
CAM0_CAMDBWP_WIDTH 32
USB_DIEPCTL2 0x7e980940:RW
USB_DIEPCTL3 0x7e980960:RW
USB_DIEPCTL4 0x7e980980:RW
USB_DIEPCTL5 0x7e9809a0:RW
USB_DIEPCTL6 0x7e9809c0:RW
USB_DIEPCTL7 0x7e9809e0:RW
USB_DIEPCTL8 0x7e980a00:RW
USB_DIEPCTL9 0x7e980a20:RW
TXP_DIM_WIDTH_CLR 0xfffff000
DMA10_CS_END_BITS 1:1
APERF0_BW1_CTRL_BUS_MSB 4
CM_GP1CTL_ENAB_MSB 4
CMI_CAM1_RX0SRC_CLR 0xfffffff3
DMA12_CS_DISDEBUG_BITS 29:29
DMA14_NEXTCONBK_ADDR_LSB 5
DMA11_CS_DREQ_SET 0x00000008
DMA13_DEBUG_LITE_MSB 28
VPU_ARB_CTRL_L2_DELAY_CLR 0xfffffff3
MPHI_CTRL_HATVAL_MSB 0
SD_SF_PHYHOLD_MSB 29
DMA3_CS_END_LSB 1
DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
FPGA_STATUS0_WIDTH 32
DMA7_DEBUG_FIFO_ERROR_BITS 1:1
ASB_CPR_CTRL_CLR_REQ_LSB 0
DMA12_DEST_AD_D_ADDR_LSB 0
UART_LSR_FE_SET 0x00000008
USB_GINTMSK_GIN_N_NAK_EFF_RESET 0x0
USB_GUSBCFG_ULPI_UTMI_SEL_RESET 0x0
SMI_CS_RXD_LSB 29
USB_DIEPCTLn(n) MACRO
SD_DQRCRC15_RISE_RESET 0x0
PM_IMAGE_POWOK_CLR 0xfffffffd
DMA4_CS_ABORT_LSB 30
PIXELVALVE_INTSTAT_x(x) MACRO
CM_SLIMCTL_SRC_LSB 0
I2C_SPI_SLV_IFLS_TXIFPSEL_LSB 6
DMA1_CS_INT_SET 0x00000004
USB_DIEPDMA12 0x7e980a94:RW
DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
SD_CS_SDUP_CLR 0xffff7fff
CM_DSI1ECTL_FRAC_CLR 0xfffffdff
DMA14_SOURCE_AD_MASK 0xffffffff
MS_SEMA_6_RESET 0000000000
USB_DIEPDMA13 0x7e980ab4:RW
A2W_PLLD_ANA_KAIP_KI_MSB 6
USB_DIEPTSIZ0_SUP_CNT_CLR 0x9fffffff
SD_DQLCRC6_RISE_SET 0xffff0000
EMMC_IRPT_EN_INT_C_SET 0x00000800
HDMI_CRP_CFG_RESET 0x08000000
PWMCTL_PWEN1 0
PWMCTL_PWEN2 8
PWMCTL_PWEN3 16
PWMCTL_PWEN4 24
APERF1_BW0_WTRANS_WIDTH 32
MPHI_VERSION_WIDTH 32
APERF0_BW1_ATRANS 0x7e009884:RO
SD_SB_REORDER_MSB 7
PWM_CTL_PWEN2_BITS 8:8
CCP2TX_TPC_WIDTH 16
PM_AUDIO 0x7e100004:RW
DMA14_TI_PERMAP_SET 0x001f0000
A2W_DESCRIPTION "Clock manager PLL control"
L1_IC0_FLUSH_E_WIDTH 32
EMMC_CONTROL0_HCTL_8BIT_LSB 5
V3D_BPOS_MASK 0xffffffff
MPHI_C0INDDB_MENDINT_CLR 0xbfffffff
SCALER_DISPEOLN 0x7e400018:RW
PWM_RNG1_MASK 0xffffffff
TXP_CTRL_DITHER_BITS 13:13
USB_DOEPCTL0_ENA_SET 0x80000000
HDMI_RAM_GCP_7_WIDTH 32
HD_MAI_CTL_EMPTY_CLR 0xfffffbff
TS_TSENSCTL 0x7e212000:RW
GROPCTR_TU1_AXI_REQ_FIFO_FULL 0x18
EMMC_STATUS_RETUNING_REQ_BITS 3:3
USB_HPRT_OVR_CURR_CHNG_BITS 5:5
FPGA_CTRL0_SD_PSU_EN_LSB 4
AUX_MU_BAUD_REG (0x7E215000 +0x068)
IC1_FORCE1_CLR 0x7e002854:RW
USB_HAINTMSK_WIDTH 32
CM_PULSECTL_KILL_MSB 5
L1_IC0_RAS_UNDERFLOW 0x7ee02058:RO
CM_TCNTCTL_BUSY_BITS 7:7
L1_D_CONTROL_MASK 0x0000000f
DMA2_CS_ACTIVE_CLR 0xfffffffe
GP_FSEL6_FSEL63_MSB 11
USB_DIEPCTL0_SET_EVEN_FR_RESET 0x0
DMA7_DEBUG_VERSION_CLR 0xf1ffffff
DMA5_STRIDE_D_STRIDE_SET 0xffff0000
USB_DOEPCTL0_MASK 0xffffffff
L1_D_CONTROL_DC0_FLUSH_CLR 0xfffffffd
VPU_ARB_CTRL_UC 0x7ee04000:RW
SD_SE_T_XSR_CLR 0xffffffc0
A2W_PLLC_ANA_STAT_DATA_LSB 0
CM_PERIADIV 0x7e10101c:RO
GP_PUD 0x7e200094:RW
A2W_PLLA_CTRLR_WIDTH 18
DMA11_TI_DEST_INC_LSB 4
SPI_LTOH_TOH_BITS 3:0
AVE_OUT_CTRL_INVERT_EVEN_FIELD_MSB 16
SMI_CS_TEEN_BITS 8:8
A2W_SMPS_A_VOLTSR_RESET 0000000000
DMA8_DEBUG_DMA_STATE_CLR 0xfe00ffff
DMA10_TXFR_LEN_XLENGTH_SET 0x0000ffff
EMMC_INTERRUPT_SDOFF_ERR_SET 0x00800000
USB_GHWCFG4_EN_B_VALID_FILTER_MSB 23
PCM_CS_A_DMAEN_LSB 9
DMA0_DEBUG_FIFO_ERROR_LSB 1
CCP2TX_TAC_CTATADJ_SET 0xf0000000
A2W_SMPS_CTLA0 0x7e1020a0:RW
A2W_SMPS_CTLA1 0x7e1020a4:RW
A2W_SMPS_CTLA2 0x7e1020a8:RW
USB_HCTSIZ1_WIDTH 32
SD_SE_RL_EN_CLR 0xefffffff
TXP_CTRL_ALPHA_ENABLE_SET 0x00100000
DMA6_DEBUG_LITE_MSB 28
SH_CDIV_CLOCKDIV_SET 0x000007ff
HDMI_RAM_PACKET_11_5 0x7e9025a0:RW
DMA7_DEBUG_DMA_ID_CLR 0xffff00ff
PRM_CS_WIDTH 32
CM_DSI0PCTL_BUSY_CLR 0xffffff7f
MS_ICCLR_1_ICCLR_1_LSB 0
GP_EDS2_EDSn64_MSB 5
DMA4_TXFR_LEN_YLENGTH_SET 0x3fff0000
EMMC_IRPT_EN_READ_RDY_LSB 5
SD_DQRCRC8_RISE_SET 0xffff0000
PM_RSTS_HADDRF_SET 0x00000002
PM_RSTC_HRCFG_SET 0x00300000
APERF0_BW0_RPEND_RESET 0000000000
DMA9_TXFR_LEN_XLENGTH_LSB 0
SH_HSTS_FIFO_ERROR_BITS 3:3
ASB_ISP_M_CTRL_RCOUNT_LSB 4
SYSAC_DBG_PRIORITY_PRIORITY_RESET 0x0
PM_PADS5_I2CMODE_BITS 6:6
DMA1_TXFR_LEN_XLENGTH_BITS 15:0
CM_PLLB_HOLDARM_LSB 1
EMMC_ARG2_RESET 0000000000
GP_FSEL4_WIDTH 30
SYSAC_L2_ARBITER_CONTROL_ALGORITHM_BITS 7:6
USB_DCTL_SGOUT_NAK_RESET 0x0
A2W_SMPS_CTLB1 0x7e1020b4:RW
A2W_SMPS_CTLB2 0x7e1020b8:RW
SMI_D_MASK 0xffffffff
DMA7_TXFR_LEN_XLENGTH_BITS 15:0
SH_HSTS_SDIO_IRPT_MSB 8
SD_SD_T_XP_BITS 18:16
HDMI_DETECTED_VERTB1_MANUAL_VSPO1_LSB 9
SD_DQLCRC7_RISE_SET 0xffff0000
UART_MSR_RI_CLR 0xffffffbf
IMASK7_1 0xffffffff:RW
HDMI_RAM_PACKET_10_4_RESET 0000000000
VCE_STATUS_REASON_MASK 0x1f
SLIM_DMA_DC3_WIDTH 32
DMA13_CONBLK_AD_MASK 0xffffffe0
CM_TSENSCTL_KILL_MSB 5
HD_MAI_CTL_FULL_CLR 0xfffff7ff
PM_PROC_MRDONE_BITS 4:4
SYSAC_V3D_PRIORITY_WIDTH 4
FPGA_STATUS0_HW_ID_BITS 3:0
APERF0_BW0_ATRANS_MASK 0xffffffff
CM_DSI0ECTL_ENAB_MSB 4
USB_GOTGCTL_DEV_HNP_EN_RESET 0x0
CM_GNRICCTL_ENAB_BITS 4:4
GP_FSEL0_FSEL06_CLR 0xffe3ffff
DMA10_DEBUG_VERSION_CLR 0xf1ffffff
SCALER_DISPSTAT_DSP2_IRQ_LSB 3
CM_GP1DIV_MASK 0x00ffffff
L1_D_PRIORITY_c0_l2_priority_BITS 3:0
USB_HCINT0_AHB_ERR_BITS 2:2
SD_RWC_RXOVR_MSB 7
GRFCCV0 0x1A005400 + 0x40:RW
PCM_MODE_A_FRXP_BITS 25:25
OTP_JTAG_DEBUG_KEY_ROW 8
FPGA_CTRL0_SPI1_SEL_MSB 10
CAM1_CAMDAT3_MASK 0xffffffff
CM_PERIIDIV_DIV_BITS 12:12
A2W_SMPS_CTLC2 0x7e1020c8:RW
A2W_SMPS_CTLC3 0x7e1020cc:RW
CM_GP1CTL_SRC_BITS 3:0
I2CC_CLEAR (3 << 4)
DMA5_TI_WAIT_RESP_LSB 3
PCM_DREQ_A_WIDTH 31
USB_GINTMSK_INCOMPL_P_MSB 21
APERF1_BW2_CTRL_RESET_MSB 31
CM_VECDIV_DIV_LSB 12
SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_RESET 0x0
PM_PROC_CFG_SET 0x007f0000
PM_DUMMY_ONE_SET 0x00000001
CM_DSI0PCTL_BUSYD_BITS 8:8
USB_GHWCFG4_WIDTH 32
DMA3_DEBUG 0x7e007320:RW
DMA15_DEST_AD_WIDTH 32
APERF1_BW2_ATRANS_MASK 0xffffffff
CM_INTEN_RESUS_SET 0x00400000
CM_EVENT_FGAINC_MSB 12
WSE_CONTROL 0x7e8060c4:RW
EMMC_RESP0_WIDTH 32
USB_GINTMSK_IEP_INT_LSB 18
USB_DIEPCTL7_MASK 0xffffffff
CM_TSENSCTL_RESET 0000000000
GROPCTR_PBE_STCL_TEST_FAIL 0x20
DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
SCALER_DISPDITHER_MASK 0xffffffff
SMI_FD_RESET 0000000000
MPHI_C1INDS_HANDLE_SET 0x1fe00000
CM_DSI1PCTL_ENAB_CLR 0xffffffef
PIXELVALVE2_APB_ID 0x70697876
PM_STATUS_RESET 0000000000
AVE_IN_CURRENT_ADDRESS_CUR_ADDR_CLR 0x00000000
TB_BOOT_STATUS_CPRMAN_PROGRAMMED_MSB 0
EMMC_INTERRUPT_WIDTH 32
USB_DIEPINT0_TX_FIFO_UNDRN_MSB 8
DMA1_STRIDE 0x7e007118:RO
DMA10_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
TS_TSENSCTL_CLR_INT_MSB 7
SD_CS_STOP_MSB 7
USB_DIEPINT0_TXF_EMPTY_MSB 7
ASB_V3D_M_CTRL_CLR_ACK_LSB 1
MPHI_OUTDS_WORDS_MSB 20
DMA4_CS_RESET_BITS 31:31
MS_SEMA_28_MASK_CLR 0xfffffffe
DMA4_TI_SRC_DREQ_LSB 10
HD_MAI_CTL_ENABLE_RESET 0x0
CM_CAM1CTL_FRAC_MSB 9
USB_DOEPCTL2_WIDTH 32
SLIM_MC_OUT_CON_RESET 0000000000
A2W_PLLA_DIG2_MASK 0x00ffffff
CM_SLIMCTL_BUSYD_BITS 8:8
DMA7_CS_ERROR_CLR 0xfffffeff
CM_PLLA_HOLDPER_MSB 7
FPGA_CTRL0_TV_ACTIVITY_MSB 13
DMA0_CS_END_LSB 1
A2W_PLLC_PER_DIV_CLR 0xffffff00
USB_HAINTMSK_MASK 0xffffffff
SD_DQRCRC13_RISE_BITS 31:16
USB_DIEPINT10_MASK 0xffffffff
EMMC_FORCE_IRPT_CMD_DONE_MSB 0
CMI_CAM0_HSSRC_MSB 1
USB_GAHBCFG_P_TXF_EMP_LVL_SET 0x00000100
USB_HCINT0_NAK_MSB 4
MPHI_HSINDS_HANDLE_MSB 28
I2C_SPI_SLV_MIS_RESET 0000000000
USB_HCFG_LS_PHY_CLK_SEL_RESET 0x0
SD_DQRCRC12_RISE_RESET 0x0
DMA9_CS_ACTIVE_LSB 0
PM_PADS2_RESET 0x0000001b
DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
JC1S 0x7e005000 + 0x5C:RW
L1_BASE 0x7ee02000
A2W_PLLB_ARM_BYPEN_MSB 9
DMA3_CS_RESET_MSB 31
BOOTROM_RAM_LENGTH ( 1024 * 2 )
SD_SD_T_RPab_SET 0xf0000000
GP_SET2_SETn64_SET 0x0000003f
DSI1_APB_ID 0x64736934
USB_DCFG_PER_FR_INT_CLR 0xffffe7ff
SD_CS_IDLE_MSB 9
CM_PLLTCNT0_CNT_CLR 0xff000000
SYSAC_L2_ARBITER_CONTROL_MASK 0x0000ffff
GP_HEN0 0x7e200064:RW
GP_HEN1 0x7e200068:RW
PWM_STA_WERR1_CLR 0xfffffffb
DMA6_CONBLK_AD_MASK 0xffffffe0
HDMI_FIFO_CTL_MASTER_SLAVE_N_LSB 0
DMA10_TI_BURST_LENGTH_LSB 12
EMMC_HWCAP0_BUS64_CLR 0xefffffff
VEC_CGMSAE_RESET 0x7e806040:RW
USB_DIEPTSIZn(n) MACRO
SPI_BASE 0x7e204000
PRM_CV 0x7e20d004:RW
PWM_CTL_POLA2_CLR 0xffffefff
APERF1_BW1_RTRANS_MASK 0xffffffff
GROPCTR_FBC_EZ_FE_FETCHES 0x3C
APERF0_BW2_CTRL_BUS_CLR 0xffffffe0
HDMI_HORZA 0x7e9020c4:RW
HDMI_HORZB 0x7e9020c8:RW
USB_DIEPINT4_WIDTH 32
HDMI_SCHEDULER_CONTROL_VSYNC_PHYST_EN_CLR 0xfffdffff
HDMI_READ_POINTERS_MASK 0x7fffffff
L1_D_PRIORITY_c0_uc_priority_LSB 4
USB_DIEPCTL0_ENA_BITS 31:31
SYSAC_TRANS_PRIORITY_P_PRIORITY_RESET 0x0
DMA5_CS_PRIORITY_LSB 16
A2W_PLLH_DIG3_RESET 0000000000
PWM_STA_WERR1_LSB 2
EMMC_FORCE_IRPT_DCRC_ERR_SET 0x00200000
SLIM_DCC6_CON_WIDTH 32
AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_LSB 0
HDCP_KEY_CTL_DISHDCP_RESET 0x0
IC1_WAKEUP_RESET 0x10000000
EMMC_BUS_CTRL_IRQ_PINS_BITS 5:3
I2C_SPI_SLV_DEBUG1_MASK 0x03ffffff
DMA15_TI_SRC_INC_BITS 8:8
DMA12_TI_WAITS_SET 0x03e00000
USB_DOEPDMA10_WIDTH 32
DMA8_CONBLK_AD_SCB_ADDR_BITS 31:5
MS_SEMA_13_RESET 0000000000
PWM_CTL_MODE2_MSB 9
MS_SEMA_4_WIDTH 1
SD_DQLCRC11_FALL_LSB 0
USB_HCSPLT1_WIDTH 32
I2C_SPI_SLV_IMSC 0x7e214018:RW
DMA14_CS_DISDEBUG_CLR 0xdfffffff
CM_INTEN_GAIND_LSB 3
DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
DMA10_DEBUG_RESET 0000000000
A2W_PLLA_ANA3_MASK 0x00ffffff
HDMI_RAM_PACKET_11_6_WIDTH 32
USB_DTHRCTL_ARB_PRK_EN_MSB 27
PM_PADS6_DRIVE_BITS 1:0
CM_AVEOCTL_FRAC_MSB 9
CCP2TX_TBA_ADDR_CLR 0xc0000000
L2_CONT_OFF_l2_disable_CLR 0xfffffffe
APERF1_BW2_ATWAIT_RESET 0000000000
PCM_DREQ_A_RX_MSB 6
SD_SD_T_RCD_BITS 3:0
L1_IC1_PRIORITY_RESET 0x000034af
DMA14_NEXTCONBK_ADDR_BITS 31:5
DMA6_TI_SRC_IGNORE_LSB 11
MPHI_C1INDCF_LENGTH_LSB 0
GROPCTR_FBC_CZ_LINE_FLUSHES 0x23
SH_TOUT_RESET 0x00a00000
L1_L1_SANDBOX_PERI_BR_sandbox_peri_BITS 12:8
CAM0_CAMIDI0_RESET 0000000000
DMA10_CS_DREQ_STOPS_DMA_SET 0x00000020
GP_HEN2_MASK 0x0000003f
DMA11_TI_WAITS_SET 0x03e00000
EMMC_CMDTM_TM_MULTI_BLOCK_MSB 5
DMA2_TI_SRC_WIDTH_CLR 0xfffffdff
DMA7_CS_ABORT_BITS 30:30
PM_PADS4_POWOK_SET 0x00000020
PWM_STA_RERR1_CLR 0xfffffff7
TXP_CTRL_BWE_BITS 19:16
DMA2_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
VEC_CGMSAE_REVID_MASK 0xffffffff
A2W_PLLD_DSI0_BYPEN_CLR 0xfffffdff
PCMRXC PCM_BASE_ADDRESS + 0x0C:RW
A2W_PLLB_SP0_CHENB_CLR 0xfffffeff
USB_GOTGINT_DBNCE_DONE_RESET 0x0
UNICAM_DLT(x) MACRO
CM_EMMCDIV_DIV_BITS 15:4
EMMC_EXRDFIFO_EN_ENABLE_SET 0x00000001
SYSAC_L2_ARBITER_CONTROL_THRESHOLD_MSB 5
SD_SF_PHYHOLD_LSB 29
USB_GHWCFG4_EN_PWROPT_RESET 0x0
USB_DIEPINT0_EP_DISBLD_SET 0x00000002
CMPRE2 0x7C:RW
CMPRE3 0x7C:RW
PWM_RNG3_MASK 0000000000
SD_TMC_TSTCLK_LSB 0
MS_SEMA_3_MASK_BITS 0:0
CMPREC 0x7C:RW
CMI_CAM1_RX1SRC_MSB 5
USB_DOEPINT0_BNA_SET 0x00000200
SCALER_DISPECTRL_POSTED_STATUS_MSB 14
PCM_GRAY_CLR_SET 0x00000002
USB_DCTL_SGOUT_NAK_SET 0x00000200
TXP_CTRL_MASK 0xffffffff
USB_DIEPINT0_OUT_PKT_ERR_RESET 0x0
GP_SET1_SETn32_MSB 31
MS_MBOX_2_MBOX_CLR 0x00000000
UART_LCR_SBC_MSB 6
AJB_OUT_LS 0x000000
DMA0_DEBUG_DMA_STATE_SET 0x01ff0000
USB_DIEPCTL0_CNAK_MSB 26
USB_DIEPDMAB9_WIDTH 32
DSI0_CTRL_CTRL0_CLR 0xfffffffe
DMA9_TI_DEST_INC_BITS 4:4
HDMI_SCHEDULER_CONTROL_VSYNC_RESET_VAL_LSB 18
MPHI_C0INDCF_HANDLE_CLR 0xf00fffff
PM_PADS0_SLEW_CLR 0xffffffef
SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_CLR 0xfffffffc
I2C_SPI_SLV_VCSTAT_DATA_BITS 3:0
USB_GPVNDCTL_REG_DATA_CLR 0xffffff00
GP_PUDCLK1_RESET 0000000000
I2C_SPI_SLV_FR_RXFF_LSB 3
DMA3_CS 0x7e007300:RW
DMA8_DEBUG_LITE_BITS 28:28
CM_PLLTCNT3_MASK 0x00ffffff
EMMC_STATUS_DAT_LEVEL1_MSB 28
AVE_OUT_CTRL_INVERT_VSYNC_BITS 15:15
CM_DSI1PCTL_RESET 0000000000
CM_CAM1CTL_ENAB_LSB 4
ST_C0_WIDTH 32
USB_DIEPDMA5_WIDTH 32
A2W_PLLD_FRAC_WIDTH 20
SD_RWC_WRTVAL_LSB 8
AJB_OUT_MS 0x000040
USB_DIEPCTL14_MASK 0xffffffff
SD_SC_WL_BITS 2:0
EMMC_INTERRUPT_CBAD_ERR_BITS 19:19
DMA15_TI_WAITS_MSB 25
DMA9_TXFR_LEN_XLENGTH_BITS 15:0
HDMI_RAM_PACKET_11_2_MASK 0xffffffff
SMI_DSW2_WHOLD_SET 0x003f0000
CM_TD1CTL_SRC_BITS 3:0
USB_GOTGINT 0x7e980004:RW
STC3_0 0x7e003018:RW
STC3_1 0xffffffff:RW
I2C_SPI_SLV_DR_UE_BITS 9:9
HDMI_RAM_PACKET_10_2_WIDTH 32
CM_GNRICCTL 0x7e101000:RW
A2W_PLLB_CTRL_NDIV_LSB 0
DMA13_TI_INTEN_MSB 0
A2W_PLLB_ANA_STAT_DATA_MSB 11
DMA3_TXFR_LEN 0x7e007314:RO
SLIM_DCC6_PROT 0x7e2102d0:RW
EMMC_EXRDFIFO_CFG_WIDTH 3
SMI_DCS_EANBLE_LSB 0
IC0_VADDR_RESET 0000000000
A2W_HDMI_CTL3R_MASK 0x00ffffff
DMA14_CS 0x7e007e00:RW
GP_FEN1_FENn32_CLR 0x00000000
HDMI_RAM_GCP_1_RESET 0000000000
GP_LEV0_RESET 0000000000
MS_SEMA_3_RESET 0000000000
SD_SECEND2_ADDR_LS_SET 0x00001fff
EMMC_CONTROL0_SPI_MODE_MSB 20
DMA0_CS_PRIORITY_MSB 19
HDMI_FIFO_CTL_ON_VB_LSB 7
CM_PCMCTL_MASH_LSB 9
HDMI_TST_AN1_RESET 0000000000
TB_BOOT_OPT_FAST_OPT_SET 0x00000001
USB_DTXFSTS11_MASK 0xffffffff
USB_HCINT0_BBL_ERR_MSB 8
GP_CLR0_CLRn0_LSB 0
STC3_x(x) MACRO
GPCLR2 0x7e200000 + 0x30:RW
EMMC_INTERRUPT_CARD_OUT_LSB 7
PIARBCTL_CAM_LIMIT_BITS 1:0
DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
EMMC_IRPT_MASK_SDOFF_ERR_MSB 23
PM_PROC_CFG_BITS 22:16
DMA_CS_DREQ_PAUSED (1<<5)
SMI_DSW2_WWIDTH_CLR 0x3fffffff
DMA15_TI_MASK 0x07fffffb
DMA7_CS_PANIC_PRIORITY_BITS 23:20
CM_GP1DIV_DIV_SET 0x00ffffff
EMMC_CONTROL2_TUNED_CLR 0xff7fffff
CM_V3DCTL_WIDTH 10
DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
CMI_CAM1_RX2SRC_MSB 7
EMMC_STATUS_RESET 0x1ff00000
ISRC1_0 0x7e00200c:RO
ISRC1_1 0xffffffff:RW
DMA11_NEXTCONBK 0x7e007b1c:RO
AVE_IN_CTRL_LOW_PRIORITY_LSB 16
SH_RSP3_WIDTH 32
EMMC_HWCAP1_DDR50_CLR 0xfffffffb
DMA14_NEXTCONBK 0x7e007e1c:RO
AVE_IN_CTRL_EN_OVERRUN_ABORT_MSB 15
AVE_IN_STATUS_CSYNC_FIELD_CLR 0xffffdfff
V3D_FDBGB_MASK 0xffffffff
SMI_CS_MASK 0xff00ffff
DMA15_TI_DEST_WIDTH_SET 0x00000020
DMA1_NEXTCONBK 0x7e00711c:RO
V3D_IDENT1_WIDTH 32
PM_CAM0_LDOLPEN_LSB 1
UART_LCR_SP_BITS 5:5
DMA_ENABLE_EN3_LSB 3
DMA7_SOURCE_AD_WIDTH 32
EMMC_IRPT_MASK_DCRC_ERR_LSB 21
I2C_SPI_SLV_CR_ENSTAT_LSB 5
PIXELVALVE2_HORZA_MASK 0xffffffff
SCALER_DISPSTAT_DSP2_IRQ_SET 0xfffffff8
FPGA_CTRL0_SW_SPI_CS_MSB 8
SYSAC_DBG_PRIORITY_PRIORITY_LSB 0
CM_HSMCTL_BUSY_MSB 7
DMA7_TXFR_LEN_XLENGTH_CLR 0xffff0000
CM_PLLD_ANARST_BITS 8:8
PM_AVS_STAT_ALERT_V3D_G_CLR 0xfffffff7
DMA1_TI_DEST_DREQ_LSB 6
DMA3_CS_RESET_LSB 31
USB_DFIFO3_MASK 0xffffffff
CM_AVEOCTL_ENAB_LSB 4
DMA12_TI_DEST_INC_LSB 4
CM_PULSECTL_WIDTH 10
DMA11_TXFR_LEN 0x7e007b14:RO
USB_DFIFO0_WIDTH 32
EMMC_CMDTM_CMD_IXCHK_EN_SET 0x00100000
CCP2RC CCP2_BASE_ADDRESS + 0x00:RW
AVE_IN_STATUS_CURRENT_BUF_LSB 17
A2W_PLLD_DSI0_DIV_MSB 7
VEC_DAC_TEST 0x7e80620c:RW
CMI_CAM0_RX1SRC_BITS 5:4
FPGA_STATUS0_MASK 0xfff800ff
CCP2RS CCP2_BASE_ADDRESS + 0x04:RW
VEC_SCHPH 0x7e806108:RW
MPHI_HSINDCF_LENGTH_SET 0x000fffff
EMMC_STATUS_DAT_ACTIVE_BITS 2:2
PM_PADS0_WIDTH 6
CM_UARTCTL_BUSY_SET 0x00000080
SCALER_DISPECTRL_SECURE_MODE_SET 0x80000000
L1_D0_RD_MISSES_MASK 0000000000
SD_SECSRT1_ADDR_LS_BITS 12:1
A2W_PLLA_ANA_KAIPR_RESET 0x0000033a
DMA12_TI_SRC_WIDTH_CLR 0xfffffdff
DMA10_TXFR_LEN_XLENGTH_CLR 0xffff0000
APERF0_BW1_ATWAIT_MASK 0xffffffff
CM_GNRICCTL_BUSY_CLR 0xffffff7f
FPGA_CTRL0_DISP_BUFFER_SET 0x00000800
CM_TIMERDIV_DIV_SET 0x0003ffff
SMI_CS_ENABLE_MSB 0
SD_CS_EXCEPTION_CLR 0xff7fffff
PM_IMAGE_MRDONE_MSB 4
USB_DIEPCTL0_MASK 0xffffffff
EMMC_FORCE_IRPT_WRITE_RDY_SET 0x00000010
APERF1_BW0_RPEND_RESET 0000000000
SYSAC_V3D_LIMITER_SPARE_RESET 0x0
USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_BITS 25:24
AVE_OUT_CTRL_INVERT_DSYNC_LSB 18
GRPFCOL 0x1A005600 + 0x64:RW
DMA0_CS_PAUSED_BITS 4:4
PM_XOSC_USESEC_LSB 0
SD_DMRCRC0_HIGH_BITS 31:16
L1_IC1_BP_MISSES_WIDTH 0
DMA3_STRIDE_D_STRIDE_LSB 16
UART_LCR_SBC_BITS 6:6
A2W_PLLA_ANA_VCOR_MASK 0x00000001
PM_CAM0_CTRLEN_LSB 0
DMA11_CONBLK_AD_SCB_ADDR_BITS 31:5
CM_VPUDIV_DIV_BITS 23:4
SMI_CS_PAD_MSB 7
SLIM_DCC0_PA1 0x7e210204:RW
SYSAC_SRC_ARBITER_CONTROL 0x7e009048:RW
SCALER_DISPLIST0 0x7e400020:RW
GP_FSEL4_FSEL41_CLR 0xffffffc7
SCALER_DISPLIST2 0x7e400028:RW
I2C_SPI_SLV_DR_TXBUSY_BITS 16:16
I2C_SPI_SLV_RSR_TXDMAPREQ_BITS 2:2
CM_TD0DIV_DIV_LSB 0
SD_SECEND1 0x7ee00048:RW
AVE_OUT_APB_ID 0x61766538
APERF1_BW0_ATRANS_MASK 0xffffffff
SD_SE_RL_EN_BITS 28:28
CCP2TC 0x7e001000:RW
CCP2TD 0x7e001024:RW
CM_TSENSDIV_MASK 0x0001f000
SD_DQRCRC1_FALL_SET 0x0000ffff
DMA7_DEBUG_READ_ERROR_LSB 2
EMMC_INTERRUPT_INT_A_SET 0x00000200
ASB_H264_S_CTRL_RCOUNT_MSB 13
MPHI_C0INDFS_DFIFOLVL_SET 0x0000ffff
SPI_CLK_CDIV_MSB 15
PCM_GRAY_RESET 0000000000
CCP2TS 0x7e001004:RW
DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
USB_DIEPINT0_EP_DISBLD_RESET 0x0
SD_SECEND2 0x7ee00050:RW
SD_CS_STATEN_CLR 0xffffffbf
L1_L1_SANDBOX_START4_CTRL_LSB 0
MPHI_MOUTFS_UFLOW_MSB 31
SD_CS_STALLING_LSB 24
MS_SEMA_31_MASK_SET 0x00000001
HDMI_RAM_PACKET_13_6_MASK 0xffffffff
VPU_ARB_CTRL_UC_LIMIT_BITS 1:0
MS_MBOX_0_MBOX_MSB 31
MPHI_CTRL_ENABLE_LSB 31
USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_MSB 31
USB_GRXSTSP 0x7e980020:RW
USB_DIEPCTL0_STALL_LSB 21
DMA9_CS_PRIORITY_BITS 19:16
MPHI_C0INDDB_TENDINT_LSB 29
SD_SECEND3 0x7ee00058:RW
USB_GUSBCFG_FORCE_DEV_MODE_LSB 30
SMI_DSW0_WSTROBE_BITS 6:0
I2CDIV_x(x) MACRO
TS_TSENSCTL_RSTB_CLR 0xfffffffd
I2C_SPI_SLV_DEBUG1_DATA_CLR 0xfc000000
EMMC_IRPT_MASK_DEND_ERR_MSB 22
AVE_IN_OUTSTANDING_BUFF1_RESET 0000000000
SMI_DSR3_RPACEALL_CLR 0xffff7fff
DMA0_CS_INT_MSB 2
A2W_PLLA_ANA_KAIP_KI_BITS 6:4
USB_HCCHAR0_MC_EC_MSB 21
AVE_OUT_STATUS_HFRONT_PORCH_MSB 4
A2W_SMPS_A_MULTI_WIDTH 0
CM_EVENT_FGAINB_LSB 11
GP_FSEL3_FSEL30_SET 0x00000007
APERF1_GEN_CTRL_RESET_BITS 1:1
ASB_CPR_CTRL_CLR_ACK_CLR 0xfffffffd
DMA12_CS_PANIC_PRIORITY_MSB 23
PWM_CTL_MSEN3_LSB 23
SMI_DSR1_RSTROBE_LSB 0
TB_TASK_PARAM3_MASK 0xffffffff
GP_FSEL5_MASK 0x3fffffff
SD_SA_PGEHLDE_CLR 0xfffffeff
DMA5_TI_SRC_DREQ_LSB 10
DMA2_CS_PAUSED_LSB 4
USB_GUSBCFG_PHY_SEL_MSB 6
PIXELVALVE2_BASE 0x7e807000
SD_SECEND2_ADDR_LS_CLR 0xffffe000
CM_BURSTCTL_ENAB_LSB 4
VCE_STATUS 0x7f000000 + 0x140000:RW
DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
HDMI_RAM_PACKET_8_3_MASK 0xffffffff
PWM_STA_RERR1_MSB 3
A2W_PLLA_FRAC_WIDTH 20
CM_PWMCTL_SRC_LSB 0
HDMI_MAI_FORMAT_WIDTH 32
HDMI_RAM_PACKET_2_2_MASK 0xffffffff
MPHI_HSINDCF_LENERR_BITS 30:30
CM_BURSTCTL_KILL_BITS 5:5
A2W_PLLA_ANA_SSCS_STEP_MSB 15
USB_DOEPTSIZ0_SUP_CNT_BITS 30:29
DMA_DEBUG_FIFO_ERR (1<<1)
USB_PCGCR_STOP_PCLK_SET 0x00000001
CM_EVENT_FLOSSD_SET 0x00020000
L2_STALLS 0x7ee0111c:RO
OTP_CTRL_HI_REG 0x7e20f00c:RW
A2W_PLLD_ANA_SSCL 0x7e102250:RW
A2W_SMPS_A_MODE_BSTPWMB_BITS 0:0
PM_GRAFX_MRDONE_LSB 4
USB_GGPIO 0x7e980038:RW
CM_OTPCTL_KILL_SET 0x00000020
A2W_XOSC_CPR 0x7e102290:RW
USB_GHWCFG4_EN_DESC_DMA_RESET 0x0
DMA9_TXFR_LEN_MASK 0x0000ffff
EMMC_HWCAP0_AINT_SET 0x20000000
HDMI_VERTB0_MANUAL_VSPO0_CLR 0xffc001ff
USB_PCGCR_RST_PDWN_MODULE_SET 0x00000008
EMMC_STATUS_WRT_PROTECT_CLR 0xfff7ffff
ARM_IF_VP1HALT 0x00000045
SMI_DSW0_WFORMAT_CLR 0xff7fffff
A2W_PLLA_ANA_SCTL_RESET_MSB 4
DMA5_TI_SRC_IGNORE_MSB 11
TH1CS 0x1A008000 + 0x00:RW
PM_AUDIO_RSTN_LSB 21
USB_GOTGCTL_HNP_REQ_RESET 0x0
ARM_MC_IHAVESPACEIRQEN 0x00000002
MS_SEMA_2_MASK_BITS 0:0
DMA7_DEBUG_DMA_ID_BITS 15:8
A2W_SMPS_L_SCA_MASK 0x00000fff
PWM_STA_BERR_MSB 8
DMA0_CS_ABORT_MSB 30
A2W_HDMI_CTL_RCAL_SELDIV_BITS 5:4
APERF0_BW0_WTWAIT 0x7e009854:RO
TB_JTB_CONFIG_TRSTN_SET 0x00004000
SD_DQRCRC8_FALL_RESET 0x0
TB_TASK_PARAM2_WIDTH 32
AVE_IN_MAX_TRANSFER_MAX_TRANSFER_MSB 31
CM_OSCFREQI_WIDTH 8
CM_PLLD_LOADDSI0_BITS 0:0
USB_DOEPCTL0_TYPE_BITS 19:18
L1_D_PRIORITY_c1_uc_priority_LSB 20
HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT_CLR 0xffff7fff
DMA11_TI_DEST_DREQ_LSB 6
DMA8_CS_ACTIVE_MSB 0
DMA6_CS_PRIORITY_LSB 16
HDMI_HDCP_KEY_1_RESET 0000000000
DMA1_CS_PANIC_PRIORITY_CLR 0xff0fffff
BOOTROM_ROM_LENGTH ( 1024 * 32 )
USB_GHWCFG3_RM_OPT_FEATURES_RESET 0x0
L1_L1_SANDBOX_START7_WIDTH 30
USB_GOTGCTL_SES_REQ_SCS_BITS 0:0
UART_LCR_DTR_SET 0x00000001
ARM_IE_VP0HALT 0x00000010
CM_PLLD_LOADDSI1_SET 0x00000004
DMA_ENABLE_EN8_SET 0x00000100
SMI_CS_RXF_BITS 31:31
DMA13_CONBLK_AD_SCB_ADDR_LSB 5
DMA4_TI_TDMODE_SET 0x00000002
DMA0_NEXTCONBK_ADDR_MSB 31
SD_TMC_IPSEL_RESET 0x0
DMA14_DEBUG_DMA_STATE_BITS 24:16
PWM_CTL_SBIT1_CLR 0xfffffff7
CM_UARTCTL_BUSY_LSB 7
SD_MR_RW_CLR 0xefffffff
PM_GNRIC_MASK 0x007f1fff
USB_HCCHAR0_LSPD_DEV_MSB 17
USB_HCINT0_ACK_CLR 0xffffffdf
DMA0_DEBUG_READ_ERROR_SET 0x00000004
EMMC_IRPT_EN_CTO_ERR_BITS 16:16
EMMC_IRPT_MASK_ENDBOOT_MSB 14
PWM_DAT4_WIDTH 0
USB_DOEPTSIZ0_SUP_CNT_SET 0x60000000
DMA5_TI_WAITS_SET 0x03e00000
USB_HCTSIZ0_XFER_SIZE_MSB 18
PM_AVS_STAT_ALERT_PERI_A_MSB 0
CCP2TX_TS_TII_CLR 0xfffdffff
SMI_DSR2_RPACE_CLR 0xffff80ff
MPHI_C1INDS_WORDS_SET 0x001fffff
USB_DOEPDMAB1_MASK 0xffffffff
SH_CMD_COMMAND_LSB 0
SD_SE_T_FAW_SET 0x0003f000
SD_DQLCRC6_FALL_SET 0x0000ffff
EMMC_HWCAP0_SLOT_TYPE_LSB 30
ASB_H264_M_CTRL_EMPTY_LSB 2
MPHI_TXAXICFG_TXPPRIO_BITS 7:4
HD_MAI_CTL_RST_MAI_MSB 0
CCP2TX_TAC 0x7e001008:RW
SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_LSB 3
L1_IC0_PRIORITY_WIDTH 16
CM_DPIDIV_RESET 0000000000
CAM0_CAMIDCA_RESET 0000000000
A2W_PLLH_ANA_VCOR_WIDTH 1
CM_INTEN_FLOSSB_CLR 0xffff7fff
CAM0_CAMDAT0 0x7e800018:RW
A2W_PLLH_ANA_SCTL_SEL_SET 0x00000007
DMA12_CS_END_CLR 0xfffffffd
APERF1_BW0_CTRL_EN_RESET 0x0
PM_USB_RESET 0000000000
DMA6_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
CM_VECCTL_BUSYD_SET 0x00000100
CM_TCNTCTL_BUSY_MSB 7
USB_DOEPINT15_WIDTH 32
DMA10_DEBUG_DMA_ID_BITS 15:8
DMA7_DEBUG_FIFO_ERROR_MSB 1
MPHI_HSINDDB_LENGTH_LSB 0
CM_CKSM_STEP_MSB 21
USB_DTHRCTL_ISO_THR_EN_LSB 1
DMA_ENABLE_WIDTH 15
HDMI_13_AUDIO_CFG_1_RESET 0x000000c8
SCALER_DISPECTRL_Y_NE_CTRL_LSB 28
USB_HPRT_OVR_CURR_ACT_SET 0x00000010
CM_TD0DIV_WIDTH 24
CCP2TX_TBA 0x7e00101c:RW
CM_EVENT_GAINB_SET 0x00000002
CM_TDCLKEN_MASK 0x00003fff
AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_BITS 31:0
RESET_CONTROLLER_BASE RS_BASE
WSE_WSS_DATA 0x7e8060c8:RW
EMMC_CMDTM_TM_DMA_EN_MSB 0
MPHI_INTSTAT_RX0TEND_BITS 4:4
HDMI_DETECTED_HORZA_MANUAL_HAP_MSB 12
EMMC_IRPT_EN_READ_RDY_CLR 0xffffffdf
I2C_SPI_SLV_MIS_BEMIS_BITS 2:2
AVE_OUT_CR_COEFF_RED_COEFF_CLR 0xc00fffff
L1_IC1_CONTROL_DISABLE_SET 0x00000001
DMA2_TI_PERMAP_LSB 16
PM_RSTS_HADPOR_MSB 12
DMA8_DEST_AD_D_ADDR_MSB 31
USB_GINTMSK_EOPF_BITS 15:15
HD_MAI_THR_PANICHIGH_CLR 0xc0ffffff
GP_AREN0_ARENn0_MSB 31
SD_DQRCRC9_RISE_BITS 31:16
PIARBCTL_CAM_ALGORITHM_MSB 7
CM_SDCCTL_SRC_LSB 0
MPHI_INTCTRL_RX0DISC_MSB 0
MPHI_C1INDCF_HANDLE_CLR 0xf00fffff
USB_DOEPCTL11_MASK 0xffffffff
DMA6_DEBUG_DMA_STATE_LSB 16
GP_AFEN2_AFENn64_LSB 0
TB_JTB_CONFIG_INV_CLK_CLR 0xffffff7f
EMMC_HWCAP1_SPI_MODE_CLR 0xfeffffff
MPHI_HSINDFS_CFIFOLVL_MSB 31
SMI_DSW2_WFORMAT_LSB 23
EMMC_HWCAP0_SDMA_SET 0x00400000
DMA9_CS_ACTIVE_CLR 0xfffffffe
HDMI_RAM_PACKET_4_6_MASK 0xffffffff
USB_DIEPCTL0_SNP_CLR 0xffefffff
SMI_FD_FCNT_BITS 5:0
SD_DQRCRC8_FALL_SET 0x0000ffff
DMA7_TI_INTEN_MSB 0
APERF0_BASE 0x7e009800
HDMI_TX_PHY_SPREAD_SPECTRUM_RESET 0x00003c00
PWM_STA_STA4_CLR 0xffffefff
EMMC_HWCAP1_RETUNE_TMR_LSB 8
USB_GRXFSIZ_GRXF_DEP_RESET 0x0
SMI_DSR2_RSETUP_LSB 24
DMA8_TI_WAIT_RESP_SET 0x00000008
SD_SECSRT3_ADDR_LS_MSB 12
I2C_SPI_SLV_RSR_UE_LSB 1
A2W_PLLD_CORE_WIDTH 10
VCE_SIM_DEBUG_OPTIONS 0x7f000000 + 0x140100:RW
DMA4_TI_WAITS_BITS 25:21
MS_SEMA_26_MASK 0x00000001
CM_DSI0PCTL_BUSY_BITS 7:7
ARM_2_MAIL0_STA (0x7E00B000 +0xA00)+0x98:RW
DMA2_SOURCE_AD_S_ADDR_BITS 31:0
CM_CKSM_FRCE_MSB 15
CCP2TX_TDL 0x7e001020:RW
DMA1_CS_PANIC_PRIORITY_SET 0x00f00000
MPHI_CTRL_DIRECT_BITS 4:4
SD_SECSRT3_EN_CLR 0xfffffffe
A2W_PLLD_ANA_SCTL_RESET_SET 0x00000010
USB_GINTMSK_EP_MIS_CLR 0xfffdffff
A2W_PLLD_ANA_VCO_RANGE_LSB 0
USB_HCCHAR0_CH_ENA_BITS 31:31
DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
DMA1_CS_PRIORITY_MSB 19
DMA4_DEST_AD_D_ADDR_BITS 31:0
USB_HCDMA5_WIDTH 32
DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
A2W_PLLH_PIX_BYPEN_LSB 9
AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_LSB 31
DSI0_PHY_AFEC0 0x7e209064:RW
DSI0_PHY_AFEC1 0x7e209068:RW
HDMI_FIFO_CTL_RECENTER_CLR 0xffffffbf
DMA11_TI_BURST_LENGTH_CLR 0xffff0fff
APERF1_BW1_CTRL_WIDTH 32
OTP_CODE_SIGNING_FLAG_ROW ((((((((((((((((((((8 +4)+4)+1)+1)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)
HDMI_VERTA0_MANUAL_VFP0_BITS 19:13
EMMC_INTERRUPT_INT_A_BITS 9:9
GP_FSEL1_FSEL10_BITS 2:0
USB_HCINT0_BBL_ERR_SET 0x00000100
HDMI_RAM_PACKET_9_4_WIDTH 32
HDMI_RAM_PACKET_6_7_WIDTH 32
SCALER_DISPSTAT_DMA_ERR_BIT1_CLR 0x00007fff
USB_GINTMSK_USB_RST_MSB 12
DMA3_TI_DEST_WIDTH_LSB 5
A2W_SMPS_C_CTL_CTRLEN_CLR 0xfffffffe
DMA1_DEBUG_LITE_CLR 0xefffffff
L2_CONT_OFF_l2_standby_CLR 0xfffff3ff
PM_CAM0_LDOLPEN_BITS 1:1
USB_GUSBCFG_FORCE_HST_MODE_LSB 29
USB_GOTGCTL_CON_ID_STS_LSB 16
A2W_PLLA_CTRL_NDIV_MSB 9
CM_CCP2CTL_SRC_SET 0x00000007
PWM_CTL_MSEN4_SET 0x80000000
DMA11_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
SD_DQLCRC1_RISE_MSB 31
GP_FSEL0_FSEL02_BITS 8:6
MS_SEMA_31_MASK 0x00000001
CM_GNRICCTL_FLIP_LSB 11
HD_MAI_CTL_ENABLE_LSB 3
GR_VCM_BASE 0x1A005C00
EMMC_HWMAXAMP0_RESET 0000000000
SD_PT1_T_INIT3_MSB 27
FPGA_CTRL0_DISP_BUFFER_LSB 11
PM_PROC_RESET 0000000000
DMA15_TI_NO_WIDE_BURSTS_BITS 26:26
SD_DQRCRC1_FALL_BITS 15:0
USB_DIEPCTL0_SNAK_LSB 27
USB_GINTMSK_INCOMPL_ISO_IN_LSB 20
CM_PERIACTL_WIDTH 7
SD_DQLCRC9_MASK 0xffffffff
DMA11_TI_DEST_IGNORE_CLR 0xffffff7f
APERF1_BW0_CTRL_BUS_MSB 4
USB_GINTMSK_DISCONN_INT_CLR 0xdfffffff
DMA12_CS_ACTIVE_LSB 0
A2W_PLLC_CORE1_CHENB_MSB 8
DSI1_LP_DLT7_MASK 0xffffffff
DMA13_TI_DEST_INC_LSB 4
HDMI_RAM_PACKET_8_4_RESET 0000000000
DMA11_SOURCE_AD_S_ADDR_LSB 0
CAM1_CAMDBCTL_WIDTH 32
SH_HCFG_DATA_IRPT_EN_BITS 4:4
OTP_VPU_CACHE_KEY_ROW (8 +4)
DMA5_TXFR_LEN_YLENGTH_MSB 29
EMMC_HWCAP0_AINT_BITS 29:29
ASB_V3D_M_CTRL_FULL_BITS 3:3
SLIM_CON_RESET 0x000000c1
USB_GOTGCTL_DEV_HNP_EN_MSB 11
AUX_MU_STAT_RX_IDLE 0x00000004
V3D_PCTRS11_WIDTH 5
USB_DTXFSTS11_WIDTH 32
USB_GPVNDCTL_CTRL_ULPI_BITS 13:8
A2W_PLLA_ANA_KAIP_MASK 0x0000077f
PWM_DAT1 0x7e20c014:RW
PWM_DAT2 0x7e20c024:RW
PWM_DAT3 0x7e20c034:RW
PWM_DAT4 0x7e20c044:RW
EMMC_BUS_CTRL_BUS_WIDTH_SET 0x00007f00
USB_GI2CCTL_RW_SET 0x40000000
USB_GAHBCFG_P_TXF_EMP_LVL_LSB 8
A2W_PLLC_ANA2_WIDTH 24
USB_DOEPTSIZ6_MASK 0xffffffff
VPU_ARB_CTRL_L2_CHANNEL_INIBIT_MSB 15
USB_DIEPTSIZ4_WIDTH 32
A2W_PLLB_ANA_KAIPR_RESET 0x0000033a
HD_HDM_CTL_ENDIAN_BITS 1:1
CM_INTEN_FGAINA_LSB 10
USB_GOTGINT_A_DEV_TOUT_CHG_RESET 0x0
USB_DVBUSPULSE_WIDTH 12
CAM1_CAMDBWP_MASK 0xffffffff
DMA10_DEBUG_LITE_MSB 28
JMCTRL_DC_TAB(n) MACRO
L1_IC0_CONTROL_ENABLE_STATS_SET 0x00000004
A2W_PLLC_CORE0_CHENB_LSB 8
ASB_BASE 0x7e00a000
TE_BASE 0x7e20e000
VEC_CPS2021_CPS2223_WIDTH 32
DMA3_TI 0x7e007308:RO
SLIM_DCC8_PA1_WIDTH 24
CM_GP1CTL_SRC_LSB 0
PCM_TXC_A_CH1WEX_MSB 31
DMA5_TXFR_LEN_XLENGTH_LSB 0
CM_DSI0ECTL_SRC_LSB 0
MPHI_MOUTFS_LEVEL_MSB 9
A2W_PLLD_DSI1_BYPEN_SET 0x00000200
DMA0_CS_RESET_CLR 0x7fffffff
A2W_PLLB_SP1_CHENB_SET 0x00000100
SMI_SCALER_2_DMA (26*(1<<16))
DMA3_TXFR_LEN_XLENGTH_SET 0x0000ffff
SD_DQRCRC3_RISE_MSB 31
HD_VID_CTL_EMPRGB_LSB 19
APERF1_BW1_ATRANS_WIDTH 32
L1_IC0_PRIORITY_MASK 0x0000ffff
L1_IC0_PRIORITY_IC0_APRIORITY2_BITS 11:8
USB_DIEPINT0_OUT_PKT_ERR_MSB 8
HDMI_PACKET_FIFO_CFG_RESET 0000000000
I2C_SPI_SLV_CR_ENSTAT_BITS 5:5
DMA8_TI_DEST_INC_CLR 0xffffffef
SMIDS_SETUP 24
DMA14_DEBUG_READ_ERROR_MSB 2
ASB_CPR_CTRL_WCOUNT_CLR 0xff003fff
DMA12_DEBUG_FIFO_ERROR_SET 0x00000002
I2C0_A_RESET 0000000000
CM_TECCTL 0x7e1010c8:RW
HDMI_READ_POINTERS_DRFT_RD_ADDR_SET 0x00000080
SD_DQRCRC12_RISE_LSB 16
CM_TECCTL_SRC_MSB 1
GP_FSEL3_FSEL35_MSB 17
I2C_SPI_SLV_IFLS_RXIFLSEL_LSB 3
DMA7_TI_SRC_DREQ_BITS 10:10
A2W_PLLD_ANA_SCTLR_MASK 0x0000001f
A2W_PLLD_CTRL_PDIV_LSB 12
DMA5_TI_INTEN_BITS 0:0
GP_FSEL5_FSEL56_CLR 0xffe3ffff
CCP2TX_TIC 0x7e001014:RW
AVE_IN_STATUS_HSYNC_DET_MSB 5
HD_VID_CTL_EMPRGB_BITS 19:19
CAM1_CAMCAP1_MASK 0xffffffff
DMA15_CS_PAUSED_SET 0x00000010
I2CDEL 0x7e205000 + 0x18:RW
DSI1_HS_DLT3_RESET 0000000000
A2W_PLLD_PER_DIV_BITS 7:0
GP_FSEL2_FSEL27_BITS 23:21
USB_GHWCFG4_EN_VBUSVALID_FILTER_MSB 21
SYSAC_TRANS_PRIORITY 0x7e009018:RW
SLIM_DCC3_STAT_RESET 0000000000
SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_CLR 0xfffffff3
HD_MAI_CTL_ERRORF_MSB 1
SMI_DSW3_WHOLD_BITS 21:16
SD_SECEND0_ADDR_MS_SET 0xffffe000
PCM_GRAY_EN_SET 0x00000001
DMA8_CS_END_CLR 0xfffffffd
DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
HDMI_CPU_STATUS 0x7e902340:RW
USB_DCTL_SGNP_IN_NAK_BITS 7:7
CM_TIMERCTL_SRC_LSB 0
MS_SEMA_1_MASK_LSB 0
ARM_1_SEM0 (0x7E00B000 +0x900)+0x00:RW
SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_RESET 0x0
USB_GAHBCFG_NP_TXF_EMP_LVL_CLR 0xffffff7f
EMMC_FORCE_IRPT_ADMA_ERR_LSB 25
EMMC_IRPT_MASK_CTO_ERR_MSB 16
DMA_ENABLE_EN12_LSB 12
DMA7_TI_SRC_WIDTH_BITS 9:9
PWM_CTL 0x7e20c000:RW
TB_JTB_CONFIG_SPEED_SET 0x00ff0000
CM_TDCLKEN_MPHIWDFT_SET 0x00000200
USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_MSB 25
USB_DIEPCTL0_DPID_LSB 16
SCALER_DISPCTRL_DSP0_PANIC_SET 0x03000000
SD_DQLCRC13_FALL_LSB 0
DMA6_TI_SRC_DREQ_LSB 10
A2W_PLLC_CORE1_BYPEN_CLR 0xfffffdff
USB_DIEPDMAB1_WIDTH 32
SMI_CS_ACTIVE_LSB 2
CM_VPUDIV_DIV_SET 0x00fffff0
PM_IMAGE_H264RSTN_CLR 0xffffff7f
A2W_PLLC_DIG3R_MASK 0x00ffffff
SYSAC_DBG_PRIORITY_PRIORITY_BITS 3:0
USB_DOEPDMAB11_WIDTH 32
APERF0_BW1_RTRANS_MASK 0xffffffff
USB_HCDMA6 0x7e9805d4:RW
SD_CS_STATEN_SET 0x00000040
I2C_SPI_SLV_DR_DATA_CLR 0xffffff00
CM_GP2CTL_FRAC_LSB 9
SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_MSB 15
PCM_RXC_A_CH2WID_SET 0x0000000f
DMA3_DEBUG_LITE_MSB 28
A2W_SMPS_CTLB1_RESET 0000000000
APERF1_BW1_CTRL_ID_EN_RESET 0x0
DMA8_TI_INTEN_BITS 0:0
DMA15_TI_NO_WIDE_BURSTS_SET 0x04000000
CM_EVENT_GAINA_BITS 0:0
CM_PLLTCNT1_CNT_SET 0x00ffffff
PM_DUMMY_ONE_BITS 0:0
CM_ARMDIV 0x7e1011b4:RO
CAM0_CAMIVWIN_MASK 0xffffffff
A2W_PLLD_FRACR 0x7e102a40:RW
PM_AVS_RSTDR_ROSC_SET 0x00000020
EMMC_IRPT_EN_WIDTH 32
I2CA_3 I2C_BASE_3 + 0x0C:RW
PM_PADS5_I2CMODE_CLR 0xffffffbf
I2C_SPI_SLV_CR_CPOL_CLR 0xffffffef
ARM_1_SEM5 (0x7E00B000 +0x900)+0x14:RW
CM_SMICTL_RESET 0000000000
A2W_PLLA_ANA_VCOR 0x7e102e10:RW
DMA3_CS_END_BITS 1:1
USB_DIEPMSK 0x7e980810:RW
SD_DQRCRC8_RISE_MSB 31
EMMC_IRPT_MASK_INT_B_LSB 10
A2W_SMPS_C_CLK_TDEN_SET 0x00000008
DMA1_CS_PAUSED_MSB 4
DMA6_DEBUG_VERSION_SET 0x0e000000
DMA4_CS_DREQ_SET 0x00000008
USB_DSTS_SUSP_STS_LSB 0
DMA4_SOURCE_AD_MASK 0xffffffff
EMMC_CMDTM_MASK 0x3ffb003f
L1_L1_SANDBOX_START1_RESET 0000000000
AVE_IN_STATUS_BUF_NOT_SERV_MSB 3
DMA4_DEBUG_VERSION_CLR 0xf1ffffff
APERF1_BW1_RMAX_WIDTH 24
L1_L1_SANDBOX_START7 0x7ee02838:RW
ASB_ISP_S_CTRL_WCOUNT_CLR 0xff003fff
CM_V3DCTL_SRC_CLR 0xfffffff0
CCP2TX_TSC_TSM_BITS 3:0
DMA10_CONBLK_AD_MASK 0xffffffe0
USB_DTKNQR2 0x7e980824:RW
CCP2RDR3 CCP2_BASE_ADDRESS + 0x88:RO
USB_DTKNQR4 0x7e980834:RW
APERF0_BW2_CTRL_ID_CLR 0xffffe0ff
APERF0_BW1_WTRANS 0x7e009890:RO
HDMI_READ_POINTERS_DOMAIN_HALF_FULL_MSB 30
CM_EVENT_LOSSD_CLR 0xfffffeff
SYSAC_DMA_ARBITER_CONTROL_LITE_MASK 0x0000ffff
EMMC_INTERRUPT_INT_B_LSB 10
USB_GOTGCTL 0x7e980000:RW
PM_RSTS_HADWRH_SET 0x00000040
A2W_PLLC_CORE2_BYPEN_SET 0x00000200
CMI_CAM0_RX0SRC_CLR 0xfffffff3
EMMC_CONTROL0_GAP_IEN_CLR 0xfff7ffff
DMA7_CS_PRIORITY_LSB 16
AVE_OUT_STATUS_WIDTH 10
L1_L1_SANDBOX_END0 0x7ee02804:RW
AVE_IN_CTRL_LINE_IRQ_EN_BITS 4:4
EMMC_RESP0 0x7e300010:RW
SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_MSB 15
PM_HDMI_RSTDR_BITS 19:19
EMMC_RESP3 0x7e30001c:RW
DMA10_DEBUG_MASK 0x1ffffff7
CCP2TX_TIC_TQIE_CLR 0xfffffffb
CM_CAM1CTL_BUSYD_LSB 8
PWM_DMAC_DREQ_LSB 0
I2C1_S_MASK 0xffffffff
GP_REN0_MASK 0xffffffff
MS_VPU_STAT_VPU_STAT_SET 0x00000001
USB_DOEPTSIZ6_WIDTH 32
APERF1_BW0_CTRL_ID_EN_CLR 0xdfffffff
DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
USB_GRSTCTL_RXF_FLSH_CLR 0xffffffef
DMA15_STRIDE_S_STRIDE_LSB 0
DMA1_SOURCE_AD_S_ADDR_BITS 31:0
SD_DQLCRC8_RISE_MSB 31
FPGA_MB_SDC_H264_FREQ 0x7e20b72c:RO
MPHI_OUTDDA_MASK 0xffffffff
SCALER_DISPBKGND_0 0x7e400000 + 0x44:RW
SCALER_DISPBKGND_1 0x7e400000 + 0x54:RW
SCALER_DISPBKGND_2 0x7e400000 + 0x64:RW
CM_PLLC_LOADPER_LSB 6
DMA9_CS_PANIC_PRIORITY_CLR 0xff0fffff
PWMDAT(n) MACRO
PCM_CS_A_TXE_CLR 0xffdfffff
UART_MSR_DSR_CLR 0xffffffdf
A2W_SMPS_A_MODER 0x7e1029a0:RW
SH_CMD_LONG_RESPONSE_MSB 9
UART_SCR_WIDTH 8
UNICAM_IDCA(x) MACRO
SH_HSTS_BUSY_IRPT_LSB 10
CM_DSI1EDIV_MASK 0x0000fff0
UNICAM_IDCD(x) MACRO
SD_REORD 0x7ee000a8:RO
HD_HDM_CTL_PDSTBY_BITS 5:4
CM_CAM1CTL_RESET 0000000000
DMA6_SOURCE_AD_S_ADDR_BITS 31:0
I2CDIV 0x7e205000 + 0x14:RW
DMA10_TI_INTEN_CLR 0xfffffffe
GP_FSEL3_FSEL31_LSB 3
EMMC_IRPT_MASK_READ_RDY_CLR 0xffffffdf
FPGA_MB_SDC_CLK_FREQ_MASK 0xffffffff
PM_CAM1_LDOCTRL_BITS 20:3
DMA4_TI_DEST_DREQ_SET 0x00000040
PIXELVALVE0_INTSTAT 0x7e206028:RW
USB_GRSTCTL 0x7e980010:RW
DMA0_CS_DREQ_BITS 3:3
I2C_SPI_SLV_MIS_OEMIS_LSB 3
VEC_FREQ1_0_WIDTH 32
A2W_PLLA_DSI0_CHENB_MSB 8
HD_VID_CTL_HPOL_LSB 27
USB_GHWCFG2_TOKEN_QUEUE_DEPTH_MSB 30
A2W_PLLD_FRAC_FRAC_MSB 19
TB_JTB_CONFIG_BUSY_MSB 31
L1_L1_SANDBOX_END6 0x7ee02834:RW
I2C_SPI_SLV_HCTRL_DATA_LSB 0
DMA9_NEXTCONBK_MASK 0xffffffe0
CMI_CAM1_RX2SRC_CLR 0xffffff3f
PM_SPARER_MASK 0x00ffffff
SD_RWC_WRTOVR_LSB 15
UART_LCR_EPS_BITS 4:4
V3D_SLCACTL_WIDTH 32
DMA1_CS_ACTIVE_SET 0x00000001
DMA14_CS_ABORT_LSB 30
CM_UARTCTL_ENAB_BITS 4:4
ARM_I0_TIMER 0x00000001
SD_DQRCRC14_RISE_BITS 31:16
SD_SB_STBY_T_CLR 0x000fffff
GR_VCM_CI_ADDR_MASK 0x0000007f
HDMI_RAM_PACKET_8_2_WIDTH 32
USB_HCSPLT0_XACT_POS_BITS 15:14
TB_BOOT_SECURE_MODE_JTAG_SECURE_CLR 0xfffffffc
PM_PADS0_DRIVE_BITS 2:0
SD_SE_RL_EN_RESET 0x0
HD_VID_CTL_ENABLE_RESET 0x0
SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_CLR 0xfffffff8
CAM1_CAMCMP0_WIDTH 32
SH_HCFG_RESET 0000000000
FPGA_MB_XSLC2_BUILD_NUM 0x7e20b71c:RO
A2W_SMPS_C_CTL_UPEN_BITS 1:1
MS_SEMA_0_MASK_MSB 0
APERF0_BW2_ATRANS_WIDTH 32
EMMC_FORCE_IRPT_BLOCK_GAP_CLR 0xfffffffb
DMA1_TI_SRC_DREQ_MSB 10
A2W_PLLB_FRACR_WIDTH 20
HD_VID_CTL_CLRRGB_SET 0x00800000
DMA6_SOURCE_AD_S_ADDR_CLR 0x00000000
AVE_IN_CTRL_EN_OVERRUN_ABORT_LSB 15
L1_L1_SANDBOX_START1_CTRL_MSB 0
DMA3_CONBLK_AD_MASK 0xffffffe0
USB_HPRT_RES_SET 0x00000040
AVE_IN_CTRL_HSYNC_IRQ_EN_SET 0x00000020
CM_ARMCTL_FRAC_MSB 9
USB_DIEPDMAB10_WIDTH 32
EMMC_IRPT_EN_INT_A_SET 0x00000200
SLIM_STAT 0x7e210008:RW
USB_DOEPCTL0_SNAK_MSB 27
DMA2_TI_DEST_WIDTH_MSB 5
CM_DFTCTL_SRC_SET 0x0000000f
USB_DTXFSTS1_MASK 0xffffffff
SD_SE_RL_SET 0x03f00000
USB_GUSBCFG_DDR_SEL_BITS 7:7
A2W_XOSC_MULTI_RESET 0000000000
SLIM_DCC9_STAT_RESET 0000000000
AVE_OUT_CTRL_ENABLE_LSB 31
A2W_PLLA_DSI0_DIV_CLR 0xffffff00
DMA5_DEBUG_DMA_STATE_BITS 24:16
SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_CLR 0xffffffcf
FPGA_MB_CORE_CLK_FREQ_MASK 0xffffffff
V3D_CT0LC_WIDTH 32
HDMI_DETECTED_HORZB_WIDTH 30
FPGA_STATUS0_SD_CD_CLR 0xffffffdf
USB_GUSBCFG_IND_PASS_THRU_SET 0x01000000
IC0_FORCE1_WIDTH 32
A2W_PLLC_MULTI_WIDTH 0
CCP2TX_TPC 0x7e00100c:RW
PM_AVS_INTEN_ALERT_V3D_G_BITS 3:3
MPHI_C0INDDA 0x7e006000:RW
MPHI_C0INDDB 0x7e006004:RW
PWM_STA_WIDTH 13
DMA11_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
DMA1_TI_PERMAP_MSB 20
V3D_PCTR9_MASK 0xffffffff
IC0_SRC0_WIDTH 32
USB_GINTMSK_ISO_OUT_DROP_SET 0x00004000
DMA1_DEBUG_DMA_STATE_BITS 24:16
GR_VPM_VRFCFG_BASE 0x1A005D00
DMA0_DEBUG_OUTSTANDING_WRITES_LSB 4
USB_DOEPDMA6_WIDTH 32
SD_SB_INHIBIT_LA_LSB 8
DMA14_TI_DEST_INC_CLR 0xffffffef
SYSAC_L2_ARBITER_CONTROL_ALGORITHM_MSB 7
DMA5_CS_END_CLR 0xfffffffd
APERF1_BW2_ATRANS_RESET 0000000000
MPHI_C1INDFS_MASK 0xffffffff
CM_H264CTL_SRC_SET 0x0000000f
HDMI_RAM_PACKET_6_1_RESET 0000000000
HDMI_RAM_PACKET_4_2 0x7e902498:RW
HDMI_RAM_PACKET_4_3 0x7e90249c:RW
HDMI_RAM_PACKET_4_4 0x7e9024a0:RW
USB_GINTMSK_I2C_INT_RESET 0x0
HDMI_RAM_PACKET_4_6 0x7e9024a8:RW
HDMI_RAM_PACKET_4_7 0x7e9024ac:RW
HDMI_RAM_PACKET_4_8 0x7e9024b0:RW
A2W_PLLB_ANA_STAT_WIDTH 12
USB_GRXSTSP_HST_BCNT_BITS 14:4
DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
A2W_PLLH_ANA_SCTL_UPDATE_LSB 3
A2W_PLLB_ANA_SCTL_SEL_BITS 2:0
USB_HCINT0_NYET_RESET 0x0
FPGA_DCM_CTRL_PERI_EN_BITS 27:24
DMA5_TI_BURST_LENGTH_LSB 12
DMA2_CS_PRIORITY_MSB 19
PCM_MODE_A_FLEN_LSB 10
EMMC_TUNE_STEPS_DDR_MASK 0x0000003f
A2W_PLLA_CCP2_CHENB_SET 0x00000100
SH_CMD_COMMAND_SET 0x0000003f
V3D_PCTRS4_WIDTH 5
SD_DAT_WIDTH 28
USB_HCSPLT0_PRT_ADDR_BITS 6:0
HDMI_RAM_PACKET_2_3_RESET 0000000000
TXP_PROGRESS_LINES_LSB 0
DMA12_DEST_AD_D_ADDR_BITS 31:0
SMI_DSR1_RPACEALL_SET 0x00008000
APERF1_BW0_RTRANS 0x7ee0805c:RO
CAM0_CAMISTA_WIDTH 32
HDMI_TX_PHY_BASE (HDMI_BASE_ADDRESS + 0x2c0)
IC0_FORCE0_CLR_RESET 0000000000
CCP2TX_TTC_BI_LSB 16
CM_PULSEDIV_DIV_MSB 23
USB_GI2CCTL_EN_CLR 0xff7fffff
RSTCS RS_BASE + 0x0:RW
DMA0_TI_SRC_IGNORE_CLR 0xfffff7ff
SCALER_DISPBASE1_MASK 0xffffffff
DMA6_TI_SRC_WIDTH_LSB 9
USB_DIEPINT0_BACK2BACK_SETUP_CLR 0xffffffbf
HDMI_13_AUDIO_CFG_1_MASK 0x000003ff
A2W_PLLA_DIG0R 0x7e102800:RW
ARM_IDVAL 0x364D5241
ASB_V3D_M_CTRL_EMPTY_LSB 2
DMA4_SOURCE_AD_S_ADDR_SET 0xffffffff
SCALER_DISPSTAT1_WIDTH 32
CM_INTEN_GAIND_BITS 3:3
APERF1_BW2_CTRL_ID_EN_MSB 29
USB_DAINT_WIDTH 32
DSI0_DISP1_CTR_WIDTH 32
A2W_PLLB_ANA_VCO_RANGE_BITS 0:0
MPHI_C0INDFS 0x7e006020:RW
SD_DQLCRC5_FALL_CLR 0xffff0000
SD_STALL_CYCLES_MSB 9
EMMC_HWCAP0_TCLKFREQ_LSB 0
CAM1_CAMDBSA1_MASK 0xffffffff
AVE_IN_STATUS_CAPTURING_SET 0x80000000
DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
A2W_PLLA_ANA_KAIP_KA_LSB 8
DMA7_CS_DISDEBUG_LSB 29
SCALER_DISPECTRL_CB_NE_CTRL_CLR 0x1fffffff
A2W_PLLH_ANA_VCOR 0x7e102e70:RW
VPU_ARB_CTRL_UC_LIMIT_LSB 0
APERF0_BW0_WMAX_WIDTH 24
PWM_CTL_RPTL1_MSB 2
CCP2TX_TC_TIP_LSB 8
GP_FSEL6_FSEL61_BITS 5:3
UNICAM_IDI0(x) MACRO
UNICAM_IDI1(x) MACRO
USB_DIEPINT0_BNA_LSB 9
USB_HCINTMSK1_WIDTH 32
MPHI_TXAXICFG_TXNPRIO_SET 0x0000000f
A2W_PLLA_DIG1R 0x7e102804:RW
VEC_DAC_MISC_WIDTH 32
SLIM_DMA_DC5_RESET 0000000000
EMMC_CONTROL1_CLK_FREQ_MS2_BITS 7:6
L2_FLUSH_END_WIDTH 28
DSI1_HS_DLT3_MASK 0xffffffff
CCP2TX_TPC_TNP_MSB 3
ARM_1_SEMS (0x7E00B000 +0x900)+0x00:RW
DMA1_CS_DREQ_LSB 3
SD_VER_MASK 0xffffffff
L1_L1_SANDBOX_END2_RESET 0000000000
A2W_PLLB_MULTI_RESET 0000000000
DMA_ENABLE_EN1_BITS 1:1
GP_FSEL0_FSEL04_CLR 0xffff8fff
CSI2_RDLS CSI2_BASE_ADDRESS + 0x08:RW
SMI_DSR3_RPACE_SET 0x00007f00
L1_D1_WBACKS 0x7ee021a0:RO
DMA1_CONBLK_AD_SCB_ADDR_MSB 31
EMMC_ARG1_WIDTH 32
DMA14_TI_DEST_DREQ_SET 0x00000040
A2W_PLLC_ANA_KAIPR_RESET 0x0000033a
CM_PULSECTL_BUSY_LSB 7
DMA5_DEBUG_READ_ERROR_CLR 0xfffffffb
SYSAC_JPEG_PRIORITY_P_PRIORITY_SET 0x000000f0
DMA9_TI_DEST_WIDTH_BITS 5:5
GP_FSEL4_FSEL45_BITS 17:15
PM_AVS_RSTDR_ROSC_BITS 5:5
UART_MSR_CTS_LSB 4
A2W_XOSC_BIAS_BIAS_CLR 0xfffffff0
DMA11_CS_ACTIVE_MSB 0
CCP2TX_TAC_CLAC_MSB 23
SMI_DSR3_MODE68_BITS 23:23
A2W_PLLD_DSI0_BYPEN_BITS 9:9
CAM_DMA (0*(1<<16))
I2C_SPI_SLV_DR_DATA_BITS 7:0
A2W_PLLA_DIG2R 0x7e102808:RW
DMA6_TI_TDMODE_CLR 0xfffffffd
JICST 0x7e005000 + 0x4:RW
GP_FSEL3_FSEL37_BITS 23:21
CCP2TX_TAC_DLAC_MSB 15
DMA_CS_RESET (1<<31)
USB_DTXFSTS0_SPC_AVAIL_LSB 16
A2W_PLLH_ANA_KAIP_KI_MSB 6
SCALER_DISPECTRL_BUSY_STATUS_SET 0xffffff00
CM_GNRICCTL_KILL_SET 0x00000020
SCALER_DISPCTRL_VSCL_DIS_BITS 31:30
VCE_CONTROL_OFFSET 0x40020
USB_HCSPLT0_SPLT_ENA_SET 0x80000000
L1_IC0_CONTROL_DISABLE_BITS 0:0
DMA1_NEXTCONBK_ADDR_SET 0xffffffe0
DMA3_CS_ERROR_BITS 8:8
GP_FSEL2_FSEL29_BITS 29:27
DMA_ENABLE_EN2_CLR 0xfffffffb
EMMC_TUNE_STEP_WIDTH 3
AVE_OUT_Y_COEFF_MASK 0x3fffffff
SMI_DSW3_WSTROBE_MSB 6
GP_FSEL4_FSEL47_SET 0x00e00000
AVE_IN_STATUS_FRAME_RATE_DET_CLR 0xffffffbf
SPI_CS_TA_CLR 0xffffff7f
USB_HCINT6_WIDTH 32
SLIM_DCC6_PA0_RESET 0000000000
MPHI_CTRL_EIGHTBIT_RESET 0x1
L1_D0_RD_HITS_WIDTH 0
DMA3_DEBUG_RESET 0000000000
AVE_IN_CTRL_LINE_IRQ_EN_CLR 0xffffffef
A2W_PLLA_DIG3R 0x7e10280c:RW
CM_ARMCTL_ENAB_LSB 4
DMA2_TI_TDMODE_SET 0x00000002
ARM_3_SEM5 (0x7E00B000 +0xB00)+0x14:RW
A2W_XOSC_CTRL_PLLBOK_MSB 19
SCALER_DISPID_WIDTH 32
A2W_PLLA_ANA_SSCS_MODE_LSB 16
TXP_CTRL_BWE_CLR 0xfff0ffff
PCM_MODE_A_FSLEN_SET 0x000003ff
GP_APB_ID 0x6770696f
DMA13_CS_RESET_MSB 31
SPI_CS_INTD_MSB 9
DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
EMMC_INTERRUPT_CARD_OUT_CLR 0xffffff7f
MPHI_C0INDDA_START_BITS 31:0
USB_GUSBCFG_PHY_IF_MSB 3
DSI0_PHYC_unused_CLR 0xffffffef
SCALER_DISPCTRL_TILE_WID_SET 0x00030000
I2C_SPI_SLV_DR_TXFE_SET 0x00100000
USB_DIEPCTL0_NAK_STS_LSB 17
HDMI_BKSV1_WIDTH 32
HDMI_CPU_CLEAR 0x7e902348:RW
AUX_MU_STAT_TXEMPTY 0x00000100
USB_HPRT_LN_STS_CLR 0xfffff3ff
CM_TD1CTL_GATE_LSB 6
USB_GOTGCTL_A_SES_VLD_BITS 18:18
SMI_DSW0_WWIDTH_MSB 31
V3D_SQCNTL_WIDTH 4
GP_REN1_RESET 0000000000
PM_GNRIC_ISFUNC_SET 0x00000020
SYSAC_UC_ARBITER_CONTROL_LIMIT_SET 0x00000003
PWMCTL_USEF1 5
PWMCTL_USEF2 13
PWMCTL_USEF3 21
PWMCTL_USEF4 29
USB_GNPTXFSIZ_IN_EP_TXF0_DEP_LSB 16
SMI_DSW0_WDREQ_LSB 7
USB_DIEPTSIZ10 0x7e980a50:RW
CM_PLLC_LOADCORE2_LSB 4
MPHI_C1INDFS_DFIFOLVL_MSB 15
USB_GRXSTSP_HST_CH_NUM_RESET 0x0
TB_ADDR_MASK 0xffffffff
DMA9_CS_PANIC_PRIORITY_SET 0x00f00000
FPGA_MB_SDC_V3D_FREQ_MASK 0xffffffff
SD_SECSRT3_ADDR_LS_RESET 0x0
A2W_PLLC_CTRL_PDIV_MSB 14
USB_GINTMSK_INCOMPL_P_RESET 0x0
AVE_IN_STATUS_BUF0_COMPL_MSB 1
PM_CAM1_LDOHPEN_BITS 2:2
DMA7_TI_SRC_DREQ_LSB 10
CCP2TX_TSC_TSM_LSB 0
L1_IC1_CONTROL_RAS_DISABLE_BITS 4:4
DMA5_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
CM_SDCCTL_MASK 0x0003f3bf
HDMI_PACKET_FIFO_CTL_RESET 0000000000
DMA8_TI_DEST_DREQ_MSB 6
INTERRUPT_DMA_VPU ((64) + 31 )
SYSAC_HVSM_PRIORITY_N_PRIORITY_BITS 3:0
USB_HCINT0_FRM_OVRUN_MSB 9
TB_TASK_TEXT_FLAG_LSB 16
USB_DOEPDMA3_WIDTH 32
VEC_CGMSAE_RESET_MASK 0xffffffff
A2W_PLLH_ANA_SCTL_UPDATE_MSB 3
MPHI_HSINDCF_MTERM_CLR 0xefffffff
AUX_MU_IO_REG (0x7E215000 +0x040)
SD_DQLCRC4_RISE_BITS 31:16
HD_CSC_CTL_COLORD_BITS 7:5
A2W_PLLH_AUX_CHENB_CLR 0xfffffeff
A2W_PLLH_DIG0 0x7e102060:RW
A2W_PLLH_DIG1 0x7e102064:RW
A2W_PLLH_DIG2 0x7e102068:RW
A2W_PLLH_DIG3 0x7e10206c:RW
DMA2_CS_END_CLR 0xfffffffd
HDMI_RAM_PACKET_3_7_WIDTH 32
SD_STALL_WIDTH 10
PM_PADS4_SPARE_LSB 4
SH_CMD_FAIL_FLAG_LSB 14
CM_PLLC_LOADCORE0_MSB 0
SD_DQRCRC8_MASK 0xffffffff
GP_FSEL6_FSEL62_CLR 0xfffffe3f
A2W_PLLB_SP1_RESET 0x00000100
A2W_PLLH_ANA_STAT_RCALCODE_LSB 16
EMMC_HWCAP1_SPI_MODE_LSB 24
EMMC_DMA_STATUS_LEN_NOMATCH_CLR 0xfffffffb
DMA13_CS_END_MSB 1
EMMC_CMDTM_TM_DMA_EN_BITS 0:0
CM_PLLD_HOLDDSI0_CLR 0xfffffffd
PIXELVALVE2_VC_WIDTH 23
PM_PADS6_PD_BITS 8:8
TXP_CTRL_DITHER_SET 0x00002000
MPHI_INTSTAT_HSTEND_RESET 0x0
DMA6_CS_ERROR_MSB 8
PM_GRAFX_POWOK_CLR 0xfffffffd
ASB_ISP_M_CTRL_WCOUNT_SET 0x00ffc000
DMA_INT_STATUS_INT10_MSB 10
FPGA_DCM_CTRL_MASK 0xff0fffff
PCMCS_DMAEN (1 << 9)
I2C_SPI_SLV_DR_RXFE_CLR 0xfffdffff
CM_H264CTL_SRC_MSB 3
I1CACHE_BASE 0xffffffff:RW
CM_SDCCTL_KILL_BITS 5:5
HDMI_PERT_INSERT_ERR_MASK 0x00ffffff
APERF1_BW2_CTRL_ID_CLR 0xffffe0ff
IC1_FORCE1_RESET 0000000000
SMI_DSR0_RSETUP_LSB 24
GP_PUD_PUD_MSB 1
DMA9_CS_DISDEBUG_LSB 29
EMMC_HWCAP0_RESUME_MSB 23
SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_CLR 0xffff00ff
MULTICORE_SYNC_SEMA_MASK_0 MULTICORE_SYNC_BASE_ADDRESS + 0x00:RW
DMA8_CS_PRIORITY_LSB 16
MULTICORE_SYNC_SEMA_MASK_2 MULTICORE_SYNC_BASE_ADDRESS + 0x08:RW
DMA1_DEBUG_READ_ERROR_MSB 2
MULTICORE_SYNC_SEMA_MASK_4 MULTICORE_SYNC_BASE_ADDRESS + 0x10:RW
MULTICORE_SYNC_SEMA_MASK_5 MULTICORE_SYNC_BASE_ADDRESS + 0x14:RW
MULTICORE_SYNC_SEMA_MASK_6 MULTICORE_SYNC_BASE_ADDRESS + 0x18:RW
MULTICORE_SYNC_SEMA_MASK_7 MULTICORE_SYNC_BASE_ADDRESS + 0x1C:RW
MULTICORE_SYNC_SEMA_MASK_8 MULTICORE_SYNC_BASE_ADDRESS + 0x20:RW
MULTICORE_SYNC_SEMA_MASK_9 MULTICORE_SYNC_BASE_ADDRESS + 0x24:RW
MPHI_OUTDFS_WIDTH 32
HDMI_READ_POINTERS_DRFT_EMPTY_MINUS_SET 0x00020000
V3D_FDBGR_WIDTH 32
SD_DQLCRC10_WIDTH 32
DMA5_CS_PRIORITY_CLR 0xfff0ffff
HDCP_KEY_CTL_DISHDCP_BITS 2:2
GRSSP 0x1A005800 + 0x10:RW
CM_SLIMCTL_BUSYD_SET 0x00000100
SCALER_OLEDCOEF0_WIDTH 32
UART_LCR_SP_SET 0x00000020
ARM_MC_IHAVEDATAIRQPEND 0x00000010
PM_GNRIC_MRDONE_BITS 4:4
USB_HCINTMSK7_MASK 0xffffffff
AJB_BUSY 0x80000000
OTP_BOOT_SIGNING_PARITY_ROW (((((((8 +4)+4)+1)+1)+1)+4)+4)
DMA4_TI_INTEN_CLR 0xfffffffe
A2W_PLLC_ANA0_MASK 0x00ffffff
GP_AREN2_RESET 0000000000
USB_GRSTCTL_TXF_FLSH_RESET 0x0
SMI_DC 0x7e600030:RW
SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_LSB 2
SD_TMC 0x7ee0007c:RW
DMA3_CS_ERROR_SET 0x00000100
HDMI_DETECTED_VERTB0_MANUAL_VSPO0_CLR 0xffc001ff
TXP_CTRL_POWERDOWN_MSB 21
GP_EDS0_EDSn0_BITS 31:0
HDMI_RAM_PACKET_2_1_WIDTH 32
SMI_DD 0x7e60003c:RW
USB_DPTXFSIZ4_MASK 0xffffffff
CM_OSCCOUNT_NUM_LSB 0
A2W_PLLB_ARM_DIV_CLR 0xffffff00
USB_DCTL_SFT_DISCON_BITS 1:1
CAM0_CAMDLT_RESET 0000000000
PM_PROC_ISFUNC_BITS 5:5
GP_EDS1_MASK 0xffffffff
DMA10_DEBUG_DMA_ID_CLR 0xffff00ff
EMMC_HWCAP0_AINT_CLR 0xdfffffff
SLIM_DCC8_PROT_RESET 0x000093a0
EMMC_DMA_STATUS_LEN_NOMATCH_MSB 2
USB_DCTL_SGNP_IN_NAK_CLR 0xffffff7f
SMIDSR2 0x7e600000 + 0x20:RW
DMA8_CS_ABORT_LSB 30
CM_UARTDIV_RESET 0000000000
UART_LCR_DLAB_MSB 7
UNICAM_IDPO(x) MACRO
DMA14_CS_PAUSED_SET 0x00000010
USB_GI2CCTL_EN_LSB 23
SD_DQLCRC1_FALL_MSB 15
A2W_SMPS_C_CTL_CTRLEN_MSB 0
CM_TDCLKEN_MPHIWDFT_LSB 9
I2C_SPI_SLV_DR_TXDMABREQ_LSB 11
TB_JTB_CONFIG_TDI_RISE_MSB 9
CM_PWMCTL_ENAB_BITS 4:4
DMA6_CS_DREQ_BITS 3:3
USB_GINTMSK_OTG_INT_LSB 2
DMA2_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
GP_FSEL4_FSEL46_LSB 18
CCP2TX_TC_TEN_MSB 0
TXP_CTRL_FORMAT_BITS 11:8
SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_RESET 0x0
CM_DPICTL_ENAB_MSB 4
SLIM_DMA_DC_STAT_0_RESET 0000000000
DMA12_CS_DREQ_STOPS_DMA_LSB 5
V3D_VPACNTL 0x7ec00000 +0x0500:RW
SLIM_DMA_DC_STAT_0 0x7e21008c:RW
SLIM_DMA_DC_STAT_1 0x7e210090:RW
DSI_PHY_CONTROL 0x7e209000 + 0x40:RW
SMI_DSW2_WPACE_MSB 14
PCM_MODE_A_FLEN_MSB 19
ASB_ISP_M_CTRL_MASK 0x00ffffff
I2C_SPI_SLV_TDR_DATA_LSB 0
CM_PLLTCNT0_RESET 0000000000
SLIM_STAT_MASK 0x03ffffff
CM_EVENT_LOSSH_SET 0x00000200
TS_TSENSSTAT_DATA_MSB 9
FPGA_DCM_CTRL_PERI_WR_EN_SET 0xf0000000
PM_AVS_RSTDR_V3D_G_BITS 3:3
DMA2_TI_SRC_DREQ_MSB 10
L1_L1_SANDBOX_END0_WIDTH 30
DMA0_STRIDE_WIDTH 32
A2W_HDMI_CTL2R_WIDTH 24
I2C0_DEL_MASK 0xffffffff
DMA3_DEBUG_LITE_CLR 0xefffffff
A2W_HDMI_CTL_HFENR_WIDTH 1
AVE_IN_STATUS_OVERRUN_CNT_MSB 28
GP_CLR1_CLRn32_CLR 0x00000000
USB_GHWCFG2_MODE_SET 0x00000007
DMA3_STRIDE_S_STRIDE_MSB 15
TB_TASK_RXDATA1 0x7e20b084:RW
A2W_PLLB_ANA_VCOR_MASK 0x00000001
CM_V3DCTL_BUSY_BITS 7:7
DMA1_TI_NO_WIDE_BURSTS_SET 0x04000000
USB_DCFG_EP_MIS_CNT_SET 0x007c0000
APERF0_BW0_RMAX_MASK 0x00ffffff
A2W_XOSC_CTRL_PLLCEN_LSB 0
EMMC_HWCAP1_SDR104_SET 0x00000002
SH_CMD_NO_RESPONSE_SET 0x00000400
IC1_VADDR 0x7e002830:RW
DMA6_TXFR_LEN_WIDTH 30
DMA1_TI_DEST_DREQ_BITS 6:6
PCM_CS_A_RXR_CLR 0xfffbffff
DMA2_TI_DEST_INC_BITS 4:4
SD_DQLCRC2_RISE_CLR 0x0000ffff
SMI_DSW1_WPACE_LSB 8
VEC_CGMSAE_TOP_FORMAT_WIDTH 32
SMI_DSR3_RWIDTH_SET 0xc0000000
SD_SC_T_WR_SET 0x00000f00
ASB_V3D_S_CTRL_WIDTH 24
UNICAM_ANA(x) MACRO
CCP2TX_TC_MEN_BITS 1:1
GROPCTR_TU1_CACHE_STALLS 0x1A
CAM1_CAMCAP0_RESET 0000000000
SYSAC_PERI_ARBITER_CONTROL_WIDTH 16
SMI_CS_START_MSB 3
A2W_PLLB_SP0_BYPEN_LSB 9
CM_HSMCTL_SRC_SET 0x0000000f
USB_HCCHAR3_WIDTH 32
DMA14_CONBLK_AD_SCB_ADDR_MSB 31
A2W_SMPS_CTLC3R_WIDTH 24
DMA15_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
USB_GI2CCTL_DAT_SE0_CLR 0xefffffff
DMA6_CS_PANIC_PRIORITY_BITS 23:20
DMA6_STRIDE_S_STRIDE_BITS 15:0
CM_DFTCTL_BUSY_LSB 7
A2W_PLLB_SP2R_WIDTH 10
ASB_ISP_S_CTRL_WCOUNT_BITS 23:14
AVE_OUT_STATUS_RESET 0000000000
SD_SECEND0 0x7ee00040:RW
VEC_CPS2425_CPS2627_MASK 0xffffffff
SH_HCFG_WIDE_INT_BUS_MSB 1
TXP_CTRL_VERSION_RESET 0x1
DMA4_DEBUG_OUTSTANDING_WRITES_LSB 4
SD_CS_STOP_LSB 7
SCALER_DISPSTAT_DSP0_STATUS_SET 0x00003f00
USB_DIEPINT0_OUT_TKN_EP_DIS_MSB 4
SD_DQRCRC3_FALL_MSB 15
USB_DFIFO8_WIDTH 32
PCM_CS_A_RXSYNC_MSB 14
APERF0_BW1_RTRANS_RESET 0000000000
SYSAC_DMA_ARBITER_CONTROL_L2_RESET 0000000000
PCM_CS_A_RXERR_SET 0x00010000
SMI_CS_INTR_LSB 11
DMA4_DEBUG_DMA_STATE_SET 0x01ff0000
SD_SC_T_RRD_CLR 0xff0fffff
DMA8_TXFR_LEN_WIDTH 16
DMA3_CS_PRIORITY_MSB 19
DMA_REG(n,offset) MACRO
DMA9_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
A2W_PLLH_ANA_SCTL_WIDTH 5
DMA0_STRIDE 0x7e007018:RO
CM_CCP2CTL_FRAC_CLR 0xfffffdff
SMI_CS_SETERR_SET 0x00002000
DMA13_TI_BURST_LENGTH_LSB 12
SD_DQRCRC12_FALL_LSB 0
EMMC_INTERRUPT_INT_A_LSB 9
V3D_DBSCFG_WIDTH 32
CM_EVENT_RESET 0000000000
SYSAC_JPEG_PRIORITY_N_PRIORITY_LSB 0
ASB_CPR_CTRL_FULL_SET 0x00000008
EMMC_IRPT_MASK_INT_C_LSB 11
PWM_DAT2_RESET 0000000000
CMI_CAM1_WIDTH 10
USB_DFIFO12_MASK 0xffffffff
APERF1_BW2_AMAX_MASK 0x00ffffff
EMMC_IRPT_MASK_BOOTACK_MSB 13
I2CCLKT_0 0x7e205000 + 0x1C:RW
I2CCLKT_1 0x7e804000 + 0x1C:RW
A2W_PLLC_CORE1_RESET 0x00000100
I2CCLKT_3 I2C_BASE_3 + 0x1C:RW
MPHI_C0INDFS_CFIFOLVL_SET 0xffff0000
EMMC_DATA_MASK 0xffffffff
EMMC_FORCE_IRPT_CCRC_ERR_MSB 17
MS_SEMA_17_MASK_MSB 0
DMA6_STRIDE_S_STRIDE_MSB 15
I2C2_A_MASK 0x0000007f
AVE_IN_CTRL_PRIV_MODE_BITS 7:7
A2W_PLLD_DIG0_RESET 0000000000
USB_GINTMSK_GIN_N_NAK_EFF_SET 0x00000040
DMA10_CS_END_MSB 1
MS_SEMA_23_MASK_LSB 0
UTHR 0x7e201000 + 0x00:RW
SMI_DSR3_RWIDTH_LSB 30
V3D_BPCA_WIDTH 32
A2W_PLLB_ANA_KAIP_KA_LSB 8
USB_DPTXFSIZ6_WIDTH 32
SD_DQRCRC4_RISE_CLR 0x0000ffff
APERF0_BW0_CTRL_RESET_SET 0x80000000
DMA15_TI_DEST_INC_LSB 4
DSI0_APB_ID 0x00647369
I2C_SPI_SLV_RIS_RXRIS_SET 0x00000001
A2W_PLLD_PERR_RESET 0x00000100
I2CCLKT_x(x) MACRO
EMMC_IRPT_EN_INT_B_LSB 10
USB_HAINT_MASK 0xffffffff
PCM_CS_A_TXON_MSB 2
CM_GP1CTL_BUSYD_SET 0x00000100
AM_VP_PERPRI 0x1800d008:RW
HDMI_DETECTED_VERTA0_MANUAL_VFP0_BITS 19:13
VCE_PC_EX0_OFFSET 0x40014
UART_LCR_PEN_MSB 3
CM_DPICTL_KILL_CLR 0xffffffdf
CM_DSI1ECTL_BUSYD_MSB 8
AUX_MU_LCR_7BITS 0x02
AVE_IN_LINE_NUM_INT_RESET 0000000000
PM_PADS4_DRIVE_CLR 0xfffffff8
SCALER_DISPSTAT_DSP0_IRQ_CLR 0x00000001
DMA10_DEST_AD_MASK 0xffffffff
HD_CSC_CTL_MODE_RESET 0x0
DMA9_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
A2W_PLLD_ANA_KAIPR_RESET 0x0000033a
DMA9_CS_END_MSB 1
CCP2TX_TAC_CTATADJ_BITS 31:28
SMI_DSR0_RSTROBE_MSB 6
A2W_PLLH_PIX_DIV_MSB 7
DSI_LP_DLT6 0x7e209000 + 0x5C:RW
DSI_LP_DLT7 0x7e209000 + 0x60:RW
APERF0_BW1_CTRL_LATHALT_SET 0x10000000
PM_PADS5_DRIVE_SET 0x00000007
DMA15_TI_SRC_WIDTH_BITS 9:9
PCM_CS_A_TXON_BITS 2:2
PCM_GRAY_FLUSH_SET 0x00000004
CCP2TX_TIC_TIIE_CLR 0xfffffffe
ASB_CPR_CTRL_WIDTH 24
SH_HSTS_DATA_FLAG_LSB 0
DMA15_TXFR_LEN_YLENGTH_CLR 0xc000ffff
DMA12_SOURCE_AD_MASK 0xffffffff
ARM_1_MY_IRQS (0x7E00B000 +0x900)+0xFC:RW
PIXELVALVE1_C 0x7e207000:RW
DMA7_TI_WIDTH 26
VEC_INTERRUPT_CONTROL_MASK 0xffffffff
SD_RWC_MARGIN_SET 0x00c00000
A2W_PLLH_ANA_STAT_CNTLENB_MSB 20
SD_TMC_TS_LSB 1
GP_FSEL1_FSEL19_CLR 0xc7ffffff
I2CS_DONE (1 << 1)
EMMC_HWCAP1_SDR50_CLR 0xfffffffe
FPGA_MB_XSLC2_BUILD_NUM_WIDTH 32
USB_DIEPINT0_OUT_TKN_EP_DIS_RESET 0x0
I2C_SPI_SLV_IMSC_OEIM_BITS 3:3
ASB_ISP_S_CTRL_FULL_LSB 3
SLIM_DCC5_PROT_RESET 0x000093a0
OTP_BOOT_SIGNING_PARITY_SIZE_IN_ROWS 1
ARM_EH_PERIBURST 0x00000001
HDMI_RAM_PACKET_12_7_MASK 0xffffffff
DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
CM_V3DCTL_ENAB_MSB 4
CAM1_CAMIDCA_MASK 0xffffffff
DMA7_CS_RESET_MSB 31
SYSAC_HVSM_PRIORITY_P_PRIORITY_MSB 7
HDMI_RAM_PACKET_13_8_WIDTH 32
CM_SMICTL_SRC_SET 0x0000000f
GP_AREN0_WIDTH 32
DMA15_TI_PERMAP_SET 0x001f0000
SPI_CS_DMAEN_BITS 8:8
L1_IC1_FLUSH_E_WIDTH 32
CM_PERIADIV_DIV_SET 0x00001000
USB_GRXSTSP_DEV_PKT_STS_CLR 0xffe1ffff
L1_D_CONTROL 0x7ee02100:RW
A2W_PLLH_ANA_KAIPR_MASK 0x0000077f
A2W_PLLH_ANA3_WIDTH 24
SD_DQLCRC11_RISE_MSB 31
TB_BOOT_OPT_FPGA_SET 0x00000004
AVE_IN_STATUS_FRAME_RATE_DET_LSB 6
USB_GHWCFG4_NUM_PERIO_EPS_LSB 0
SD_DQLCRC8_FALL_MSB 15
IWAKEUP_0 0x7e002034:RW
IWAKEUP_1 0xffffffff:RW
SCALER_DISPSTAT_WR_IRQ_SET 0xffffffe0
CM_PLLC_LOADCORE2_BITS 4:4
A2W_SMPS_B_STAT_VOLTS_MSB 4
VPU_ARB_CTRL_UC_DELAY_RESET 0x0
CM_EVENT_FLOSSB_SET 0x00008000
L1_IC1_RAS_UNDERFLOW 0x7ee020d8:RO
SD_DQRCRC15_MASK 0xffffffff
DMA8_DEBUG 0x7e007820:RW
DMA3_CS_ACTIVE_CLR 0xfffffffe
DMA12_TI_DEST_INC_BITS 4:4
CM_HSMDIV_DIV_BITS 15:4
USB_DOEPINT0_SETUP_RESET 0x0
PCM_CH2POS_LSB 4
CM_PULSECTL_BUSYD_LSB 8
DMA10_CS_ABORT_MSB 30
TS_TSENSCTL_MASK 0x07ffffff
SD_MR_DONE_BITS 31:31
CMI_CAM1_RX0SRC_MSB 3
AVE_OUT_CB_COEFF_RED_COEFF_CLR 0xc00fffff
AVE_IN_OVERRUN_ADDRESS_WIDTH 32
SH_HCFG_SDIO_IRPT_EN_MSB 5
CM_INTEN_BADPASS_LSB 18
DMA2_CS_PRIORITY_BITS 19:16
GP_FSEL0_FSEL08_SET 0x07000000
DMA7_DEBUG_LITE_SET 0x10000000
USB_DTHRCTL_NON_ISO_THR_EN_BITS 0:0
USB_DAINT_IN_EP_INT_RESET 0x0
TB_JTB_TDO_MASK 0xffffffff
PIXELVALVE1_VERTA_EVEN_WIDTH 32
USB_HCCHAR0_MC_EC_RESET 0x0
PM_SPARER 0x7e100078:RO
HDMI_AN_INFLUENCE_1_RESET 0000000000
I2C_SPI_SLV_DR_RXDMAPREQ_LSB 12
PM_SPAREW 0x7e100074:RW
TXP_CTRL_ALPHA_ENABLE_BITS 20:20
DMA8_TI_SRC_DREQ_LSB 10
A2W_PLLD_CORE_CHENB_MSB 8
SD_DQLCRC11_FALL_CLR 0xffff0000
GP_SET0_SETn0_CLR 0x00000000
AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_CLR 0x7fffffff
ASB_H264_M_CTRL_RCOUNT_MSB 13
CM_AVEOCTL_ENAB_BITS 4:4
DMA9_CONBLK_AD_SCB_ADDR_BITS 31:5
SMI_DSR3_RSETUP_MSB 29
SMI_CS_RXD_BITS 29:29
MPHI_MINFS_LEVEL_RESET 0x0
HDMI_RAM_PACKET_11_7_RESET 0000000000
PCM_MODE_A 0x7e203008:RW
FPGA_CTRL0_LV_SPARE_OUT_MSB 19
APERF0_BW0_CTRL_ID_RESET 0x0
MULTICORE_SYNC_ICSET_0 MULTICORE_SYNC_BASE_ADDRESS + 0x90:RW
DMA15_TI_WAITS_SET 0x03e00000
MS_STATUS_STATUS_CLR 0x00000000
TXP_CTRL_TEST_MODE_SET 0x00000010
HDMI_RAM_GCP_7_MASK 0xffffffff
SD_DQLCRC9_RISE_CLR 0x0000ffff
DMA1_CS_ERROR_LSB 8
DMA_ENABLE_EN6_SET 0x00000040
A2W_PLLD_ANA_STAT_DATA_BITS 11:0
SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_RESET 0x0
USB_GINTMSK_ENUM_DONE_SET 0x00002000
A2W_PLLB_ARMR_RESET 0x00000100
DMA_INT_STATUS_INT13_MSB 13
IC0_MASK7_WIDTH 31
DMA10_TI_DEST_INC_MSB 4
USB_HCCHAR6_WIDTH 32
HDMI_RAM_PACKET_10_2_MASK 0xffffffff
PM_PADS4_DRIVE_MSB 2
USB_DIEPTSIZ0_MC_MSB 30
JQADDR 0x7e005000 + 0x40:RW
USB_DPTXFSIZ11_WIDTH 32
HDCP_KEY_CTL_DONE_RESET 0x0
CM_PLLC_HOLDCORE1_MSB 3
USB_DIEPINT0_XFER_COMPL_CLR 0xfffffffe
A2W_PLLD_CORE_DIV_MSB 7
SLIM_DCC0_STAT_RESET 0000000000
SPI_FIFO_DATA_SET 0x000000ff
SD_RAC_RESET 0000000000
CAM0_CAMIBSA1_RESET 0000000000
ARM_DS_OWNER 0x00000003
DMA1_DEBUG_OUTSTANDING_WRITES_BITS 7:4
USB_GOTGINT_HST_NEG_SUC_STS_CHG_CLR 0xfffffdff
SD_DQRCRC5_WIDTH 32
USB_HCTSIZ0_XFER_SIZE_CLR 0xfff80000
TE_2C 0x7e20e018:RW
TB_JTB_TDI_MASK 0xffffffff
CM_SLIMCTL_ENAB_MSB 4
MS_SEMA_31_MASK_BITS 0:0
CAM0_CAMDBG0_RESET 0000000000
DMA15_DEBUG 0x7ee05020:RW
CM_LOCK_FLOCKB_SET 0x00000200
SMI_A_ADDR_LSB 0
DMA15_TI_SRC_INC_LSB 8
PM_AVS_STAT_ALERT_PERI_A_CLR 0xfffffffe
CCP2TX_TTC_FSP_MSB 12
DMA9_CS_PRIORITY_LSB 16
I2CCLKT_2 0x7e805000 + 0x1C:RW
DMA11_CS_PANIC_PRIORITY_SET 0x00f00000
A2W_PLLB_ARM_DIV_BITS 7:0
PM_PADS3_DRIVE_LSB 0
EMMC_STATUS_CARD_STABLE_BITS 17:17
USB_GINTMSK_NP_TXF_EMP_BITS 5:5
DMA9_SOURCE_AD_S_ADDR_CLR 0x00000000
DMA8_DEBUG_VERSION_CLR 0xf1ffffff
A2W_PLLA_ANA_SCTLR_MASK 0x0000001f
A2W_PLLA_DIG0_RESET 0000000000
USB_DIEPTXF2_MASK 0xffffffff
SD_DQLCRC2_MASK 0xffffffff
CM_DSI1EDIV_WIDTH 16
DMA9_TI_SRC_WIDTH_SET 0x00000200
EMMC_CONTROL0_HCTL_CRDDET_S_CLR 0xffffff7f
IC1_S_WIDTH 27
APERF1_BW2_CTRL_EN_CLR 0xbfffffff
CM_PLLA_LOADPER_CLR 0xffffffbf
PWM_CTL_MODE2_BITS 9:9
APERF0_BW2_RPEND_WIDTH 8
HDMI_SCHEDULER_CONTROL_MODE_ACTIVE_CLR 0xfffffffd
PWM_CTL_POLA4_SET 0x10000000
CM_V3DCTL_KILL_CLR 0xffffffdf
USB_DOEPINT10_MASK 0xffffffff
TB_PRINTER_CTRL_WIDTH 16
EMMC_IRPT_MASK_CCRC_ERR_CLR 0xfffdffff
MPHI_INTSTAT_HSDISC_BITS 30:30
USB_DIEPTSIZ0_MC_SET 0x60000000
INTERRUPT_I2C ((64) + 53 )
USB_HCCHAR0_EP_NUM_LSB 11
A2W_PLLA_PERR_RESET 0x00000100
PM_PADS2_POWOK_CLR 0xffffffdf
CM_OTPCTL_BUSYD_CLR 0xfffffeff
L1_IC1_RAS_UNDERFLOW_WIDTH 0
DMA14_CS_DREQ_LSB 3
DMA5_CS_RESET_BITS 31:31
CM_V3DCTL_SRC_BITS 3:0
CM_SMICTL_BUSYD_SET 0x00000100
SYSAC_UC_ARBITER_CONTROL_THRESHOLD_CLR 0xffffffcf
EMMC_IRPT_EN_ENDBOOT_BITS 14:14
USB_DOEPDMA11 0x7e980c74:RW
DMA6_CS_END_MSB 1
SCALER_DISPCTRL0_WIDTH 32
PCM_INTSTC_A_TXW_LSB 0
DPHY_CSR_CRC_CTRL_RESET 0000000000
DMA14_TI_SRC_WIDTH_CLR 0xfffffdff
DMA2_CS_PAUSED_BITS 4:4
DMA2_DEST_AD 0x7e007210:RO
A2W_PLLD_CORE_BYPEN_CLR 0xfffffdff
A2W_PLLD_CORE_DIV_BITS 7:0
GP_AJBTDI_WIDTH 32
DMA13_NEXTCONBK_MASK 0xffffffe0
USB_DOEPINT4_WIDTH 32
CM_CAM0CTL_BUSY_SET 0x00000080
CM_GP0CTL_SRC_SET 0x0000000f
DMA4_CS_ABORT_BITS 30:30
DMA0_DEBUG_LITE_MSB 28
SD_MR_TIMEOUT_LSB 30
GP_REN2_RENn64_MSB 5
DMA6_TI_BURST_LENGTH_BITS 15:12
TS_TSENSCTL_DIRECT_MSB 6
SD_SB_EIGHTBANK_MSB 4
CM_DSI1ECTL_BUSYD_BITS 8:8
L1_L1_SANDBOX_START4_START_ADDR_LSB 5
SLIM_MC_OUT_STAT_WIDTH 4
PWM_STA_STA2_CLR 0xfffffbff
DMA1_SOURCE_AD_S_ADDR_LSB 0
MPHI_INTSTAT_RX1MEND_LSB 8
SCALER_DISPSTAT_PROF_IRQ_SET 0xffffffff
DMA2_CS_INT_BITS 2:2
CM_INTEN_FLOSSA_BITS 14:14
V3D_PCTR2_WIDTH 32
SCALER_DISPECTRL_PANIC_CTRL_CLR 0xffffff80
AVE_IN_STATUS_MAX_HIT_CLR 0xfffeffff
PM_GNRIC_POWOK_LSB 1
USB_DCTL_GNP_IN_NAK_STS_CLR 0xfffffffb
GRMCCT 0x1A005C00 + 0x28:RW
SLIM_DCC2_PROT_RESET 0x000093a0
I2C_SPI_SLV_BASE 0x7e214000
DMA3_TI_SRC_DREQ_MSB 10
USB_GOTGCTL_CON_ID_STS_BITS 16:16
USB_DOEPDMA15 0x7e980cf4:RW
SDDELC0 SD_DELC0
DMA11_DEBUG_VERSION_CLR 0xf1ffffff
CSI2_REA1 CSI2_BASE_ADDRESS + 0x210:RW
PCM_CS_A_SYNC_LSB 24
USB_DOEPINT0_SETUP_BITS 3:3
DMA1_SOURCE_AD_MASK 0xffffffff
UART_LCR_WLS_SET 0x00000003
USB_GOTGCTL_A_SES_VLD_CLR 0xfffbffff
DMA8_TI_SRC_INC_LSB 8
PIXELVALVE1_APB_ID 0x70697876
AVE_IN_STATUS_CURRENT_BUF_BITS 17:17
SMI_DSR0_RDREQ_MSB 7
PIARBCTL_CAM_LIMIT_CLR 0xfffffffc
SD_RWC_WRTVAL_MSB 12
I2C_SPI_SLV_VCSTAT_DATA_CLR 0xfffffff0
USB_GAHBCFG_MASK 0x000001bf
APERF0_BW2_CTRL_RESET_RESET 0x0
DMA12_CS_PRIORITY_BITS 19:16
USB_DFIFO4 0x7e985000:RW
CM_UARTDIV 0x7e1010f4:RW
ARM_0_MAIL0_CNF (0x7E00B000 +0x800)+0x9C:RW
CM_GP2CTL_BUSY_BITS 7:7
A2W_SMPS_L_SPV_VOLTS_LSB 0
CM_TD0CTL_BUSY_BITS 7:7
SMI_DSW0_WHOLD_CLR 0xffc0ffff
CM_AVEOCTL_SRC_SET 0x0000000f
USB_DOEPCTL0_EO_FR_NUM_CLR 0xfffeffff
CMI_CAM1_RX3SRC_BITS 9:8
MPHI_C0INDDB_MORUN_SET 0x80000000
CM_DPICTL_SRC_CLR 0xfffffff0
DSI0_PHYC_txulpshs_0_sync_LSB 1
PWM_CTL_MSEN2_SET 0x00008000
DMA_ENABLE_EN4_LSB 4
A2W_PLLA_CTRL_RESET 0x00010000
SD_CS_SDUP_LSB 15
SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_LSB 4
CM_BURSTCTL_WIDTH 8
GP_CLR0_WIDTH 32
SD_SA_POWSAVE_LSB 0
HDMI_RAM_PACKET_12_6_MASK 0xffffffff
DMA8_TI_DEST_IGNORE_SET 0x00000080
UART_LCR_STB_BITS 2:2
I2C0_DLEN_WIDTH 16
USB_DSTS_SOF_FN_LSB 8
MPHI_HSINDFS_DFIFOLVL_CLR 0xfffffffe
CM_VPUCTL_FRAC_MSB 9
SYSAC_TRANS_PRIORITY_N_PRIORITY_CLR 0xfffffff0
V3D_ERRSTAT 0x7ec00000 +0x0f20:RW
EMMC_TUNE_STEPS_STD_RESET 0000000000
CM_SLIMCTL_KILL_CLR 0xffffffdf
DMA5_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
DMA8_DEBUG_OUTSTANDING_WRITES_LSB 4
A2W_PLLB_ANA_SSCS 0x7e1021f0:RW
MPHI_INTCTRL_HSDISC_CLR 0xfffeffff
AVE_IN_LINE_NUM_INT_LINE_NUM_INT_LSB 0
DMA1_TI_WAIT_RESP_SET 0x00000008
APERF0_BW2_CTRL_ID_BITS 12:8
SH_CMD_READ_CMD_LSB 6
APERF0_BW2_RPEND 0x7e009868:RO
DMA4_CS_PRIORITY_MSB 19
CM_TSENSCTL_ENAB_BITS 4:4
A2W_SMPS_B_STAT_VOLTS_SET 0x0000001f
EMMC_IRPT_MASK_DATA_DONE_LSB 1
HDMI_RAM_PACKET_7_3_RESET 0000000000
CM_PULSECTL_BUSY_MSB 7
CAM0_CAMIBSA0 0x7e800110:RW
CAM0_CAMIBSA1 0x7e800304:RW
A2W_SMPS_A_VOLTS_WIDTH 5
PM_CAM1_LDOHPEN_MSB 2
A2W_XOSC0R_WIDTH 24
DMA12_DEBUG_DMA_STATE_SET 0x01ff0000
CSI2DBGDPHY CSI2_BASE_ADDRESS + 0x80:RW
EMMC_FORCE_IRPT_SDOFF_ERR_CLR 0xff7fffff
ASB_V3D_M_CTRL_WIDTH 24
DMA5_SOURCE_AD_S_ADDR_MSB 31
CM_SLIMCTL_SRC_BITS 3:0
CM_ISPCTL_BUSYD_CLR 0xfffffeff
DSI1_RXPKT_FIFO_RESET 0000000000
DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
EMMC_FORCE_IRPT_WRITE_RDY_BITS 4:4
UART_LCR_PEN_BITS 3:3
USB_DTXFSTS0_SPC_AVAIL_RESET 0x0
I2C_SPI_SLV_CR_TESTFIFO_CLR 0xfffff7ff
GR_PPL_DEBUG_ADDR_MASK 0x0000001F
SCALER_DISPSLAVE1_MASK 0xffffffff
SMI_DC_REQW_BITS 5:0
AUX_SPI_CNTL1_CSPLUS2 0x00000200
DMA3_CS_PANIC_PRIORITY_LSB 20
DMA6_NEXTCONBK_MASK 0xffffffe0
SD_VIN_ID_MSB 15
SD_DQRCRC10_RISE_SET 0xffff0000
PCMCS PCM_BASE_ADDRESS + 0x00:RW
HDMI_RAM_PACKET_7_3_MASK 0xffffffff
L1_L1_SANDBOX_START2_CTRL_SET 0x00000001
HDMI_READ_POINTERS_DRFT_OVERFLOW_LSB 19
DMA0_TI_WAITS_BITS 25:21
SD_DQRCRC9_FALL_LSB 0
HDMI_RAM_PACKET_1_2_MASK 0xffffffff
ARM_C1_BELL0 0x00000004
DMA10_CS_RESET_CLR 0x7fffffff
V3D_BPOA_MASK 0xffffffff
USB_DIEPTXF4_MASK 0xffffffff
MPHI_C0INDCF_LENGTH_MSB 19
USB_GRSTCTL_INT_TKN_Q_FLSH_BITS 3:3
AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_BITS 31:31
PWM_RNG2_RESET 0x00000020
SD_DQLCRC13_RISE_BITS 31:16
APERF1_APB_ID 0x41584950
PM_AVS_EVENT_ALERT_PERI_A_LSB 0
PM_AVS_STAT_ALERT_SYSTEM_A_BITS 1:1
USB_DFIFO9 0x7e98a000:RW
GRFTLOC 0x1A005400 + 0x08:RW
USB_DIEPDMAB5_MASK 0xffffffff
DMA11_TI_DEST_IGNORE_MSB 7
L1_IC1_PRIORITY_IC1_APRIORITY3_CLR 0xffff0fff
CM_PLLTCTL_RESET 0000000000
DSI0_PHYC_RESET 0000000000
DMA6_DEBUG_FIFO_ERROR_CLR 0xfffffffd
CM_ISPCTL_WIDTH 10
I2C_SPI_SLV_IMSC_TXIM_MSB 1
DMA2_DEBUG_DMA_STATE_LSB 16
USB_GUSBCFG_USB_TRD_TIM_MSB 13
DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
DMA4_DEST_AD_MASK 0xffffffff
USB_DOEPINT8_MASK 0xffffffff
DMA11_TI_BURST_LENGTH_SET 0x0000f000
TXP_CTRL_TRANSPOSE_SET 0x00000040
DMA4_DEBUG_FIFO_ERROR_CLR 0xfffffffd
DMA8_DEST_AD_D_ADDR_BITS 31:0
PM_AVS_INTEN_ALERT_SYSTEM_A_MSB 1
MS_MBOX_3_RESET 0000000000
SMIDS_HOLD 16
VCE_PC_IF0_OFFSET 0x4000c
USB_DFIFO8_MASK 0xffffffff
PCM_FIFO_A_MASK 0xffffffff
DMA4_TI_DEST_IGNORE_MSB 7
USB_DVBUSPULSE_PULSE_MSB 11
USB_GRXSTSP_HST_DPID_BITS 16:15
A2W_PLLB_ANA_SSCL_LIMIT_LSB 0
HDMI_TX_PHY_TX_PHY_TMDS_CFG_WIDTH 32
VCE_BUSY_USER 0x01
DMA6_TI_SRC_DREQ_SET 0x00000400
CM_EMMCCTL_FRAC_LSB 9
AVE_IN_CTRL_LENGTH_IN_PXLS_LSB 8
USB_DIEPINT0_AHB_ERR_MSB 2
L2_CONT_OFF_l2_enable_stats_CLR 0xffffffdf
GR_PSE_BASE 0x1A005800
PM_DUMMY 0x7e1000fc:RO
PWM_STA_GAPO1_MSB 4
CM_GP1CTL_BUSY_CLR 0xffffff7f
CM_INTEN_BURSTDONE_CLR 0xff7fffff
CM_V3DDIV_DIV_CLR 0xffff000f
CM_TSENSCTL_BUSY_MSB 7
SPI_CS_CSPOL_SET 0x00000040
A2W_PLLD_ANA_SCTL_UPDATE_MSB 3
L2_SD_STALLS 0x7ee01124:RO
DMA1_TI_BURST_LENGTH_MSB 15
SH_HBCT 0x7e20203c:RW
DMA2_NEXTCONBK_ADDR_MSB 31
AVE_IN_CHAR_CTRL_WIDTH 32
FPGA_CTRL0_CAM_CTL0_CLR 0xfffffffe
CM_GNRICCTL_GATE_SET 0x00000040
CM_TIMERCTL_FRAC_MSB 9
DMA7_TI_SRC_IGNORE_LSB 11
USB_DOEPINT0_STS_PHSE_RCVD_SET 0x00000020
USB_GI2CCTL_RW_DATA_LSB 0
A2W_PLLC_CTRL_NDIV_LSB 0
HDMI_RAM_PACKET_12_2_MASK 0xffffffff
PM_AVS_EVENT_ALERT_ARM_P_MSB 4
A2W_XOSC_CTRL_PLLAOK_SET 0x00040000
A2W_PLLC_ANA_SCTL_RESET_CLR 0xffffffef
EMMC_CONTROL2_ACNOX_ERR_CLR 0xfffffffe
FPGA_MB_XSLC3_BUILD_NUM 0x7e20b720:RO
DMA0_DEST_AD_D_ADDR_MSB 31
HDMI_RAM_PACKET_13_5_WIDTH 32
CM_PLLH_DIGRST_CLR 0xfffffdff
DMA_INT_STATUS_INT14_BITS 14:14
DMA13_DEBUG_READ_ERROR_MSB 2
PCM_CS_A_TXCLR_LSB 3
CGMSAE_BOT_FORMAT 0x7e806050:RW
USB_GPVNDCTL_REG_ADDR_CLR 0xffc0ffff
USB_DIEPCTL15_MASK 0xffffffff
SCALER_IRQ_STATUS 0x7e400000 + 0x04:RW
MPHI_C1INDCF_LENGTH_CLR 0xfff00000
TB_BOOT_OPT_EIGHT_BANK_BITS 1:1
USB_PCGCR_RST_PDWN_MODULE_MSB 3
VPU_ARB_CTRL_UC_LIMIT_RESET 0x0
DMA3_CS_END_MSB 1
DSI1_PR_TO_CNT 0x7e700048:RW
VCE_BUSY_DMAIN 0x08
VEC_CONFIG3_MASK 0xffffffff
DMA13_TI_WAITS_LSB 21
DMA12_DEST_AD_D_ADDR_MSB 31
A2W_XOSC_PWR_RSTB_BITS 2:2
DMA4_CS_END_LSB 1
SMI_CS_RXD_MSB 29
CM_EVENT_OCDONE_CLR 0xffdfffff
DMA4_CS_ABORT_MSB 30
MPHI_CTRL_MASK 0x88031111
CM_SLIMCTL_SRC_MSB 3
USB_DOEPINT3 0x7e980b68:RW
FPGA_DCM_RD_DATA_DATA_SET 0x0000ffff
USB_DCTL_SFT_DISCON_RESET 0x0
SMI_DCS_WRITE_SET 0x00000008
DMA2_DEBUG_DMA_ID_MSB 15
ASB_V3D_M_CTRL_RCOUNT_SET 0x00003ff0
SYSAC_UC_ARBITER_CONTROL_WIDTH 16
GP_FSEL4_FSEL43_SET 0x00000e00
USB_HCINT0_FRM_OVRUN_SET 0x00000200
HDMI_SCHEDULER_CONTROL_IGN_VSYNC_PREDS_BITS 5:5
USB_DOEPCTL0_DIS_BITS 30:30
DMA0_TI_SRC_DREQ_BITS 10:10
A2W_SMPS_C_CLK_OSCDIV_BITS 1:0
SD_TMC_IPRD_BITS 15:8
USB_DOEPINT4 0x7e980b88:RW
USB_DIEPCTL0_SET_D0_PID_MSB 28
SYSAC_L2_ARBITER_CONTROL_LIMIT_LSB 0
PM_CAM1_LDOCTRL_CLR 0xffe00007
SLIM_CON 0x7e210000:RW
A2W_PLLA_DSI0R 0x7e102b00:RW
DMA_TI_D_WIDTH (1<<5)
CRYPTO_OP_DMA (20*(1<<16))
EMMC_CONTROL0_READWAIT_EN_MSB 18
AVE_IN_OUTSTANDING_BUFF0_MASK 0x000000ff
EMMC_CONTROL0_HCTL_8BIT_MSB 5
DMA15_STRIDE_D_STRIDE_LSB 16
USB_GPVNDCTL_STS_DONE_MSB 27
PM_SPARER_SPARE_LSB 0
SYSAC_DMA_DREQ_CONTROL_RESET 0000000000
DMA10_TI_SRC_IGNORE_LSB 11
USB_GUSBCFG_PHY_LPWR_CLK_SEL_CLR 0xffff7fff
A2W_PLLB_ANA3_WIDTH 24
DMA9_TI_WAITS_SET 0x03e00000
PWM_CTL_MODE4_BITS 25:25
IC0_MASK1_RESET 0000000000
TS_TSENSCTL_REGULEN_LSB 26
DMA11_TI_WAIT_RESP_SET 0x00000008
PM_RSTS_HADPOR_BITS 12:12
AVE_IN_CTRL_BUF1_IRQ_EN_CLR 0xfffffffb
CM_EVENT_LOSSB_CLR 0xffffffbf
PM_RSTS_HADWRF_SET 0x00000020
IC0_FORCE0_SET_MASK 0xffffffff
GP_FSEL2_FSEL26_BITS 20:18
FPGA_STATUS0_SW_SPI_SPI_IN_BITS 7:7
A2W_SMPS_A_VOLTS_RESET 0000000000
USB_DIEPCTL5_WIDTH 32
CM_PERIACTL 0x7e101018:RW
CM_ISPCTL_FRAC_CLR 0xfffffdff
HDMI_RAM_PACKET_3_6_MASK 0xffffffff
EMMC_IRPT_EN_ATA_ERR_MSB 29
SD_SECSRT0_ADDR_LS_CLR 0xffffe001
A2W_PLLB_ANA_SCTL_RESET_BITS 4:4
EMMC_IRPT_EN_BLOCK_GAP_LSB 2
SD_DQRCRC15_RISE_CLR 0x0000ffff
ADDRESS_EXTERNAL(p) MACRO
DMA11_TI_DEST_INC_MSB 4
HDMI_VERTA1_MANUAL_VSP1_CLR 0xfe0fffff
HD_VID_CTL_FULSYNC_CLR 0xffbfffff
I2C_SPI_SLV_IMSC_BEIM_BITS 2:2
A2W_SMPS_B_STAT_POK_CLR 0xffffefff
DMA2_TXFR_LEN_YLENGTH_CLR 0xc000ffff
DMA10_CS_DREQ_BITS 3:3
CM_EVENT_LOSSD_BITS 8:8
HDMI_CEC_CNTRL_3_WIDTH 32
PCM_CS_A_DMAEN_MSB 9
DMA0_DEBUG_FIFO_ERROR_MSB 1
PM_DSI0_LDOLPEN_SET 0x00000002
AVE_OUT_CTRL_ERROR_IRQ_EN_LSB 0
UART_LSR_FE_CLR 0xfffffff7
I2C_SPI_SLV_HCTRL_MASK 0x000000ff
SD_SECSRT2_EN_CLR 0xfffffffe
CAM0_CAMANA_RESET 0x00000777
DMA4_DEBUG_DMA_ID_LSB 8
DMA10_SOURCE_AD_S_ADDR_SET 0xffffffff
USB_GINTMSK_PRT_INT_BITS 24:24
MS_ICCLR_1_ICCLR_1_MSB 0
I2C_SPI_SLV_FR_TXFF_BITS 2:2
SYSAC_L2_ARBITER_CONTROL_DELAY_SET 0x0000000c
MS_SEMA_1_RESET 0000000000
SD_DQLCRC2_FALL_CLR 0xffff0000
I2C_SPI_SLV_IFLS_TXIFLSEL_CLR 0xfffffff8
DMA7_TI_DEST_IGNORE_SET 0x00000080
AVE_OUT_CTRL_MODE_LSB 4
PCM_GRAY_CLR_CLR 0xfffffffd
CCP2TX_TD_TCS_BITS 4:0
DMA_INT_STATUS_INT8_CLR 0xfffffeff
CM_DSI0ECTL_BUSY_CLR 0xffffff7f
V3D_RFC 0x7ec00000 +0x0138:RW
ASB_V3D_M_CTRL_CLR_REQ_BITS 0:0
SYSAC_TRANS_PRIORITY_N_PRIORITY_BITS 3:0
DMA2_TI_NO_WIDE_BURSTS_BITS 26:26
DMA4_TI_MASK 0x07fffffb
HD_HDM_CTL_SW_RST_SET 0x00000004
AVE_OUT_CB_COEFF_GREEN_COEFF_BITS 19:10
CM_PLLB_HOLDARM_MSB 1
DMA0_TXFR_LEN_YLENGTH_BITS 29:16
SD_PHYC_PHYRST_SET 0x00000001
WSE_VPS_CONTROL 0x7e8060d0:RW
CM_EVENT_FLOSSC_LSB 16
CCP2RWP0 CCP2_BASE_ADDRESS + 0x114:RO
CCP2RWP1 CCP2_BASE_ADDRESS + 0x214:RO
HDMI_DETECTED_VERTB1_MANUAL_VSPO1_MSB 21
EMMC_CMDTM_TM_MULTI_BLOCK_LSB 5
I2C_SPI_SLV_FR_RXBUSY_CLR 0xffffffdf
DMA5_NEXTCONBK_ADDR_SET 0xffffffe0
DMA_CS_PAUSED (1<<4)
CM_CAM0CTL_WIDTH 10
DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
UNICAM_IPIPE(x) MACRO
SYSAC_L2_ARBITER_CONTROL_DELAY_RESET 0x0
DMA4_TXFR_LEN_XLENGTH_SET 0x0000ffff
EMMC_STATUS_CMD_INHIBIT_SET 0x00000001
GP_FSEL0_FSEL09_LSB 27
PM_AVS_EVENT_MASK 0x0000001f
HDCP_KEY_CTL_START_CLR 0xfffffffe
DMA11_DEBUG_READ_ERROR_CLR 0xfffffffb
I2C_SPI_SLV_IFLS_RXIFPSEL_SET 0x00000e00
DMA3_DEST_AD_D_ADDR_SET 0xffffffff
SYSAC_L2_ARBITER_CONTROL_THRESHOLD_LSB 4
A2W_PLLA_DSI0R_WIDTH 10
PWM_STA_MASK 0x00001fff
AVE_OUT_STATUS_MASK 0x000003f7
FPGA_CTRL0_SPI0_SEL_B_CLR 0xffffefff
MPHI_HSINDS_WORDS_CLR 0xffe00000
DMA5_TI_WAIT_RESP_MSB 3
DMA5_TI_WIDTH 27
DPHY_CSR_BYTE1_MASTER_DLL_OUTPUT 0x7ee07030:RW
CM_TECCTL_ENAB_BITS 4:4
CM_VECDIV_DIV_MSB 15
VEC_CGMSAE_TOP_FORMAT_MASK 0xffffffff
DMA3_CS_PAUSED_LSB 4
CM_HSMDIV_DIV_CLR 0xffff000f
MPHI_HSINDDB 0x7e006068:RW
DMA2_CS_DISDEBUG_LSB 29
EMMC_STATUS_READ_TRANSFER_CLR 0xfffffdff
SD_SECSRT3_MASK 0xffffffff
L1_D1_WR_HITS_WIDTH 0
L1_IC1_FLUSH_E_RESET 0xffffffff
EMMC_EXRDFIFO_EN_ENABLE_BITS 0:0
FPGA_CTRL0_SW_SPI_SDA_O_CLR 0xffffff7f
VCE_PC_PF0_OFFSET 0x40008
DMA15_DEST_AD_D_ADDR_SET 0xffffffff
HD_MAI_CTL_FLUSH_MSB 9
TB_PCM 0x7e20b200:RW
SD_SECSRT1_ADDR_LS_LSB 1
MS_SEMA_0_MASK_BITS 0:0
CAM1_BASE 0x7e801000
DMA_ENABLE_EN7_LSB 7
APERF0_BW2_CTRL_EN_RESET 0x0
CM_SLIMCTL_MASH_SET 0x00000600
APERF0_BW2_AMAX_MASK 0x00ffffff
GP_AFEN0 0x7e200088:RW
ASB_V3D_M_CTRL_FULL_LSB 3
PCM_CS_A_TXW_BITS 17:17
GP_EDS0_EDSn0_LSB 0
TS_APB_ID 0x7473656e
V3D_DBQSTP_WIDTH 32
SD_DQRCRC4_FALL_CLR 0xffff0000
DMA11_CS_PANIC_PRIORITY_CLR 0xff0fffff
MS_SEMA_4 0x7e000010:RW
MS_MBOX_1_WIDTH 32
ASB_V3D_M_CTRL_CLR_ACK_MSB 1
SLIM_DCC2_PA0_WIDTH 24
SD_DQRCRC1 0x7ee00110:RO
SD_DQRCRC2 0x7ee00114:RO
SD_DQRCRC3 0x7ee00118:RO
SD_DQRCRC4 0x7ee0011c:RO
USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_LSB 22
SD_DQRCRC6 0x7ee00124:RO
SD_DQRCRC7 0x7ee00128:RO
DMA4_TI_SRC_DREQ_MSB 10
SD_DQRCRC9 0x7ee00130:RO
I2C_SPI_SLV_ICR_BEIC_MSB 2
CM_INTEN_FLOSSD_SET 0x00020000
A2W_PLLA_ANA_KAIP_KA_MSB 10
USB_HCDMA6_WIDTH 32
A2W_PLLB_ANA_SSCL 0x7e1022f0:RW
EMMC_BUS_CTRL_IRQSEL_SET 0x00700000
A2W_PLLD_DSI0_WIDTH 10
PM_AVS_EVENT_ALERT_PERI_A_CLR 0xfffffffe
USB_GGPIO_WIDTH 32
FPGA_DCM_CTRL_REMOTE_RST_SET 0x0000001f
DMA0_CS_END_MSB 1
DMA10_TI_SRC_DREQ_BITS 10:10
SYSAC_SRC_ARBITER_CONTROL_DELAY_LSB 2
CM_LOCK_FLOCKC_LSB 10
L1_L1_SANDBOX_END3_MASK 0x3fffffe0
SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_LSB 8
MPHI_AXIPRIV_TXPROT_BITS 2:0
A2W_HDMI_CTL1_RESET 0x00011c00
SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_BITS 15:8
SCALER_DISPLACT2_MASK 0xffffffff
CM_CAM1DIV_DIV_CLR 0xffff000f
CM_ARMCTL_SRC_LSB 0
FPGA_CTRL0_DIS_BL_BITS 1:1
A2W_SMPS_LDO0_WIDTH 24
SD_SECEND3_ADDR_LS_MSB 12
DMA9_CS_ACTIVE_MSB 0
DSI1_HSTX_TO_CNT_MASK 0x00ffffff
CM_SDCCTL_KILL_MSB 5
GRDACFG4 0x1A005A00 + 0x30:RW
DSI1_TXPKT1_H 0x7e700008:RW
HDMI_RAM_PACKET_13_0_WIDTH 32
CM_LOCK_LOCKH_BITS 4:4
DMA7_CS_DISDEBUG_CLR 0xdfffffff
AM_DB_MEMPRI 0x1800d014:RW
EMMC_INTERRUPT_OEM_ERR_MSB 31
MS_SEMA_18_MASK_CLR 0xfffffffe
CM_UARTDIV_DIV_SET 0x003fffff
DMA5_TI_TDMODE_SET 0x00000002
SH_HBLC 0x7e202050:RW
SD_SECSRT3_ADDR_MS_CLR 0x00001fff
ASB_H264_S_CTRL_CLR_ACK_SET 0x00000002
HDMI_FIFO_CTL_MASTER_SLAVE_N_MSB 0
DMA6_DEBUG_VERSION_BITS 27:25
CM_EVENT_GAINA_LSB 0
PWM_CTL_POLA1_BITS 4:4
HDMI_SCHEDULER_CONTROL_USE_POSTLN_AVOID_CLR 0xffffbfff
SPI_CS_CPOL_MSB 3
A2W_PLLC_PER_BYPEN_CLR 0xfffffdff
PIARBCTL_CAM_ALGORITHM_BITS 7:6
GRDACFG5 0x1A005A00 + 0x34:RW
PCM_CS_A_RXON_LSB 1
SD_DQRCRC12_RISE_BITS 31:16
SD_SD_T_XP_SET 0x00070000
USB_GINTMSK_FET_SUSP_SET 0x00400000
SD_SECSRT1_EN_RESET 0x0
MPHI_C0INDDB_MORUN_RESET 0x0
L1_D_PRIORITY_c0_uc_priority_MSB 7
APERF1_BW2_WTWAIT_RESET 0000000000
SD_SF_PGEHLD_T_LSB 19
SD_SB_BANKLOW_CLR 0xffffff9f
DMA5_CS_PRIORITY_MSB 19
SD_RWC_WRTOVR_RESET 0x0
MPHI_C1INDDA_WIDTH 32
L1_D1_RD_SNOOPS_WIDTH 0
AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_SET 0x00000fff
DMA9_CONBLK_AD_SCB_ADDR_LSB 5
USB_DOEPCTL0_CNAK_CLR 0xfbffffff
DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
CAM1_CAMIDCA_RESET 0000000000
DMA12_TXFR_LEN_WIDTH 16
SLIM_DCC4_PA1_MASK 0x00ffff3f
DMA4_CS_RESET_CLR 0x7fffffff
APERF1_BW1_CTRL_EN_RESET 0x0
GR_FBC_DEBUG_BASE 0x1A005500
SD_DQLCRC11_FALL_MSB 15
DMA6_CS_ACTIVE_CLR 0xfffffffe
PIXELVALVE1_VERTA_WIDTH 32
DMA3_TI_SRC_IGNORE_BITS 11:11
TXP_CTRL_EI_CLR 0xfffffffb
CCP2TX_TS_TUE_MSB 3
DMA14_DEBUG_DMA_ID_LSB 8
HDMI_RAM_PACKET_4_3_WIDTH 32
GP_FSEL0_FSEL02_CLR 0xfffffe3f
DMA7_DEBUG_FIFO_ERROR_CLR 0xfffffffd
USB_HCTSIZ0_DO_PNG_SET 0x80000000
USB_HCSPLT0 0x7e980504:RW
IDCLVWMCU 0x10002000:RW
DMA6_TI_SRC_IGNORE_MSB 11
A2W_PLLH_FRACR_MASK 0x000fffff
MPHI_C1INDCF_LENGTH_MSB 19
A2W_XOSC_PWR_RESET 0x00000004
I2C_SPI_SLV_SLV_MASK 0x0000007f
DMA8_DEBUG_DMA_ID_BITS 15:8
A2W_PLLB_CTRL_NDIV_MSB 9
USB_HCSPLT1 0x7e980524:RW
AVE_OUT_STATUS_HBACK_PORCH_SET 0x00000020
I2C_SPI_SLV_SLV_ADDR_LSB 0
ARM_IF_TIMER 0x00000040
OTP_ARM_DISABLE_BIT 24
A2W_PLLD_ANA_KAIP_KA_LSB 8
V3D_FDBG0_MASK 0xffffffff
DSI0_RX1_PKTH 0x7e20900c:RO
USB_GOTGCTL_HST_NEG_SCS_CLR 0xfffffeff
USB_DIEPINT14_WIDTH 32
CAM1_CAMMISC_MASK 0xffffffff
DMA3_TI_PERMAP_LSB 16
MPHI_C0INDCF_MTERM_SET 0x10000000
EMMC_CONTROL0_WAKE_ONINS_EN_MSB 25
EMMC_IRPT_EN_CEND_ERR_LSB 18
DMA13_DEBUG 0x7e007d20:RW
A2W_PLLC_ANA_KAIP_KA_CLR 0xfffff8ff
SCALER_DISPSTAT_DSP1_IRQ_SET 0xfffffffc
L1_L1_SANDBOX_START7_START_ADDR_LSB 5
SMI_A_DEVICE_SET 0x00000300
DMA3_DEBUG_READ_ERROR_BITS 2:2
DMA9_TI_BURST_LENGTH_LSB 12
SLIM_DCC2_PROT_MASK 0xc001ffff
DMA10_DEBUG_DMA_STATE_LSB 16
CSI2_RDS_x(x) MACRO
L1_IC0_CONTROL_START_FLUSH_SET 0x00000002
CAM1_CAMPRI_MASK 0xffffffff
CM_DSI0EDIV_DIV_SET 0x0000fff0
APERF1_BW1_CTRL_LATHALT_MSB 28
SD_TMC_TSTCLK_MSB 0
EMMC_IRPT_MASK_CARD_IN_CLR 0xffffffbf
L1_D0_WR_THRUS_WIDTH 0
USB_DAINT_OUT_EP_INT_RESET 0x0
DSI0_PHYC_forcehsstop_sync_LSB 2
SD_DQLCRC8_FALL_RESET 0x0
SD_DQLCRC12_RISE_CLR 0x0000ffff
SYSAC_SRC_ARBITER_CONTROL_DELAY_BITS 3:2
SD_DQLCRC9_FALL_CLR 0xffff0000
DMA5_TI_DEST_DREQ_SET 0x00000040
OTP_SUSPEND_SECURE_RAM_KEY (((((((((((((((((((((8 +4)+4)+1)+1)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+1)
UNICAM_ISTA(x) MACRO
USB_GPVNDCTL_REG_DATA_RESET 0x0
MPHI_C1INDS_HANDLE_RESET 0x0
INTERRUPT_CAM0 ((64) + 38 )
CCP2TX_TS_IEB_LSB 1
DSI_PIX_FIFO 0x7e209000 + 0x20:RW
I2C_SPI_SLV_DMACR_RXDMAE_LSB 0
CM_GP2CTL_BUSY_SET 0x00000080
DMA1_STRIDE_S_STRIDE_BITS 15:0
V3D_PCTR11_MASK 0xffffffff
ASB_ISP_S_CTRL_RCOUNT_LSB 4
I2C0_S_MASK 0xffffffff
HDMI_SCHEDULER_CONTROL_VSYNC_RESET_VAL_MSB 21
CM_DSI1PCTL_BUSY_BITS 7:7
SH_VDD_POWER_ON_LSB 0
CM_TD0CTL_BUSY_LSB 7
USB_DIEPINT8_MASK 0xffffffff
AVE_OUT_CTRL_INVERT_CSYNC_LSB 17
I2C_SPI_SLV_FR_RXFF_MSB 3
EMMC_FORCE_IRPT_DEND_ERR_BITS 22:22
SD_SD_T_RC_CLR 0xfe0fffff
DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
AVE_IN_CTRL_PRIV_MODE_CLR 0xffffff7f
DMA6_TI_BURST_LENGTH_LSB 12
MULTICORE_SYNC_SEMA_MASK_20 MULTICORE_SYNC_BASE_ADDRESS + 0x50:RW
DMA7_TI_WAITS_LSB 21
APERF1_BW2_RTWAIT_MASK 0xffffffff
CM_CCP2DIV_DIV_LSB 12
ASB_H264_S_CTRL_FULL_LSB 3
CM_CAM1CTL_ENAB_MSB 4
IC1_WAKEUP_WIDTH 32
A2W_PLLA_CORE_DIV_CLR 0xffffff00
DMA5_TXFR_LEN_WIDTH 30
USB_DOEPDMA7_MASK 0xffffffff
EMMC_BUS_CTRL_IRQ_PINS_CLR 0xffffffc7
DMA11_DEBUG_DMA_ID_BITS 15:8
APHY_CSR_ADDR_SLAVE_DLL_OFFSET 0x7ee06018:RW
PM_CCP2TX_LDOCTRL_CLR 0xfff80003
GP_FSEL6_FSEL69_CLR 0xc7ffffff
A2W_SMPS_CTLB1R_RESET 0000000000
SLIM_DCC3_STAT 0x7e21026c:RW
USB_HCTSIZ0_DO_PNG_BITS 31:31
FPGA_CTRL0_DIS_RST_CLR 0xfffffff7
CCP2TX_TS_TFE_BITS 4:4
MULTICORE_SYNC_SEMA_MASK_22 MULTICORE_SYNC_BASE_ADDRESS + 0x58:RW
CAM0_CAMDBG2_MASK 0xffffffff
PCMCS_TXSYNC (1 << 13)
ARBITER_CTRL_BASE 0x7e009000
IC0_FORCE0_SET_RESET 0000000000
SH_RSP1_CID_CSD_BITS 31:0
HDMI_RAM_PACKET_9_7_RESET 0000000000
EMMC_TUNE_STEPS_DDR_STEPS_BITS 5:0
HD_VID_CTL_CLRSYNC_LSB 24
CAM1_CAMDAT2_WIDTH 32
PWM_CTL_PWEN3_CLR 0xfffeffff
USB_GOTGCTL_DBNC_TIME_SET 0x00020000
CM_EVENT_GAINH_BITS 4:4
CAM1_CAMANA_MASK 0xffffffff
SD_VIN_VIO_SET 0x00100000
CM_PLLA_HOLDCORE_SET 0x00000020
CM_ARMCTL_KILL_MSB 5
DMA15_CS_INT_BITS 2:2
DMA15_TI_TDMODE_MSB 1
A2W_SMPS_CTLA1_WIDTH 24
AUX_MU_CNTL_AURTRINV 0x40
DMA4_TXFR_LEN_YLENGTH_BITS 29:16
CM_DSI0PCTL_RESET 0000000000
CM_PLLB_DIGRST_CLR 0xfffffdff
HDMI_FIFO_CTL_ON_VB_MSB 7
MULTICORE_SYNC_SEMA_MASK_25 MULTICORE_SYNC_BASE_ADDRESS + 0x64:RW
MPHI_TXAXICFG 0x7e006048:RW
MS_SEMA_8_MASK 0x00000001
A2W_PLLD_ANA_KAIP 0x7e102350:RW
GP_CLR0_CLRn0_MSB 31
AVE_OUT_CTRL_PRIV_ACCESS_LSB 8
SMI_DSW1_WHOLD_SET 0x003f0000
SYSAC_L2_ARBITER_CONTROL 0x7e009040:RW
A2W_PLLA_DSI0_WIDTH 10
UNICAM_PRI(x) MACRO
DMA13_CS_ACTIVE_LSB 0
SMI_DA_WRITE_CLR 0xfffffcff
USB_DIEPINT0_OUT_TKN_EP_DIS_CLR 0xffffffef
EMMC_SLOTISR_VER_SLOT_STATUS_SET 0x000000ff
CM_OTPCTL_BUSY_SET 0x00000080
USB_DOEPCTL0_DPID_BITS 16:16
SH_HCFG_SLOW_CARD_SET 0x00000008
AVE_IN_CTRL_LOW_PRIORITY_MSB 19
USB_GHWCFG4_EN_A_VALID_FILTER_LSB 22
DMA11_DEBUG_LITE_SET 0x10000000
MULTICORE_SYNC_SEMA_MASK_28 MULTICORE_SYNC_BASE_ADDRESS + 0x70:RW
A2W_XOSC_PWR_WIDTH 3
GP_FSEL5_FSEL58_SET 0x07000000
USB_GRXSTSP_DEV_EP_NUM_SET 0x0000000f
A2W_PLLB_ANA_KAIP_MASK 0x0000077f
DMA14_TI_INTEN_CLR 0xfffffffe
VPU_ARB_CTRL_UC_RESET 0000000000
IC1_FORCE0_SET_MASK 0xffffffff
CCP2TX_TD_WIDTH 8
PM_CAM0_LDOLPEN_MSB 1
HDMI_VERTB0_WIDTH 22
CAM1_CAMDBWP_WIDTH 32
EMMC_CONTROL1_CLK_FREQ8_LSB 8
EMMC_IRPT_MASK_DCRC_ERR_MSB 21
I2C_SPI_SLV_CR_ENSTAT_MSB 5
PIXELVALVE1_BASE 0x7e207000
DMA13_CS_ERROR_SET 0x00000100
DMA4_CS_DREQ_BITS 3:3
I2C2_DIV_RESET 0x000005dc
A2W_PLLD_DSI1R_MASK 0x000003ff
USB_GHWCFG2_NUM_HOST_CHAN_LSB 17
DMA1_TI_DEST_DREQ_MSB 6
SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_CLR 0xffffffcf
SYSAC_DBG_PRIORITY_RESET 0000000000
CM_AVEOCTL_ENAB_MSB 4
DMA12_TI_DEST_INC_MSB 4
AUX_ENABLE_MINIUART 0x01
L1_L1_SANDBOX_START6_CTRL_BITS 0:0
HDMI_RAM_PACKET_11_6_MASK 0xffffffff
GRMSADR 0x1A005C00 + 0x0C:RW
I2C_SPI_SLV_ICR_RESET 0000000000
OTP_CONFIG_REG_MASK 0x00000007
PM_RSTC_HRCFG_LSB 20
SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_BITS 3:2
APERF1_BW0_CTRL_ID_MSB 12
USB_GRSTCTL_H_SFT_RST_RESET 0x0
DMA15_CS_PANIC_PRIORITY_CLR 0xff0fffff
DMA0_NEXTCONBK 0x7e00701c:RO
L1_IC1_PRIORITY_MASK 0x0000ffff
L1_IC1_BP_HITS_MASK 0000000000
DMA4_TI_DEST_WIDTH_LSB 5
I2CS_0 0x7e205000 + 0x04:RW
I2CS_1 0x7e804000 + 0x04:RW
I2CS_2 0x7e805000 + 0x04:RW
I2CS_3 I2C_BASE_3 + 0x04:RW
L1_D_FLUSH_S_WIDTH 30
EMMC_STATUS_CARD_INSERT_SET 0x00010000
GROPCTR_FBC_CZ_FE_MISSES 0x2C
A2W_PLLC_CTRL_PWRDN_LSB 16
CM_AVEOCTL_FRAC_BITS 9:9
AVE_OUT_Y_COEFF_RED_COEFF_BITS 29:20
AVE_IN_CURRENT_LINE_NUM 0x7e910024:RW
SD_CS_STBY_CLR 0xfffffff7
A2W_PLLD_PERR_MASK 0x000003ff
AVE_OUT_CTRL_INVERT_DSYNC_MSB 18
APERF1_BW2_RTRANS_RESET 0000000000
CM_PLLD_HOLDDSI0_SET 0x00000002
SYSAC_L2_ARBITER_CONTROL_LIMIT_RESET 0x0
PM_XOSC_USESEC_MSB 0
DMA1_TI_DEST_WIDTH_BITS 5:5
DSI1_RXPKT_FIFO_MASK 0xffffffff
PM_CAM0_CTRLEN_MSB 0
DMA6_TI_INTEN_BITS 0:0
PM_DSI0_CTRLEN_LSB 0
L1_IC0_RAS_POPS 0x7ee02054:RO
MPHI_INTCTRL_OMFUFLW_CLR 0xffffefff
SMIDS_SWAP 22
CM_V3DCTL_GATE_CLR 0xffffffbf
GP_FSEL4_FSEL44_LSB 12
A2W_SMPS_L_SPVR_RESET 0000000000
USB_PCGCR_GATE_HCLK_RESET 0x0
I2CS_x(x) MACRO
CM_TD0DIV_DIV_MSB 23
DMA9_NEXTCONBK_ADDR_LSB 5
CM_CAM1CTL_KILL_CLR 0xffffffdf
SCALER_DISPECTRL_CB_BUSY_BITS 31:10
SLIM_DCC5_CON_MASK 0xffff0070
HDMI_SCHEDULER_CONTROL_HSYNC_PHYST_EN_CLR 0xfffeffff
A2W_PLLB_DIG3R_WIDTH 24
EMMC_CONTROL1_CLK_EN_LSB 2
L1_IC1_CONTROL_BP_DISABLE_CLR 0xfffffff7
DMA13_TI_DEST_WIDTH_BITS 5:5
PM_AVS_EVENT_ALERT_H264_I_MSB 2
USB_GHWCFG3_PACKET_COUNT_WIDTH_LSB 4
PM_AVS_INTEN_ALERT_PERI_A_LSB 0
APERF0_GEN_CTRL_ENABLE_BITS 0:0
DMA7_DEST_AD_D_ADDR_LSB 0
CCP2TX_TS_IS_CLR 0xfffeffff
CM_TD0CTL_KILL_MSB 5
USB_DCTL_TST_CTL_RESET 0x0
CM_INTEN_BURSTDONE_SET 0x00800000
VPU_ARB_CTRL_L2_LIMIT_LSB 0
DMA4_DEBUG_LITE_SET 0x10000000
L1_L1_SANDBOX_START4_CTRL_MSB 0
DMA9_CS_END_BITS 1:1
CM_CAM1CTL_SRC_BITS 3:0
I2C_SPI_SLV_CR_RXE_SET 0x00000200
GP_FSEL2_FSEL21_MSB 5
SD_DQLCRC5_FALL_RESET 0x0
MPHI_CTRL_ENABLE_MSB 31
USB_GINTMSK_INCOMPL_ISO_OUT_MSB 21
A2W_PLLA_CORE_CHENB_MSB 8
SD_DQRCRC10_FALL_SET 0x0000ffff
MPHI_C0INDDB_TENDINT_MSB 29
USB_GNPTXFSIZ_NP_TXF_DEP_LSB 16
USB_GUSBCFG_FORCE_DEV_MODE_MSB 30
DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
HDMI_BCH_CONFIGURATION_MASK 0x000001ff
CAM0_CAMDCS_RESET 0000000000
SCALER_DISPCTRL0 0x7e400040:RW
SCALER_DISPCTRL1 0x7e400050:RW
SCALER_DISPCTRL2 0x7e400060:RW
SMI_DD_MASK 0x0003ffff
USB_HCINTMSK1 0x7e98052c:RW
USB_HCINTMSK2 0x7e98054c:RW
USB_HCINTMSK3 0x7e98056c:RW
USB_HCINTMSK4 0x7e98058c:RW
A2W_SMPS_A_MODE_MASK 0x00000001
USB_HCINTMSK6 0x7e9805cc:RW
USB_HCINTMSK7 0x7e9805ec:RW
CAM1_CAMIVWIN_MASK 0xffffffff
DMA_INT_STATUS 0x7e007fe0:RO
USB_HPTXFSIZ 0x7e980100:RW
SH_RSP2_CID_CSD_SET 0xffffffff
USB_DIEPTSIZ15_MASK 0xffffffff
USB_GHWCFG3_VENDOR_CTL_INTERFACE_LSB 9
PM_IMAGE_POWUP_CLR 0xfffffffe
JCTRL_START (1 << 7)
PIXELVALVE_VSIZE_0 PIXELVALVE0_VSIZE
PIXELVALVE_VSIZE_1 PIXELVALVE1_VSIZE
DMA8_CS_ACTIVE_SET 0x00000001
CM_OSCFREQF_MASK 0x000fffff
CM_PLLD_LOADDSI1_MSB 2
A2W_HDMI_CTL_RCAL_SELDIV_SET 0x00000030
MS_SEMA_21_MASK_SET 0x00000001
TRANSPOSER_CONTROL 0x7e00400c:RW
V3D_FDBGB_WIDTH 32
HD_HDM_CTL_RFSTBY_MSB 7
DMA2_CS_PAUSED_MSB 4
CM_TECDIV 0x7e1010cc:RW
PM_IMAGE_ISPRSTN_CLR 0xfffffeff
APERF0_BW0_RTWAIT_WIDTH 32
CM_BURSTCTL_ENAB_MSB 4
EMMC_BUS_CTRL_BE_PWR_SET 0x7f000000
CM_OTPCTL_SRC_LSB 0
SLIM_DCC3_PA0_MASK 0x00ffff1f
AUX_MU_LSR_OE 0x02
GROPCTR_FBC_EZ_PBE_MISSES 0x36
USB_GINTMSK_MODE_MIS_SET 0x00000002
PM_DFT_MASK 0x00000003
DMA0_TI_INTEN_SET 0x00000001
MPHI_HSINDCF_EMPTY_BITS 31:31
PM_PROC_ARMRSTN_MSB 6
DMA6_CS_RESET 0000000000
PIXELVALVE1_VERTB_EVEN 0x7e207020:RW
AUX_SPI_CNTL0_HOLD10 0x00003000
HDMI_MAI_FORMAT_MASK 0xffffffff
DMA7_DEBUG_READ_ERROR_BITS 2:2
DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
PM_GRAFX_MRDONE_MSB 4
DMA12_BASE 0x7e007c00
VPU_ARB_CTRL_L2_DELAY_SET 0x0000000c
CM_GP0CTL_MASH_BITS 10:9
CM_AVEOCTL_KILL_CLR 0xffffffdf
PIXELVALVE_VSIZE_x(x) MACRO
A2W_PLLH_DIG0R_WIDTH 24
EMMC_IRPT_EN_DMA_ERR_LSB 28
PM_AVS_EVENT_ALERT_SYSTEM_A_SET 0x00000002
CM_TDCLKEN_SLIMDFT_CLR 0xffffefff
USB_HCINT1 0x7e980528:RW
SYSAC_UC_ARBITER_CONTROL_ALGORITHM_CLR 0xffffff3f
UFCR 0x7e201000 + 0x08:RW
PM_AUDIO_RSTN_MSB 21
SD_RWC_LASTCNT_CLR 0xffe0ffff
PM_IMAGE_POWOK_SET 0x00000002
SMI_DSW0_WPACE_BITS 14:8
MS_SEMA_24_WIDTH 1
VEC_CLMP0_START 0x7e806144:RW
ARM_C1_PERSON 0x00000100
ARM_1_SEMCLRDBG (0x7E00B000 +0x900)+0xE0:RW
DMA6_DEBUG_OUTSTANDING_WRITES_BITS 7:4
MPHI_INTSTAT_RX1DISC_RESET 0x0
DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
SD_CS_SDUP_SET 0x00008000
CM_AVEOCTL_SRC_BITS 3:0
CM_DSI1ECTL_FRAC_SET 0x00000200
HDMI_ENCODER_CTL_RESET 0000000000
V3D_BPCA_MASK 0xffffffff
USB_DOEPCTL1_MASK 0xffffffff
TS_TSENSCTL_RSTDELAY_SET 0x03fc0000
PRM_CV_MASK 0xffffffff
A2W_PLLD_ANA0R_MASK 0x00ffffff
L1_D_PRIORITY_c1_uc_priority_MSB 23
SLIM_DMA_DC6_MASK 0xffffffff
CM_UARTCTL_SRC_SET 0x0000000f
HDMI_CEC_TX_DATA_1_MASK 0xffffffff
DMA6_CS_PRIORITY_MSB 19
SH_HBLC_WIDTH 16
HDMI_RAM_PACKET_9_5_WIDTH 32
USB_GINTMSK_SESS_REQ_INT_LSB 30
GP_PUDCLK0_PUDCLKn0_LSB 0
ARM_MS_EMPTY 0x40000000
A2W_PLLD_CTRL_PDIV_BITS 14:12
MPHI_C0INDS_DISCARD_CLR 0x7fffffff
A2W_SMPS_CTLB0R_RESET 0000000000
HDMI_READ_POINTERS_DRFT_HOLD_WR_MSB 23
AVE_OUT_STATUS_VBACK_PORCH_CLR 0xfffffeff
A2W_PLLH_FRACR_WIDTH 20
IC0_FORCE0_WIDTH 32
HDMI_VERTA0_MANUAL_VAL0_LSB 0
PWM_CTL_SBIT4_LSB 27
HD_MAI_CTL_EMPTY_SET 0x00000400
EMMC_TUNE_STEPS_DDR_STEPS_LSB 0
GP_AFEN1_RESET 0000000000
USB_DSTS_SUSP_STS_SET 0x00000001
SMI_DSR0_RSTROBE_BITS 6:0
HDMI_RAM_PACKET_5_7_WIDTH 32
A2W_PLLB_CTRLR_MASK 0x000373ff
CM_VPUCTL_SRC_MSB 3
DMA2_CS_ACTIVE_SET 0x00000001
A2W_PLLA_CORE_BYPEN_CLR 0xfffffdff
A2W_SMPS_B_MULTI_MASK 0000000000
DMA10_NEXTCONBK_MASK 0xffffffe0
A2W_PLLB_CTRLR_RESET 0x00010000
EMMC_HWCAP0_SLOT_TYPE_MSB 31
ASB_H264_M_CTRL_EMPTY_MSB 2
DMA7_DEBUG_VERSION_SET 0x0e000000
DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
PCM_TXC_A_CH2WEX_CLR 0xffff7fff
L1_D_CONTROL_DC0_FLUSH_SET 0x00000002
EMMC_INTERRUPT_ERR_LSB 15
SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_MSB 3
SLIM_DCC7_CON_WIDTH 32
GROPCTR_TU1_CACHE_REQ_STALLS 0x1B
DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
USB_DOEPDMAB15_MASK 0xffffffff
SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_LSB 6
CM_DFTDIV_DIV_LSB 12
SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_RESET0x0
DMA15_SOURCE_AD_S_ADDR_CLR 0x00000000
PWM_STA_GAPO4_CLR 0xffffff7f
PM_PADS6_MASK 0x00000123
L1_D0_WR_HITS_WIDTH 0
GP_FSEL1_FSEL17_CLR 0xff1fffff
DPHY_CSR_GLBL_DQ_DLL_PHASE_LD_VL 0x7ee07010:RW
AVE_OUT_STATUS_COEFF_ERROR_LSB 2
CM_TSENSCTL_FRAC_BITS 9:9
APERF0_BW2_CTRL_ID_EN_SET 0x20000000
USB_DTHRCTL_ISO_THR_EN_MSB 1
HDMI_VERTA0_MANUAL_VSP0_SET 0x01f00000
SD_SE_RL_EN_SET 0x10000000
HDMI_RAM_PACKET_7_4_RESET 0000000000
SCALER_DISPECTRL_Y_NE_CTRL_MSB 31
DMA5_TI_SRC_INC_LSB 8
DMA7_DEBUG_DMA_ID_SET 0x0000ff00
EMMC_IRPT_EN_MASK 0xffffffff
SCALER_DISPCTRL_WIDTH 32
CM_DSI0PCTL_BUSY_SET 0x00000080
A2W_PLLB_ARM_MASK 0x000003ff
USB_GUSBCFG_ULPI_EXT_VBUS_IND_BITS 21:21
SYSAC_V3D_LIMITER_ENABLE_SET 0x00000001
CM_ARMCTL_BUSYD_LSB 8
A2W_HDMI_CTL_RCAL_SELDIV_CLR 0xffffffcf
DMA4_TI_TDMODE_MSB 1
AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_MSB 31
A2W_PLLH_ANA_MULTI_MASK 0000000000
SD_SECEND3_ADDR_MS_LSB 13
A2W_PLLH_PIX_DIV_BITS 7:0
A2W_PLLD_ANA_SCTL_UPDATE_BITS 3:3
DMA2_TI_PERMAP_MSB 20
EMMC_DMA_STATUS_RESET 0000000000
EMMC_INTERRUPT_ATA_ERR_BITS 29:29
AVE_IN_STATUS_CSYNC_FIELD_BITS 13:13
DMA9_TXFR_LEN_XLENGTH_CLR 0xffff0000
CM_BURSTCTL_KILL_CLR 0xffffffdf
EMMC_CMDTM_TM_AUTO_CMD_EN_SET 0x0000000c
A2W_SMPS_LDO1R_MASK 0x00ffffff
CM_SDCCTL_SRC_MSB 3
PM_AVS_EVENT_WIDTH 5
VEC_ENC_PrimaryControl 0x7e806068:RW
HD_HDM_CTL_PDSTBY_CLR 0xffffffcf
A2W_HDMI_CTL_HFEN_HFEN_MSB 0
CM_INTEN_GAIND_CLR 0xfffffff7
SLIM_DCC6_PA0_WIDTH 24
PWM_CTL_SBIT1_SET 0x00000008
SMI_DSW1_WSETUP_LSB 24
UART_MSR_RI_SET 0x00000040
GP_AFEN2_AFENn64_MSB 5
EMMC_FORCE_IRPT_OEM_ERR_LSB 30
CM_GP1CTL_KILL_SET 0x00000020
IC1_SRC0_MASK 0xffffffff
HD_MAI_CTL_FULL_SET 0x00000800
SMI_DSW2_WFORMAT_MSB 23
CM_UARTCTL_FRAC_CLR 0xfffffdff
TB_JTB_CONFIG_TDO_RISE_CLR 0xfffffbff
GP_FSEL0_FSEL06_SET 0x001c0000
PM_DSI1_LDOCTRL_BITS 20:3
DMA12_TI_BURST_LENGTH_BITS 15:12
AUX_SPI_CNTL0_INFALL 0x00000000
SD_DQLCRC2_FALL_RESET 0x0
GRSVFMT 0x1A005800 + 0x0C:RW
SD_CS_STATEN_BITS 6:6
USB_GHWCFG2_TOKEN_QUEUE_DEPTH_LSB 26
USB_DOEPDMAB5_WIDTH 32
EMMC_HWCAP1_RETUNE_TMR_MSB 11
EMMC_BOOT_TIMEOUT_TIMEOUT_LSB 0
CM_TDCLKEN_PLLBDIV2_LSB 5
HDMI_PERT_DATA_MASK 0x00ffffff
CAM1_CAMISTA_WIDTH 32
SD_DQRCRC8_RISE_BITS 31:16
A2W_HDMI_CTL0R_RESET 0x00470238
SMI_DSW3_WPACEALL_MSB 15
USB_DTHRCTL_RX_THR_LEN_BITS 26:17
DMA3_NEXTCONBK_MASK 0xffffffe0
A2W_PLLC_DIG1_RESET 0x00004000
GRDAADR0 0x1A005A00 + 0x40:RW
GRDAADR1 0x1A005A00 + 0x44:RW
GRDAADR2 0x1A005A00 + 0x48:RW
GRDAADR3 0x1A005A00 + 0x4C:RW
USB_DOEPCTL0_STALL_LSB 21
GRDAADR5 0x1A005A00 + 0x54:RW
GRDAADR6 0x1A005A00 + 0x58:RW
GRDAADR7 0x1A005A00 + 0x5C:RW
INTERRUPT_ISP ((64) + 8 )
HDMI_CP_STATUS_WIDTH 32
A2W_PLLD_ANA_VCO_RANGE_MSB 0
SYSAC_H264_PRIORITY_RESET 0000000000
EMMC_IRPT_EN_OEM_ERR_LSB 30
USB_DOEPCTL0_SET_ODD_FR_BITS 29:29
CM_DSI1PCTL_ENAB_SET 0x00000010
DMA_ENABLE_EN4_SET 0x00000010
SMI_DSW3_WSWAP_CLR 0xffbfffff
HDCP_KEY_KY0_WIDTH 32
A2W_PLLH_PIX_BYPEN_MSB 9
USB_PCGCR_MASK 0x0000000f
EMMC_INTERRUPT_TUNE_ERR_BITS 26:26
DMA3_TI_DEST_DREQ_CLR 0xffffffbf
PM_PADS4_SPARE_BITS 4:4
SH_CMD_FAIL_FLAG_BITS 14:14
JOADDR 0x7e005000 + 0x38:RW
HDMI_DETECTED_HORZB_MANUAL_HSP_BITS 19:10
HDMI_PERT_INSERT_ERR_SEP_RESET 0000000000
DMA3_TI_DEST_WIDTH_MSB 5
CMI_USBCTL 0x7e802010:RW
CM_EVENT_FGAIND_BITS 13:13
MS_SEMA_28_MASK_SET 0x00000001
DMA8_TI_INTEN_CLR 0xfffffffe
USB_GOTGCTL_CON_ID_STS_MSB 16
ARM_1_MAIL0_STA (0x7E00B000 +0x900)+0x98:RW
HDMI_SCHEDULER_CONTROL_ENC_ONLY_WHEN_AUTH_MSB 6
L2_APB_ID 0x4c324343
CM_GNRICCTL_FLIP_MSB 11
DMA7_CS_ERROR_SET 0x00000100
A2W_XOSC0_MASK 0x00ffffff
EMMC_INTERRUPT_CCRC_ERR_BITS 17:17
GP_AFEN0_AFENn0_LSB 0
A2W_PLLC_ANA1R_MASK 0x00ffffff
A2W_PLLC_PER_DIV_SET 0x000000ff
CCP2TX_TC 0x7e001000:RW
CCP2TX_TD 0x7e001024:RW
EMMC_CONTROL1_RESET 0000000000
USB_HCCHAR0_EP_NUM_BITS 14:11
USB_DIEPCTL0_SNAK_MSB 27
USB_GINTMSK_INCOMPL_ISO_IN_MSB 20
CCP2TX_TS 0x7e001004:RW
DMA0_DEBUG_VERSION_LSB 25
A2W_XOSC_CTRL_HDMIEN_MSB 1
A2W_XOSC_CTRL_PLLDOK_CLR 0xfffdffff
A2W_PLLH_ANA_STAT_RCALCODE_BITS 19:16
DMA9_DEBUG_RESET 0000000000
DMA9_TI_SRC_INC_CLR 0xfffffeff
DMA12_CS_ACTIVE_MSB 0
IC0_MASK3_MASK 0x77777777
SMI_DSW3_WIDTH 32
USB_HCCHAR2_MASK 0xffffffff
AVE_IN_CTRL_OVERRUN_IRQ_EN_BITS 0:0
DMA13_TI_DEST_INC_MSB 4
L1_D1_WR_HITS 0x7ee02190:RO
ARM_0_SEM3 (0x7E00B000 +0x800)+0x0C:RW
USB_DCFG_PER_FR_INT_SET 0x00001800
APERF0_BW1_CTRL_EN_BITS 30:30
CM_PLLTCNT0_CNT_SET 0x00ffffff
HDMI_VERTB0_MANUAL_VBP0_CLR 0xfffffeff
TB_ADDR_WIDTH 32
A2W_PLLC_ANA_SCTL_SEL_BITS 2:0
HDMI_FIFO_CTL_RECENTER_DONE_LSB 14
A2W_SMPS_CTLC2R_WIDTH 24
EMMC_FORCE_IRPT_DMA_ERR_SET 0x10000000
PWM_STA_WERR1_SET 0x00000004
CAM1_CAMIBSA0_WIDTH 32
A2W_PLLB_SP1R_WIDTH 10
DC1START 0xffffffff:RW
I2C_SPI_SLV_MIS_TXMIS_CLR 0xfffffffd
APERF0_BW0_ATWAIT_MASK 0xffffffff
DMA2_TXFR_LEN_WIDTH 30
PWM_CTL_POLA2_SET 0x00001000
CPG_Debug1_MASK 0xffffffff
SPI_CS_INTD_CLR 0xfffffdff
APERF0_BW2_CTRL_BUS_SET 0x0000001f
CCP2TX_TAC_PTATADJ_SET 0x0f000000
CM_TCNTCNT_CNT_CLR 0xff000000
SD_DQRCRC0_FALL_BITS 15:0
A2W_SMPS_C_CLK_TDEN_LSB 3
HDMI_SCHEDULER_CONTROL_VSYNC_PHYST_EN_SET 0x00020000
A2W_PLLC_CTRL_PDIV_LSB 12
SMI_DD_RESET 0000000000
ASB_V3D_S_CTRL_EMPTY_MSB 2
CM_INTEN_FGAINA_MSB 10
CM_TIMERCTL 0x7e1010e8:RW
L1_D1_RD_HITS_WIDTH 0
PM_IMAGE_MASK 0x007f11ff
CCP2TX_TS_TFP_BITS 6:6
DMA1_TI_SRC_IGNORE_CLR 0xfffff7ff
CCP2TX_TS_TQL_BITS 12:8
DMA4_STRIDE_WIDTH 32
SD_PT2_T_INIT5_LSB 0
CM_LOCK_FLOCKC_BITS 10:10
CM_GP1CTL_SRC_MSB 3
GR_VCACHE_BASE 0x1a00a000
USB_DIEPDMA1 0x7e980934:RW
PIXELVALVE0_HORZA 0x7e20600c:RW
PIXELVALVE0_HORZB 0x7e206010:RW
USB_DIEPDMA4 0x7e980994:RW
USB_DIEPDMA5 0x7e9809b4:RW
CM_DSI0ECTL_SRC_MSB 3
USB_DIEPDMA7 0x7e9809f4:RW
USB_DIEPDMA8 0x7e980a14:RW
USB_DIEPDMA9 0x7e980a34:RW
DMA2_STRIDE_S_STRIDE_LSB 0
EMMC_HWCAP0_HS_BITS 21:21
A2W_PLLD_FRACR_WIDTH 20
DMA0_TI_WAIT_RESP_BITS 3:3
DMA10_DEBUG_FIFO_ERROR_CLR 0xfffffffd
HD_VID_CTL_EMPRGB_MSB 19
CCP2TX_TBA_ADDR_SET 0x3fffffff
L2_CONT_OFF_l2_disable_SET 0x00000001
UART_LCR_LOOP_BITS 4:4
CM_DSI0ECTL_KILL_SET 0x00000020
DMA4_TI_INTEN_MSB 0
CAM1_CAMIHSTA_RESET 0000000000
I2C1_A_MASK 0x0000007f
USB_GHWCFG4_EN_PWROPT_SET 0x00000010
A2W_SMPS_LDO0R 0x7e1028d0:RW
HDMI_READ_POINTERS_DRFT_ALMOST_FULL_CLR 0xffdfffff
FPGA_MB_XC1_BUILD_NUM_MASK 0xffffffff
A2W_PLLC_CORE0_DIV_SET 0x000000ff
V3D_PCTR10 0x7ec006d0:RW
V3D_PCTR11 0x7ec006d8:RW
V3D_PCTR12 0x7ec006e0:RW
V3D_PCTR13 0x7ec006e8:RW
V3D_PCTR14 0x7ec006f0:RW
V3D_PCTR15 0x7ec006f8:RW
USB_DIEPDMAn(n) MACRO
USB_GRXSTSP_HST_DPID_MSB 16
PCM_INTSTC_A_RXERR_SET 0x00000008
A2W_PLLC_ANA_SSCS_STEP_MSB 15
SD_DQRCRC12_RISE_MSB 31
SMI_DSW3_WFORMAT_SET 0x00800000
USB_DOEPCTL4_MASK 0xffffffff
A2W_PLLD_CTRL_PDIV_MSB 14
SD_SECEND2_ADDR_LS_BITS 12:0
A2W_PLLD_DSI0_BYPEN_SET 0x00000200
EMMC_STATUS 0x7e300024:RW
GP_FSEL5_FSEL59_LSB 27
A2W_PLLB_SP0_CHENB_SET 0x00000100
MS_IREQ_1 0x7e000088:RW
AVE_IN_CURRENT_LINE_BUF1_RESET 0000000000
DMA4_CS_DISDEBUG_LSB 29
MPHI_INTCTRL_RX0DISC_CLR 0xfffffffe
USB_HCINT0_FRM_OVRUN_RESET 0x0
EMMC_INTERRUPT_CEND_ERR_BITS 18:18
CM_SMICTL_MASK 0x000003bf
A2W_SMPS_LDO1R 0x7e1028d4:RW
USB_DOEPINT0_EP_DISBLD_BITS 1:1
DSI1_TXPKT_CMD_FIFO_MASK 0x000000ff
DMA3_SOURCE_AD_WIDTH 32
MPHI_INTCTRL_HSDISC_BITS 16:16
PM_PADS0_HYST_BITS 3:3
A2W_PLLB_ANA_SCTL_UPDATE_BITS 3:3
USB_DIEPCTL0_ENA_MSB 31
PM_GRAFX_POWUP_CLR 0xfffffffe
CM_TIMERCTL_SRC_MSB 1
USB_DOEPINT0_IN_TKN_TXFEMP_SET 0x00000010
MS_SEMA_1_MASK_MSB 0
PM_XOSC_USESEC_SET 0x00000001
DMA0_TXFR_LEN_WIDTH 30
EMMC_FORCE_IRPT_ADMA_ERR_MSB 25
SD_SF_MDLL_CAL_CLR 0xfffffe00
USB_GINTMSK_USB_SUSP_CLR 0xfffff7ff
DMA0_TI_INTEN_CLR 0xfffffffe
VPU_ARB_CTRL_UC_ALGORITHM_BITS 7:6
SH_CMD_NEW_FLAG_CLR 0xffff7fff
APERF1_BW1_RTWAIT_MASK 0xffffffff
DMA1_TI_NO_WIDE_BURSTS_BITS 26:26
DMA10_DEBUG_FIFO_ERROR_LSB 1
DSI0_CTRL_CTRL0_SET 0x00000001
DMA10_SOURCE_AD_WIDTH 32
CM_PLLC_HOLDCORE0_BITS 1:1
AVE_IN_LINE_LENGTH_LINE_LENGTH_SET 0x00000fff
MPHI_C0INDCF_HANDLE_SET 0x0ff00000
DMA0_DEST_AD_D_ADDR_LSB 0
PM_PADS0_SLEW_SET 0x00000010
PWM_CTL_CLRF1_CLR 0xffffffbf
USB_GPVNDCTL_REG_DATA_SET 0x000000ff
GP_GPTEST_SMPS_MSB 0
ACISFIFO 0x1C004800 + 0x04:RW
CM_GP2CTL_FRAC_MSB 9
USB_DIEPCTL1 0x7e980920:RW
TE_1VSWIDTH_MASK 0xffffffff
CM_DSI1EDIV_DIV_CLR 0xffff000f
IC1_C_WIDTH 4
A2W_PLLB_ANA_SSCS_MODE_LSB 16
SMI_DC_PANICW_SET 0x0003f000
DMA13_TI_DEST_DREQ_CLR 0xffffffbf
USB_DIEPINT0_IN_EP_NAK_EFF_LSB 6
HDMI_RAM_PACKET_3_4_WIDTH 32
IC0END L1_I_FLUSH_E
SD_DQLCRC12_FALL_CLR 0xffff0000
DMA3_TI_WAITS_MSB 25
MS_STATUS 0x7e000080:RO
A2W_PLLA_PER_RESET 0x00000100
CM_PLLD_HOLDDSI1_LSB 3
USB_DOEPDMA7 0x7e980bf4:RW
USB_HCDMA2_MASK 0xffffffff
CAM0_CAMIDS_RESET 0000000000
DMA14_DEBUG_LITE_SET 0x10000000
CM_TDCLKEN_PLLCBYP_CLR 0xfffffffb
A2W_PLLC_CORE0_BYPEN_CLR 0xfffffdff
L1_D_CONTROL_DC_DISABLE_SET 0x00000001
APERF1_BW2_RTWAIT_WIDTH 32
USB_DSTS_SUSP_STS_MSB 0
USB_DOEPCTL0_DPID_LSB 16
USB_DOEPDMA9 0x7e980c34:RW
L2_CONT_OFF_l2_no_wr_allocate_CLR 0xfffffffd
A2W_PLLA_CCP2_BYPEN_BITS 9:9
GP_PUDCLK2_PUDCLKn64_CLR 0xffffffc0
DMA14_DEST_AD_MASK 0xffffffff
DSI0_HS_DLT4_WIDTH 10
SH_VDD 0x7e202030:RW
TB_JTB_CONFIG_D_HOLD_BITS 13:12
GP_FEN1_FENn32_SET 0xffffffff
A2W_PLLA_CTRL_PRSTN_SET 0x00020000
CM_CAM0CTL_ENAB_BITS 4:4
MPHI_OUTDDB_TENDINT_MSB 29
CM_GP1CTL_KILL_BITS 5:5
PCM_CH1POS_LSB 20
EMMC_CONTROL2_UHSMODE_SET 0x00070000
USB_DOEPINT0_TIMEOUT_BITS 3:3
PM_PROC_ISPOW_SET 0x00000004
L1_IC1_PRIORITY_IC1_APRIORITY1_CLR 0xffffff0f
CM_INTEN_FLOSSC_MSB 16
HDMI_RAM_PACKET_5_1_RESET 0000000000
GP_FSEL4_FSEL45_CLR 0xfffc7fff
EMMC_CMDTM_TM_DAT_DIR_SET 0x00000010
A2W_PLLH_AUXR_WIDTH 10
USB_GINTMSK_INCOMPL_ISO_IN_RESET 0x0
SMI_DSW2_WWIDTH_SET 0xc0000000
GP_SEN1_SEN_CLR 0xffc00000
CM_CAM1CTL_BUSYD_MSB 8
PWM_DMAC_DREQ_MSB 7
L1_L1_SANDBOX_PERI_BR 0x7ee02840:RW
USB_HPTXSTS_HPTXQTOP_LSB 24
DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
DMA15_STRIDE_S_STRIDE_MSB 15
SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_RESET 0x0
DMA8_CS_DISDEBUG_BITS 29:29
HDMI_RAM_PACKET_6_0_RESET 0000000000
HDMI_RAM_PACKET_1_3_RESET 0000000000
CM_PLLC_LOADPER_MSB 6
A2W_PLLA_CORE_MASK 0x000003ff
DMA7_CS_PRIORITY_SET 0x000f0000
SH_HSTS_BUSY_IRPT_MSB 10
SD_DQLCRC10_MASK 0xffffffff
I2C_SPI_SLV_CR_HOSTCTRLEN_CLR 0xffffefff
TB_JTB_CONFIG_SBITS_MSB 4
PIXELVALVE2_C_WIDTH 24
GP_FSEL3_FSEL31_MSB 5
CM_OSCFREQF_FRAC_MSB 19
EMMC_CONTROL2_WIDTH 32
CM_SYSCTL_WIDTH 7
PCM_RXC_A_CH2WEX_CLR 0xffff7fff
CM_TD0CTL_BUSY_CLR 0xffffff7f
CM_CCP2CTL_ENAB_BITS 4:4
HDMI_SCHEDULER_CONTROL_VSYNC_RESET_VAL_CLR 0xffc3ffff
USB_GAHBCFG_DMA_EN_RESET 0x0
PM_AVS_STAT_ALERT_V3D_G_SET 0x00000008
SCALER_DISPBASE0_MASK 0xffffffff
SD_SC_WL_LSB 0
PIXELVALVE1_VERTA_MASK 0xffffffff
MPHI_INTCTRL_OMFUFLW_MSB 12
HD_VID_CTL_HPOL_MSB 27
FPGA_STATUS0_SD_WP_SET 0x00000010
SD_SD_MASK 0xf1f71fff
V3D_PCTR10_WIDTH 32
APERF0_BW1_CTRL_ID_EN_RESET 0x0
SLIM_DCC6_STAT_MASK 0xc0ff00c7
I2C_SPI_SLV_HCTRL_DATA_MSB 7
A2W_SMPS_A_MODE_BSTPWMB_LSB 0
SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_BITS 5:4
CM_TDCLKEN_USBDFT_LSB 11
DMA3_CS_PANIC_PRIORITY_BITS 23:20
ARM_1_BELLCLRDBG (0x7E00B000 +0x900)+0xE4:RW
SD_RWC_WRTOVR_MSB 15
DMA6_NEXTCONBK 0x7e00761c:RO
SD_SF_PGEHLD_T_CLR 0xe007ffff
SD_DQLCRC4_RISE_LSB 16
DMA_ENABLE_EN0_BITS 0:0
SD_DQLCRC4_WIDTH 32
PCM_INTSTC_A_MASK 0x0000000f
CM_HSMDIV_DIV_LSB 4
UART_MSR_DDCD_CLR 0xfffffff7
DMA15_CS_END_SET 0x00000002
CM_PLLC_DIGRST_MSB 9
CM_H264CTL_ENAB_BITS 4:4
DMA2_CS_RESET_MSB 31
DMA12_TI_SRC_WIDTH_SET 0x00000200
DSI0_CMD_PKTC_WIDTH 32
SH_HSTS_REW_TIME_OUT_LSB 7
CM_GNRICCTL_BUSY_SET 0x00000080
A2W_PLLH_ANA_KAIPR_RESET 0x0000033a
SD_CS_EXCEPTION_SET 0x00800000
CCP2TX_TIC_TQIE_MSB 2
SMI_DSR1_RWIDTH_BITS 31:30
PRM_CS 0x7e20d000:RW
MPHI_HSINDFS_CFIFOLVL_BITS 31:16
A2W_HDMI_CTL0R 0x7e102880:RW
SCALER_DISPSTAT_PROF_IRQ_BITS 31:0
CM_PULSEDIV_MASK 0x00fff000
USB_DOEPINT0_EP_DISBLD_LSB 1
APERF1_BW0_RTWAIT_WIDTH 32
CAM0_CAMIBEA0 0x7e800114:RW
CAM0_CAMIBEA1 0x7e800308:RW
ARM_MC_OPPISEMPTYIRQEN 0x00000004
HDMI_AN_INFLUENCE_2_MASK 0xffffffff
VEC_CPS1617_CPS1819_WIDTH 32
SD_CS_EN_SET 0x00000002
FPGA_CTRL0_SW_SPI_SCL_CLR 0xffffffbf
GP_FSEL4_FSEL41_SET 0x00000038
USB_GNPTXSTS_TX_Q_SPC_AVAIL_CLR 0xff00ffff
A2W_PLLB_ANA_SCTL_WIDTH 5
CM_PULSEDIV_DIV_BITS 23:12
PIXELVALVE0_INTEN 0x7e206024:RW
SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_LSB 8
GP_REN0_RENn0_BITS 31:0
VEC_ENC_RevID_MASK 0xffffffff
V3D_DBSCS_MASK 0xffffffff
AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_CLR 0x7fffffff
DMA5_CS_ERROR_LSB 8
GP_SET2_SETn64_MSB 5
HDMI_TX_PHY_TX_PHY_SPARE_RESET 0xffff0000
A2W_HDMI_CTL1R 0x7e102884:RW
DMA_ENABLE_EN9_MSB 9
FPGA_CTRL0_OFFSET 0x08
SMI_CS_PXLDAT_RESET 0x0
CM_GP2CTL_ENAB_LSB 4
CM_AVEOCTL 0x7e1011b8:RW
CM_TD0CTL_RESET 0000000000
A2W_XOSC_CTRLR_WIDTH 8
PWM_STA_FULL1_LSB 0
SCALER_DISPCTRL_DSP1_IRQ_CTRL_MSB 10
USB_GOTGINT_SES_END_DET_LSB 2
HDCP_KEY_CTL_MASK 0x00000007
DMA0_DEBUG_OUTSTANDING_WRITES_MSB 7
FPGA_DCM_RD_DATA 0x7e20b618:RO
SD_SB_INHIBIT_LA_MSB 8
A2W_PLLD_CTRL_PRSTN_CLR 0xfffdffff
HD_MAI_CTL_CHNUM_CLR 0xffffff0f
HDMI_RAM_PACKET_5_0 0x7e9024b4:RW
HDMI_RAM_PACKET_5_1 0x7e9024b8:RW
HDMI_RAM_PACKET_5_2 0x7e9024bc:RW
HDMI_RAM_PACKET_5_3 0x7e9024c0:RW
HDMI_RAM_PACKET_5_4 0x7e9024c4:RW
HDMI_RAM_PACKET_5_5 0x7e9024c8:RW
HDMI_RAM_PACKET_5_6 0x7e9024cc:RW
HDMI_RAM_PACKET_5_7 0x7e9024d0:RW
HDMI_RAM_PACKET_5_8 0x7e9024d4:RW
CCP2TX_TIC_TQIE_BITS 2:2
MPHI_CTRL_EIGHTBIT_BITS 12:12
SMI_DSW1_WSTROBE_CLR 0xffffff80
DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
EMMC_CONTROL1_CLK_INTLEN_MSB 0
DSI1_TXPKT_CMD_FIFO 0x7e70001c:RW
CMI_USBCTL_MASK 0x00000040
A2W_HDMI_CTL2R 0x7e102888:RW
A2W_PLLH_ANA_SCTL_RESET_MSB 4
A2W_HDMI_CTL_HFENR 0x7e102a80:RW
SD_DQRCRC6_RISE_LSB 16
DMA5_TI_BURST_LENGTH_MSB 15
APERF1_BW0_CTRL_EN_MSB 30
GROPCTR_FEVALIDQUADS 0x07
SMI_DSW3_WDREQ_BITS 7:7
PM_GRAFX_ISPOW_LSB 2
V3D_DBQITC_WIDTH 32
A2W_SMPS_C_CLK_USEOSC_LSB 2
APERF0_BW0_CTRL_BUS_LSB 0
MPHI_MINFS_WPTR_LSB 10
PM_RSTC_QRCFG_BITS 13:12
MS_SEMA_8_MASK_MSB 0
FPGA_DCM_CTRL 0x7e20b614:RW
GP_CLR2_RESET 0000000000
EMMC_IRPT_EN_BLOCK_GAP_MSB 2
DMA2_SOURCE_AD_S_ADDR_CLR 0x00000000
SH_HSTS_BLOCK_IRPT_CLR 0xfffffdff
OTP_HDCP_AES_PARITY_ROW (((((((((((((8 +4)+4)+1)+1)+1)+4)+4)+1)+4)+4)+1)+4)+4)
DMA13_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
DMA5_TXFR_LEN_YLENGTH_SET 0x3fff0000
A2W_PLLA_FRACR_RESET 0000000000
IC1_MASK6_RESET 0000000000
CCP2TX_TTC_BI_MSB 23
GP_SET2_WIDTH 6
DMA2_TI_DEST_DREQ_BITS 6:6
MPHI_C0INDFS_MASK 0xffffffff
DMA6_STRIDE 0x7e007618:RO
SLIM_DMA_MC_TX_MASK 0xffffffff
PIXELVALVE2_HORZA_WIDTH 32
A2W_HDMI_CTL3R 0x7e10288c:RW
DMA6_TI_SRC_WIDTH_MSB 9
CM_EVENT_GAINC_MSB 2
HDMI_DVO_TIMING_ADJUST_C_RESET 0x88888888
HD_MAI_CTL_FULL_BITS 11:11
FPGA_A0_BASE 0x7e213000
CM_PWMCTL_BUSY_MSB 7
DMA_DEBUG_READ_LAST_ERR (0)
USB_HCFG_LS_SUPP_BITS 2:2
CM_TSENSDIV_DIV_BITS 16:12
CM_INTEN_GAINH_SET 0x00000010
CAM0_CAMICC 0x7e800130:RW
HDMI_RAM_PACKET_1_2 0x7e90242c:RW
DMA_INT_STATUS_INT6_CLR 0xffffffbf
EMMC_HWCAP0_TCLKFREQ_MSB 5
PM_DSI0_LDOCTRL_LSB 3
CM_TD1CTL_FLIP_SET 0x00000800
HDMI_READ_POINTERS_DRFT_ALMOST_FULL_LSB 21
USB_DOEPINT0_TIMEOUT_CLR 0xfffffff7
HDMI_RAM_PACKET_1_3 0x7e902430:RW
CM_INTEN_LOSSB_LSB 6
HDMI_VERTB0_MANUAL_VSPO0_SET 0x003ffe00
DMA14_TI_DEST_INC_MSB 4
USB_DIEPDMA6_WIDTH 32
CCP2TX_TC_TIP_MSB 15
CM_EVENT_FLOSSA_LSB 14
MPHI_C1INDDB_MORUN_BITS 31:31
APERF1_BW0_CTRL_ID_EN_BITS 29:29
HDMI_CEC_TX_DATA_3_RESET 0000000000
FPGA_MB_SDC_H264_FREQ_WIDTH 32
CM_TIMERCTL_BUSYD_LSB 8
GRSHPX 0x1A005800 + 0x44:RW
FPGA_CTRL0_TERMEN_CLK_CLR 0xfffdffff
APERF1_BW0_ATWAIT_MASK 0xffffffff
CM_SMIDIV_DIV_LSB 4
A2W_SMPS_B_STATR 0x7e1029b0:RW
DMA1_CS_DREQ_MSB 3
SYSAC_SRC_ARBITER_CONTROL_LIMIT_BITS 1:0
CM_SMICTL_KILL_BITS 5:5
USB_DOEPDMAB12_WIDTH 32
ARM_IF_INDEX 0x0000007F
VPU_ARB_CTRL_L2_CHANNEL_INIBIT_CLR 0xffff00ff
L1_L1_SANDBOX_START5_CTRL_CLR 0xfffffffe
GP_FSEL0_FSEL07_LSB 21
USB_DSTS_ERRTIC_ERR_CLR 0xfffffff7
DSI0_DISP0_CTR_WIDTH 32
EMMC_IRPT_MASK_INT_C_CLR 0xfffff7ff
MULTICORE_SYNC_VPU_SEMA_STATUS MULTICORE_SYNC_BASE_ADDRESS + 0xC8:RW
EMMC_CMDTM_CMD_INDEX_SET 0x3f000000
HDMI_RAM_PACKET_6_3_MASK 0xffffffff
HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT_SET 0x00008000
CCP2TX_TS_ARE_LSB 2
UART_MSR_CTS_MSB 4
ST_CS_RESET 0000000000
TB_BOOT_OPT_FPGA_BITS 2:2
DMA_INT_STATUS_INT7_MSB 7
MPHI_C1INDFS_CFIFOLVL_SET 0xffff0000
GP_FSEL6_FSEL65_LSB 15
USB_DTXFSTS15_MASK 0xffffffff
SMI_CS_WRITE_BITS 5:5
USB_DTXFSTS0_SPC_AVAIL_MSB 31
CCP2TX_TSC_RESET 0x00000002
USB_HPRT_OVR_CURR_ACT_BITS 4:4
DMA14_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
USB_HCINT0_ACK_SET 0x00000020
AVE_IN_STATUS_LINE_NUM_HIT_LSB 4
PWM_CTL_MSEN2_BITS 15:15
PWMRNG1 0x7e20c000 + 0x10:RW
PWMRNG2 0x7e20c000 + 0x20:RW
PWMRNG3 0x7e20c000 + 0x30:RW
PWMRNG4 0x7e20c000 + 0x40:RW
SYSAC_TRANS_PRIORITY_MASK 0x000000ff
A2W_PLLA_PER_CHENB_MSB 8
DMA_ENABLE_EN5_LSB 5
USB_DOEPTSIZ13_MASK 0xffffffff
CCP2TX_TS_TII_SET 0x00020000
USB_GAHBCFG_GLBL_INTR_MSK_CLR 0xfffffffe
DMA4_CS_ACTIVE_CLR 0xfffffffe
SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_RESET 0x0
HD_MAI_CTL_FLUSH_RESET 0x0
DMA2_TI_DEST_INC_MSB 4
TB_JTB_CONFIG_BITCNT_BITS 29:23
EMMC_EXRDFIFO_EN_ENABLE_LSB 0
CM_TD0CTL_GATE_MSB 6
SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_CLR 0xffffff3f
SYSAC_V3D_PRIORITY 0x7e00900c:RW
DMA5_DEBUG_FIFO_ERROR_LSB 1
APERF0_APB_ID 0x41584950
APERF1_GEN_CTRL_RESET_RESET 0x0
AUX_SPI_CNTL0_OUTMS 0x00000040
CM_ARMCTL_ENAB_MSB 4
DMA14_TXFR_LEN_XLENGTH_BITS 15:0
PCM_FIFO_A 0x7e203004:RW
HDMI_RAM_PACKET_1_1_WIDTH 32
CM_INTEN_FLOSSB_SET 0x00008000
A2W_PLLA_ANA_SSCS_MODE_MSB 16
A2W_PLLH_RCALR_WIDTH 10
PIXELVALVE1_INTSTAT_MASK 0x000003ff
DMA12_CS_END_SET 0x00000002
CAM0_CAMCLT_RESET 0000000000
AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_MSB 11
HDMI_RAM_PACKET_9_8_RESET 0000000000
USB_DFIFO7_MASK 0xffffffff
CM_LOCK_FLOCKA_LSB 8
DMA5_CS_DISDEBUG_LSB 29
I2C_SPI_SLV_CR_INV_RXF_CLR 0xfffffbff
USB_DIEPCTL0_NAK_STS_MSB 17
V3D_PCTR4 0x7ec006a0:RW
AUX_SPI_CNTL0_FFCLR 0x00000200
INTERRUPT_SW_OFFSET (32)
DSI_STAT 0x7e209000 + 0x2C:RW
APERF0_BW1_CTRL_ID_RESET 0x0
AVE_OUT_CR_COEFF_BLUE_COEFF_MSB 9
SLIM_DCC5_PA0_RESET 0000000000
A2W_SMPS_CTLC2_WIDTH 24
AUX_SPI_STAT_RXEMPTY 0x00000080
SLIM_DMA_DC0_MASK 0xffffffff
HDMI_CPU_CLEAR_RESET 0000000000
USB_GNPTXFSIZ_IN_EP_TXF0_DEP_MSB 31
EMMC_INTERRUPT_READ_RDY_LSB 5
SMI_DSR2_RPACE_SET 0x00007f00
USB_GRXSTSP_DEV_DPID_LSB 15
EMMC_SPI_INT_SPT_SELECT_BITS 7:0
CM_HSMCTL_FRAC_LSB 9
DSI0_INT_EN_RESET 0000000000
UART_MSR_MASK 0x000000ff
PM_USB_CTRLEN_LSB 0
EMMC_STATUS_DAT_ACTIVE_LSB 2
HD_MAI_THR_PANICHIGH_SET 0x3f000000
USB_DTXFSTS5_WIDTH 32
DMA7_TI_SRC_DREQ_MSB 10
CCP2TX_TSC_TSM_MSB 3
PWM_CTL_POLA3_LSB 20
USB_DIEPCTL4_MASK 0xffffffff
AVE_OUT_OFFSET_RED_OFFSET_LSB 16
MPHI_C1INDCF_HANDLE_SET 0x0ff00000
MPHI_HSINDDB_TENDINT_LSB 29
USB_GOTGCTL_HNP_REQ_SET 0x00000200
SD_DQRCRC8_RISE_RESET 0x0
GP_FSEL2_FSEL25_MSB 17
USB_HFNUM_NUM_LSB 0
FPGA_DCM_CTRL_PERI_EN_MSB 27
MPHI_INTSTAT_HSTEND_LSB 31
EMMC_HWCAP0_BASEMHZ_MSB 15
DMA14_CS_RESET_CLR 0x7fffffff
USB_DCTL_CGOUT_NAK_CLR 0xfffffbff
I2C_SPI_SLV_RSR_TXDMAPREQ_CLR 0xfffffffb
AVE_IN_STATUS_OVERRUN_DET_CLR 0xfffffffe
EMMC_HWCAP1_SPI_MODE_SET 0x01000000
CAM1_CAMIVSTA_RESET 0000000000
DMA6_TI_DEST_IGNORE_CLR 0xffffff7f
CAM1_CAMDBG0_RESET 0000000000
DMA12_DEBUG_WIDTH 29
EMMC_IRPT_EN_TUNE_ERR_BITS 26:26
GROPCTRC 0x1A005100 + 0x070:RW
HD_MAI_THR_PANICHIGH_BITS 29:24
TXP_CTRL_LINEAR_UTILE_CLR 0xffffff7f
SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_BITS 1:0
PM_PADS4_SPARE_MSB 4
HDMI_CEC_RX_DATA_3_MASK 0xffffffff
V3D_PCTRS3_WIDTH 5
IC0_VADDR_MASK 0xfffffe00
SD_PHYC_PHYRST_RESET 0x0
DMA8_DEST_AD_MASK 0xffffffff
I2C_SPI_SLV_RIS_OERIS_SET 0x00000008
A2W_PLLH_ANA_STAT_RCALCODE_MSB 19
TXP_CTRL_BWE_RESET 0xf
USB_GRSTCTL_RXF_FLSH_BITS 4:4
USB_GOTGCTL_DEV_HNP_EN_SET 0x00000800
SH_HBCT_BYTECOUNT_CLR 0x00000000
USB_BASE 0x7e980000
V3D_PCTRS6_MASK 0x0000001f
HDMI_DETECTED_VERTA0_MANUAL_VSP0_CLR 0xfe0fffff
GP_FSEL0_FSEL00_CLR 0xfffffff8
GP_FSEL4_FSEL48_CLR 0xf8ffffff
A2W_PLLB_ANA_KAIPR_MASK 0x0000077f
SMI_DSW0_WDREQ_BITS 7:7
EMMC_CMDTM_CMD_RSPNS_TYPE_LSB 16
USB_GUSBCFG_ULPI_IF_PROT_DIS_CLR 0xfdffffff
DMA0_TXFR_LEN_MASK 0x3fffffff
SD_SECSRT3_EN_SET 0x00000001
USB_GINTMSK_EP_MIS_SET 0x00020000
A2W_PLLB_ARM_CHENB_LSB 8
DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
DMA2_DEST_AD_D_ADDR_CLR 0x00000000
SD_DQLCRC3_RISE_BITS 31:16
SMI_DSR0_RSETUP_MSB 29
USB_DIEPTSIZ0_PKT_CNT_BITS 28:19
A2W_PLLA_PER_BYPEN_CLR 0xfffffdff
PIXELVALVE1_INTEN_MASK 0x000003ff
SH_HBCT_MASK 0xffffffff
EMMC_INTERRUPT_RETUNE_SET 0x00001000
DMA12_CONBLK_AD_SCB_ADDR_LSB 5
CM_TECCTL_KILL_LSB 5
PM_RSTS_HADSRF_LSB 9
UART_LSR_RFE_LSB 7
A2W_PLLC_ANA_SCTL_UPDATE_CLR 0xfffffff7
DMA8_CS_INT_BITS 2:2
HDMI_CP_INTEGRITY 0x7e90204c:RW
CM_PCMCTL_ENAB_MSB 4
SCALER_DISPSTAT_DMA_ERR_BIT1_SET 0xffff8000
SYSAC_UC_ARBITER_CONTROL_DELAY_LSB 2
A2W_SMPS_C_CTL_CTRLEN_SET 0x00000001
DMA1_DEBUG_LITE_SET 0x10000000
APERF1_BW0_CTRL_ID_RESET 0x0
DMA5_STRIDE_MASK 0xffffffff
L2_CONT_OFF_l2_standby_SET 0x00000c00
DMA6_CS_RESET_BITS 31:31
PCM_CS_A_EN_CLR 0xfffffffe
SD_CS_IDLE_BITS 9:9
SCALER_DISP_LIST_0 0x7e400000 + 0x20:RW
SCALER_DISP_LIST_1 0x7e400000 + 0x24:RW
SCALER_DISP_LIST_2 0x7e400000 + 0x28:RW
OTP_BASE_ADDRESS 0x7e20f000
APERF0_BW2_WTRANS_MASK 0xffffffff
HDMI_RAM_PACKET_2_2_RESET 0000000000
SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_MSB 3
ASB_V3D_S_CTRL_CLR_ACK_LSB 1
PM_GNRIC_POWUP_LSB 0
EMMC_STATUS_DAT_LEVEL1_BITS 28:25
MPHI_HSINDCF_WIDTH 32
CAM0_CAMIDCD_MASK 0xffffffff
CCP2TX_TBA_MASK 0x3fffffff
PWM_STA_GAPO1_BITS 4:4
A2W_PLLB_ANA_STAT_DATA_LSB 0
CM_PLLC_LOADPER_SET 0x00000040
DMA5_CS_ABORT_BITS 30:30
HDMI_RAM_PACKET_8_7_MASK 0xffffffff
CM_OSCCOUNT_NUM_MSB 23
SMI_DSW0_WPACEALL_CLR 0xffff7fff
PWM_CTL_MSEN1_LSB 7
DMA3_TXFR_LEN_YLENGTH_LSB 16
SD_DQLCRC13_FALL_RESET 0x0
CM_ARMCTL_KILL_CLR 0xffffffdf
DMA15_TI_SRC_DREQ_BITS 10:10
IC1_MASK4_WIDTH 31
DMA11_TI_DEST_IGNORE_SET 0x00000080
HDMI_CEC_RX_DATA_3_RESET 0000000000
USB_GINTMSK_DISCONN_INT_SET 0x20000000
USB_HPRT_SPD_RESET 0x0
CM_DPICTL_BUSY_CLR 0xffffff7f
DSI1_PR_TO_CNT_MASK 0xffffffff
AVE_IN_CURRENT_LINE_BUF1_MASK 0x80000fff
DSI0_CTRL_CTRL1_LSB 1
SYSAC_L2_ARBITER_CONTROL_ALGORITHM_RESET 0x0
I2C_SPI_SLV_MIS_BEMIS_CLR 0xfffffffb
CM_TD1CTL_STEP_MSB 12
DMA8_CS_ABORT_MSB 30
HDMI_DVO_TIMING_ADJUST_A_WIDTH 20
A2W_SMPS_A_GAINR_MASK 0x00000007
A2W_PLLB_ANA0_MASK 0x00ffffff
DMA0_CS_DISDEBUG_MSB 29
L1_D_FLUSH_E_RESET 0x3fffffff
CM_AVEODIV_DIV_LSB 12
I2C_SPI_SLV_DR_TXDMABREQ_MSB 11
GROPCTR_FBC_CZ_FE_LINE_REQS 0x2A
USB_DIEPTXF1_FIFO_STADDR_BITS 15:0
CM_ARMCTL_SRC_BITS 3:0
MPHI_C0INDS_VALID_LSB 30
USB_GINTMSK_OTG_INT_MSB 2
I2C0_DIV_MASK 0x0000ffff
IDCKEYHU 0x10002008:RW
EMMC_IRPT_MASK_DMA_CLR 0xfffffff7
GP_FSEL4_FSEL46_MSB 20
HDMI_VERTB1_RESET 0x00000021
A2W_PLLH_AUXR 0x7e102b60:RW
CAM1_CAMDBG3_MASK 0xffffffff
USB_PCGCR_PWR_CLMP_CLR 0xfffffffb
TXP_CTRL_ABORT_LSB 14
GP_FSEL6_FSEL67_CLR 0xff1fffff
DMA9_DEBUG_VERSION_CLR 0xf1ffffff
AVE_OUT_STATUS_HBACK_PORCH_CLR 0xffffffdf
ISP_RC_WIDTH 32
SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_LSB 0
DMA13_CS_DREQ_STOPS_DMA_BITS 5:5
HDMI_CEC_TX_DATA_1_WIDTH 32
TS_TSENSSTAT_VALID_LSB 10
CM_DSI0HSCK_SELPLLD_BITS 0:0
I2C_SPI_SLV_RIS_OERIS_CLR 0xfffffff7
OTP_APB_ID 0x206f7470
AUX_MU_IIR_NOIRQS 0x01
SD_PHYC 0x7ee00060:RW
USB_DOEPCTL0_MPS_CLR 0xfffff800
SD_SECEND1_ADDR_MS_CLR 0x00001fff
MS_SEMA_9_RESET 0000000000
GRSACT 0x1A005800 + 0x20:RW
I2C_SPI_SLV_DEBUG1_DATA_LSB 0
HDMI_RAM_PACKET_3_0_MASK 0xffffffff
AVE_IN_CTRL_BYTE_ORDER_BITS 13:11
USB_GRSTCTL_C_SFT_RST_BITS 0:0
SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_BITS 15:8
A2W_PLLD_CTRL_PWRDN_CLR 0xfffeffff
FPGA_APB_ID 0x66706761
USB_DOEPINT0_BACK2BACK_SETUP_SET 0x00000040
DMA0_CS_RESET_SET 0x80000000
DMA12_DEBUG_READ_ERROR_LSB 2
MS_SEMA_15_MASK_BITS 0:0
CM_PCMCTL_MASH_MSB 10
EMMC_CONTROL1_SRST_CMD_LSB 25
A2W_XOSC_CTRL_PLLCEN_MSB 0
V3D_PCTR2_MASK 0xffffffff
DMA10_CS_PAUSED_SET 0x00000010
CM_DFTCTL_BUSYD_CLR 0xfffffeff
APERF0_BW0_RMAX 0x7e009864:RO
ARM_0_MY_IRQS (0x7E00B000 +0x800)+0xFC:RW
ASB_ISP_M_CTRL_CLR_REQ_MSB 0
GROPCTR_FBC_EZ_LINE_FLUSHES 0x33
EMMC_FORCE_IRPT_DTO_ERR_SET 0x00100000
SMI_DSW1_WPACE_MSB 14
MPHI_AXIPRIV_HSPECEN_RESET 0x0
ASB_CPR_CTRL_WCOUNT_SET 0x00ffc000
USB_DOEPDMAB5_MASK 0xffffffff
USB_GINTMSK_OEP_INT_CLR 0xfff7ffff
GP_FSEL4_FSEL41_BITS 5:3
EMMC_CONTROL2_ACEND_ERR_BITS 3:3
GR_PSE_DEBUG_BASE 0x1A005900
I2C_SPI_SLV_RSR_WIDTH 6
DMA14_CS_DREQ_BITS 3:3
A2W_PLLA_CTRL_PDIV_BITS 14:12
AVE_IN_CTRL_LINE_IRQ_EN_LSB 4
CM_DFTCTL_BUSY_MSB 7
GP_FSEL5_FSEL56_SET 0x001c0000
FPGA_CTRL0_CAM_CTL2_SET 0x00000004
HDMI_RAM_PACKET_12_8_WIDTH 32
SYSAC_USB_PRIORITY 0x7e009020:RW
DMA8_TI_SRC_WIDTH_CLR 0xfffffdff
DMA4_DEBUG_OUTSTANDING_WRITES_MSB 7
A2W_PLLB_ARM_DIV_LSB 0
VEC_WSE_CONTROL_MASK 0xffffffff
L1_IC1_RD_MISSES_MASK 0000000000
EMMC_INTERRUPT_DATA_DONE_MSB 1
DMA1_TI_WAITS_BITS 25:21
USB_GUSBCFG_IND_PASS_THRU_RESET 0x0
DMA5_CS_DREQ_CLR 0xfffffff7
SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_SET 0x0000000c
HDMI_RAM_PACKET_13_0 0x7e9025d4:RW
A2W_SMPS_CTLB2_MASK 0x00ffffff
CM_TDCLKEN_PLLDBYP_CLR 0xfffffff7
DMA8_CS_END_SET 0x00000002
A2W_PLLB_SP2_MASK 0x000003ff
EMMC_STATUS_NEW_READ_DATA_BITS 11:11
I2C_SPI_SLV_CR_BRK_LSB 7
USB_GAHBCFG_NP_TXF_EMP_LVL_SET 0x00000080
SMI_DSW3_WDREQ_LSB 7
SMI_CS_WRITE_LSB 5
USB_HCTSIZ4_WIDTH 32
PWM_STA_STA3_LSB 11
DMA13_TI_BURST_LENGTH_MSB 15
PCMMODE_FTXP (1 << 24)
SD_DQRCRC12_FALL_MSB 15
AVE_IN_STATUS_MAX_HIT_LSB 16
USB_GOTGCTL_A_SES_VLD_LSB 18
HD_FRAME_CNT_MASK 0xffffffff
SYSAC_JPEG_PRIORITY_N_PRIORITY_MSB 3
HDMI_RAM_PACKET_13_2 0x7e9025dc:RW
PRM_CV_WIDTH 32
SMI_CS_RXR_CLR 0xf7ffffff
I2C_SPI_SLV_IMSC_BEIM_CLR 0xfffffffb
GRFCMSK 0x1A005400 + 0x2C:RW
DSI_RX1_PKTH 0x7e209000 + 0x0C:RW
A2W_PLLC_CORE1_BYPEN_SET 0x00000200
SD_SD_T_RPpb_SET 0x000000f0
SCALER_DISPSTAT_DMA_IRQ_CLR 0x0000000f
APERF1_BW2_RPEND_WIDTH 8
CM_BURSTCNT_CNT_LSB 0
A2W_PLLC_FRACR_MASK 0x000fffff
CAM0_CAMDBEA1_WIDTH 32
HDMI_READ_POINTERS_DRFT_RD_ADDR_LSB 7
USB_GHWCFG3_MODE_BITS 7:7
I2C_SPI_SLV_DEBUG1 0x7e214038:RW
I2C_SPI_SLV_DEBUG2 0x7e21403c:RW
EMMC_IRPT_MASK_CARD_IN_BITS 6:6
I2C_SPI_SLV_DR_DATA_SET 0x000000ff
CM_SDCCTL_WIDTH 18
USB_HFIR_MASK 0x0000ffff
MPHI_CTRL_HATVAL_RESET 0x0
USB_DIEPTSIZ0_PKT_CNT_MSB 28
DMA2_TI_SRC_INC_LSB 8
HD_SPARE_RESET 0000000000
EMMC_CMDTM_CMD_TYPE_CLR 0xff3fffff
TXP_CTRL_EI_LSB 2
IDCKEYLU 0x1000200C:RW
PM_DSI1_MASK 0x001fffff
SMI_CS_INTR_CLR 0xfffff7ff
MS_SEMA_23_MASK_MSB 0
DMA_INT_STATUS_INT9_MSB 9
CM_PWMDIV_WIDTH 24
DMA5_CONBLK_AD_SCB_ADDR_MSB 31
SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_RESET 0x0
PM_PADS5_I2CMODE_SET 0x00000040
DMA10_TI_MASK 0x03fffff9
A2W_PLLB_ANA_KAIP_KA_MSB 10
A2W_PLLH_DIG2_RESET 0x000000aa
UMCR 0x7e201000 + 0x10:RW
SLIM_DMA_DC6_WIDTH 32
PCM_DREQ_A_RX_PANIC_LSB 16
DMA15_TI_DEST_INC_MSB 4
CM_HSMCTL_BUSYD_CLR 0xfffffeff
CAM0_CAMCAP1_WIDTH 32
DMA8_DEBUG_FIFO_ERROR_MSB 1
HD_VID_CTL_ENABLE_BITS 31:31
L1_D1_WR_THRUS 0x7ee0219c:RO
DMA13_TI_SRC_INC_CLR 0xfffffeff
GP_FSEL4_FSEL42_LSB 6
A2W_PLLD_CTRL_NDIV_LSB 0
AM_VP_UC_PRI 0x1800d004:RW
A2W_PLLA_ANA_SCTLR_WIDTH 5
EMMC_CONTROL0_HCTL_CRDDET_LSB 6
DMA1_TI_DEST_IGNORE_BITS 7:7
HDMI_RAM_PACKET_13_8 0x7e9025f4:RW
APERF0_BW0_WTWAIT_RESET 0000000000
I2C1_DEL_RESET 0x00300030
ASB_ISP_S_CTRL_WCOUNT_SET 0x00ffc000
CM_V3DCTL_SRC_SET 0x0000000f
DMA3_NEXTCONBK_ADDR_SET 0xffffffe0
GP_FSEL3_FSEL30_BITS 2:0
APERF0_BW2_CTRL_ID_SET 0x00001f00
HDMI_ASYNC_RM_SAMPLE_INC (HDMI_BASE_ADDRESS + 0x300) + 8:RW
CM_EVENT_LOSSD_SET 0x00000100
HDMI_BCH_CONFIGURATION_RESET 0x00000083
MS_SEMA_13_MASK_LSB 0
AUX_SPI0_PEEK_REG (0x7E215000 +0x08C)
USB_GINTMSK_SESS_REQ_INT_MSB 30
CMI_CAM0_RX0SRC_SET 0x0000000c
PM_RSTS_HADWRH_LSB 6
DMA6_DEBUG 0x7e007620:RW
SMI_DSR0_MODE68_LSB 23
HD_CSC_32_31_WIDTH 32
A2W_SMPS_L_SIV_VOLTS_CLR 0xffffffe0
USB_HPRT_SPD_CLR 0xfff9ffff
EMMC_FORCE_IRPT_OEM_ERR_MSB 31
EMMC_RESP3_WIDTH 32
GP_FSEL2_FSEL22_BITS 8:6
PM_PROC_ISFUNC_CLR 0xffffffdf
CM_V3DCTL_BUSY_CLR 0xffffff7f
A2W_PLLB_ANA_KAIP 0x7e1023f0:RW
GP_AJBCONF_WIDTH 32
CCP2TX_TIC_TQIE_SET 0x00000004
USB_HPRT_LN_STS_LSB 10
DMA0_TI_WAITS_CLR 0xfc1fffff
SH_HSTS_DATA_FLAG_MSB 0
APERF1_BW0_CTRL_ID_EN_SET 0x20000000
USB_GRSTCTL_RXF_FLSH_SET 0x00000010
GP_FSEL1_FSEL14_BITS 14:12
PIXELVALVE2_C 0x7e807000:RW
DMA_ENABLE_EN8_LSB 8
SD_DQLCRC10_FALL_RESET 0x0
MS_SEMA_2_MASK_CLR 0xfffffffe
SD_TMC_TS_MSB 1
TXP_CTRL_TFORMAT_BITS 5:5
DMA0_NEXTCONBK_MASK 0xffffffe0
UART_MSR_DSR_SET 0x00000020
DMA_INT_STATUS_INT13_SET 0x00002000
ASB_ISP_S_CTRL_FULL_MSB 3
SD_CS_SREF2RUN_CLR 0xfffffeff
CM_AVEOCTL_MASK 0x000003bf
DMA0_TI_WAIT_RESP_CLR 0xfffffff7
GP_FSEL0_FSEL06_BITS 20:18
USB_DIEPCTL0_SNP_RESET 0x0
DMA0_TI_SRC_DREQ_MSB 10
TB_JTB_CONFIG_SBITS_SET 0x0000001f
DMA10_TI_INTEN_SET 0x00000001
USB_DOEPCTL5_WIDTH 32
SMI_DSR2_FSETUP_LSB 22
EMMC_INTERRUPT_READ_RDY_MSB 5
EMMC_IRPT_MASK_READ_RDY_SET 0x00000020
CM_INTEN_OCDONE_CLR 0xffdfffff
IC0_S_WIDTH 27
GP_LEN2_RESET 0000000000
HDMI_CORE_REV_RESET 0x00000600
HDMI_AN1_WIDTH 32
CM_EMMCCTL_BUSYD_SET 0x00000100
MS_IREQ_0_IREQ_0_BITS 31:0
CM_PLLA_DIGRST_BITS 9:9
CCP2TX_TTC_LEC_LSB 8
A2W_PLLD_CTRL 0x7e102140:RW
SMI_FD_FLVL_RESET 0x0
SH_HCFG_BUSY_IRPT_EN_LSB 10
DMA15_TXFR_LEN_XLENGTH_CLR 0xffff0000
PIXELVALVE0_STAT_WIDTH 10
SD_CS_RDH_IDLE_RESET 0x0
USB_GHWCFG4_NUM_PERIO_EPS_MSB 3
TB_BOOT_OPT_TB_PRESENT_CLR 0x7fffffff
I2CS_RXD (1 << 5)
PM_PADS5_RESET 0x0000001b
PM_RSTS_RESET 0x00001000
PM_RSTC_WRCFG_LSB 4
DMA7_TI_DEST_DREQ_LSB 6
MPHI_C1INDDA_START_BITS 31:0
DMA6_CS_DISDEBUG_LSB 29
I2CS_RXR (1 << 3)
USB_DCFG_DESC_DMA_BITS 23:23
AVE_IN_STATUS_BUF1_COMPL_BITS 2:2
MPHI_HSINDS_VALID_BITS 30:30
EMMC_FORCE_IRPT_CBAD_ERR_MSB 19
SMI_CS_AFERR_MSB 25
CM_PULSECTL_BUSYD_MSB 8
SD_SB_STBY_T_SET 0xfff00000
AVE_OUT_Y_COEFF_RESET 0x0994b43a
DMA8_TI_SRC_IGNORE_LSB 11
MPHI_OUTDDB_TENDINT_BITS 29:29
A2W_PLLH_ANA_STAT_CNTLENB_BITS 20:20
PM_RSTS_HADWRH_BITS 6:6
SPI_CS_CSPOL_LSB 6
USB_GOTGCTL_SES_REQ_CLR 0xfffffffd
SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_SET 0x00000007
DMA6_TI_SRC_INC_CLR 0xfffffeff
AVE_IN_OVERRUN_ADDRESS_RESET 0000000000
DC_HUFFTABLE_OFFSET(t) MACRO
HD_CSC_14_13_MASK 0xffffffff
MPHI_OUTDDB_LENGTH_MSB 19
USB_DIEPINT7_WIDTH 32
A2W_PLLA_ANA2R_WIDTH 24
APERF1_BW0_CTRL_RESET_CLR 0x7fffffff
ASB_V3D_S_CTRL_RCOUNT_BITS 13:4
PCM_CS_A_RXSEX_LSB 23
PCM_INTEN_A_RXR_SET 0x00000002
A2W_SMPS_A_MODE 0x7e1021a0:RW
DMA8_TI_SRC_DREQ_MSB 10
A2W_PLLA_DIG0 0x7e102000:RW
A2W_PLLA_DIG1 0x7e102004:RW
A2W_PLLA_DIG2 0x7e102008:RW
A2W_PLLA_DIG3 0x7e10200c:RW
GPEDS0 0x7e200000 + 0x40:RW
CM_PLLD_LOADPER_BITS 6:6
GPEDS2 0x7e200000 + 0x48:RW
A2W_PLLB_CTRL_NDIV_CLR 0xfffffc00
DMA5_CS_WIDTH 32
CM_EVENT_A2WDONE_LSB 20
SD_DQLCRC4_FALL_LSB 0
AUX_SPI1_STAT_REG (0x7E215000 +0x0C8)
SD_DQRCRC1_MASK 0xffffffff
USB_GPVNDCTL_STS_DONE_BITS 27:27
CM_TD1CTL_MASK 0x00001bff
USB_DOEPDMA13_WIDTH 32
MS_SEMA_16_RESET 0000000000
TB_BOOT_ADDR_MASK 0xffffffff
USB_DIEPEMPMSK_EP_TXF_EMP_MSK_BITS 15:0
A2W_PLLA_DSI0_DIV_SET 0x000000ff
USB_HCTSIZ0_XFER_SIZE_RESET 0x0
USB_HCSPLT4_WIDTH 32
USB_DOEPINT0_TX_FIFO_UNDRN_CLR 0xfffffeff
SH_CDIV_MASK 0x000007ff
DMA1_CS_ERROR_MSB 8
CM_INTEN_LOSSD_BITS 8:8
SCALER_DISPBKGND2_WIDTH 32
CM_SLIMCTL_BUSY_CLR 0xffffff7f
USB_GRSTCTL_DMA_REQ_CLR 0xbfffffff
UART_LSR_THRE_CLR 0xffffffdf
DMA11_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
PWM_CTL_SBIT2_LSB 11
AVE_OUT_CB_COEFF_GREEN_COEFF_SET 0x000ffc00
PM_GRAFX_ENAB_BITS 12:12
I2C_SPI_SLV_FR_TXBUSY_LSB 0
PCM_RXC_A_CH2POS_LSB 4
PIARBCTL_CAM_CHANNEL_INIBIT_RESET 0x0
MS_SEMA_3_MASK 0x00000001
PM_SMPS_RSTDR_CLR 0xfffffffd
CM_PCMCTL_BUSYD_LSB 8
EMMC_HWCAP0_AINT_MSB 29
DMA5_CS_END_SET 0x00000002
TH0_BASE 0x18011000
PWM_STA 0x7e20c004:RW
APERF0_BW1_CTRL_ID_EN_LSB 29
A2W_SMPS_L_SCA_ANA_LSB 0
USB_HCINTMSK0_MASK 0xffffffff
CGMSAE_TOP_FORMAT 0x7e80604c:RW
PCM_INTSTC_A_WIDTH 4
DMA15_TI_SRC_INC_MSB 8
USB_DOEPCTL12_WIDTH 32
MS_SEMA_12_MASK 0x00000001
USB_DIEPCTL0_DIS_BITS 30:30
DMA9_CS_PRIORITY_MSB 19
CM_INTEN_FLOSSC_LSB 16
OTP_VPU_CACHE_KEY_PARITY_START_BIT 8
A2W_PLLC_ANA_SSCLR_MASK 0x0001ffff
PM_PADS3_DRIVE_MSB 2
USB_GINTMSK_MASK 0xf77effff
MPHI_C0INDCF_MTERM_BITS 28:28
DMA13_CS_WIDTH 32
GP_FSEL1_FSEL15_CLR 0xfffc7fff
ARM_AIS1_HAVESPAC 0x00000100
CM_PCMCTL_KILL_LSB 5
USB_DCTL_SFT_DISCON_MSB 1
PWM_CTL_USEF3_BITS 21:21
SD_PHYC_VREF_ENB_MSB 4
SD_DQRCRC5_MASK 0xffffffff
A2W_PLLA_DSI0_BYPEN_SET 0x00000200
USB_GI2CCTL_EN_SET 0x00800000
SMI_DSW3_WPACEALL_LSB 15
SMICS_PXLDAT 14
PCM_DREQ_A_TX_CLR 0xffff80ff
HDMI_FIFO_CTL_FIFO_RESET_MSB 5
A2W_PLLD_ANA_STAT_DATA_MSB 11
VEC_BASE 0x7e806000
DMA0_TI_SRC_IGNORE_SET 0x00000800
USB_DOEPDMAB12 0x7e980b1c:RW
USB_DOEPDMAB13 0x7e980b1c:RW
USB_DIEPINT0_BACK2BACK_SETUP_SET 0x00000040
USB_DOEPDMAB15 0x7e980b1c:RW
EMMC_STATUS_CARD_INSERT_CLR 0xfffeffff
UNICAM_CMP0(x) MACRO
UNICAM_CMP1(x) MACRO
USB_GHWCFG2_EN_PERIO_HOST_LSB 18
MS_VPUSEMA_1_VPUSEMA_1_BITS 0:0
EMMC_HWCAP1_WIDTH 26
HDMI_DETECTED_VERTB1_MANUAL_VBP1_CLR 0xfffffeff
ARM_C0_APROTPASS 0x0000A000
HDMI_DETECTED_VERTB0_WIDTH 22
SD_DQRCRC6_FALL_LSB 0
SLIM_DCC7_STAT_WIDTH 32
OTP_DATA_REG 0x7e20f018:RW
HD_MAI_CTL_WHOLSMP_BITS 12:12
SMICS 0x7e600000 + 0x00:RW
USB_HCCHAR0_EP_NUM_MSB 14
CM_H264CTL_MASK 0x000003ff
EMMC_STATUS_MASK 0x1fff0f0f
HDMI_CTS_1_WIDTH 20
PM_PADS2_DRIVE_LSB 0
DMA15_TI_DEST_IGNORE_LSB 7
SCALER_DISPECTRL_CB_NE_CTRL_SET 0xe0000000
DMA14_CS_DREQ_MSB 3
MPHI_RXAXICFG_INTHRESH_CLR 0xfffe00ff
CM_UARTCTL_SRC_CLR 0xfffffff0
A2W_PLLH_ANA_KAIP_KA_LSB 8
V3D_L2CACTL 0x7ec00000 +0x0020:RW
PIARBCTL_CAM_DELAY_LSB 2
CM_CAM0CTL_FRAC_BITS 9:9
USB_DIEPTXF3_MASK 0xffffffff
CM_INTEN_GAINB_CLR 0xfffffffd
USB_GRSTCTL_FRM_CNTR_RST_CLR 0xfffffffb
PM_SPARER_SPARE_SET 0x00ffffff
DMA11_TXFR_LEN_XLENGTH_MSB 15
CM_DSI0EDIV_WIDTH 16
DMA1_CS_DISDEBUG_MSB 29
SMIDA 0x7e600000 + 0x38:RW
SMIDC 0x7e600000 + 0x30:RW
PCM_INTSTC_A_TXW_MSB 0
DMA10_TI_WAIT_RESP_CLR 0xfffffff7
ASB_H264_M_CTRL_FULL_CLR 0xfffffff7
USB_GINTMSK_P_TXF_EMP_CLR 0xfbffffff
INTERRUPT_TRANSPOSER ((64) + 11 )
A2W_PLLB_ANA1 0x7e1020f4:RW
DMA13_NEXTCONBK_ADDR_LSB 5
HDMI_RAM_PACKET_STATUS_WIDTH 14
A2W_PLLH_DIG0_WIDTH 24
GP_FSEL0_FSEL04_SET 0x00007000
PM_IMAGE_ISPOW_MSB 2
MPHI_C0INDS_VALID_BITS 30:30
SD_MR_TIMEOUT_MSB 30
A2W_PLLA_ANA0R 0x7e102810:RW
SLIM_DMA_DC_STAT_0_MASK 0xffffffff
DMA5_DEBUG_READ_ERROR_SET 0x00000004
IC0_FORCE1_CLR_WIDTH 32
GP_FEN2_FENn64_CLR 0xffffffc0
DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
A2W_XOSC_BIAS_BIAS_SET 0x0000000f
DMA11_DEST_AD_D_ADDR_LSB 0
HDMI_PERT_INSERT_ERR_SEP_MASK 0xffffffff
EMMC_IRPT_EN_CBAD_ERR_MSB 19
A2W_PLLB_ANA_STAT 0x7e1024f0:RW
MPHI_INTSTAT_RX1DISC_BITS 24:24
SD_DMRCRC0_MASK 0xffffffff
PM_GNRIC_POWOK_MSB 1
HDMI_RAM_GCP_4_RESET 0000000000
USB_DCTL_CGOUT_NAK_RESET 0x0
DMA0_DEBUG_DMA_ID_SET 0x0000ff00
DMA6_TI_TDMODE_SET 0x00000002
SLIM_DMA_MC_CON_MASK 0x00000003
MS_SEMA_9_MASK_CLR 0xfffffffe
USB_HCSPLT5 0x7e9805a4:RW
CM_CCP2CTL_FRAC_BITS 9:9
EMMC_HWCAP1_DRV18_TYPED_SET 0x00000040
DMA8_TI_SRC_INC_MSB 8
CM_GP0DIV_RESET 0000000000
A2W_PLLA_ANA1R 0x7e102814:RW
A2W_XOSC_CTRL_USBOK_SET 0x00004000
DMA_ENABLE_EN2_SET 0x00000004
EMMC_INTERRUPT_ERR_SET 0x00008000
DMA7_NEXTCONBK_ADDR_CLR 0x0000001f
DMA8_CS_DREQ_BITS 3:3
HDMI_RAM_PACKET_12_2_RESET 0000000000
GP_AFEN1_AFENn32_MSB 31
SPI_CS_TA_SET 0x00000080
A2W_SMPS_L_SPV_VOLTS_MSB 4
JMADDR 0x7e005000 + 0x30:RW
A2W_XOSC_PWR_BYPASS_MSB 0
SCALER_DISPSTAT_DMA_ERR_BIT2_LSB 7
DMA11_TXFR_LEN_XLENGTH_BITS 15:0
HD_HDM_CTL_CECOVR_LSB 8
DMA14_CS_DREQ_STOPS_DMA_BITS 5:5
SD_DQLCRC1_FALL_SET 0x0000ffff
DSI0_PHYC_txulpshs_0_sync_MSB 1
DSI1_PHY_AFEC0_MASK 0xffffffff
HDMI_DETECTED_VERTB0_MANUAL_VBP0_SET 0x00000100
TXP_CTRL_BWE_SET 0x000f0000
CM_GP0CTL_ENAB_CLR 0xffffffef
SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_MSB 5
USB_DIEPINT0 0x7e980908:RW
USB_DIEPINT1 0x7e980928:RW
USB_DIEPINT2 0x7e980948:RW
USB_DIEPINT3 0x7e980968:RW
SPI_LTOH_TOH_LSB 0
USB_DIEPINT5 0x7e9809a8:RW
CM_H264CTL_FRAC_BITS 9:9
USB_DIEPINT7 0x7e9809e8:RW
USB_DIEPINT8 0x7e980a08:RW
A2W_PLLA_ANA2R 0x7e102818:RW
APERF1_BW1_ATWAIT_RESET 0000000000
DSI0_PHYC_unused_SET 0x00000010
A2W_SMPS_C_CTLR 0x7e102ac0:RW
EMMC_INTERRUPT_DTO_ERR_MSB 20
A2W_PLLA_CCP2R_MASK 0x000003ff
SLIM_DCC9_PROT_WIDTH 32
GROPCTR_FBC_CZ_FE_QUAD_REQS 0x29
GP_FSEL5_FSEL59_MSB 29
I2C_SPI_SLV_MIS_BEMIS_LSB 2
DMA8_DEBUG_OUTSTANDING_WRITES_MSB 7
USB_HPRT_LN_STS_SET 0x00000c00
USB_DFIFO3_WIDTH 32
CAM0_CAMIVWIN 0x7e800128:RW
CM_TD0CTL_STEP_CLR 0xffffefff
HD_MAI_CTL_FULL_RESET 0x0
A2W_PLLA_ANA_STATR_WIDTH 12
TH1T0PC 0x1A008000 + 0x10:RW
EMMC_CONTROL2_DRVTYPE_CLR 0xffcfffff
A2W_PLLH_ANA_STAT_DATA_CLR 0xfffff000
CM_OSCFREQI_MASK 0x000000ff
SD_DMRCRC0_LOW_CLR 0xffff0000
EMMC_IRPT_MASK_DEND_ERR_BITS 22:22
FPGA_CTRL0_DIS_CTL0_CLR 0xfffffffe
PM_PADS3_WIDTH 6
GP_EDS0_EDSn0_SET 0xffffffff
SD_STALL_MASK 0x000003ff
DMA2_STRIDE_D_STRIDE_CLR 0x0000ffff
A2W_PLLA_ANA3R 0x7e10281c:RW
DSI0_CTRL_CTRL2_BITS 2:2
GP_AREN0_MASK 0xffffffff
V3D_PCTRS0 0x7ec00684:RW
V3D_PCTRS1 0x7ec0068c:RW
V3D_PCTRS2 0x7ec00694:RW
V3D_PCTRS3 0x7ec0069c:RW
V3D_PCTRS4 0x7ec006a4:RW
L1_IC1_FLUSH_E_MASK 0xffffffe0
V3D_PCTRS6 0x7ec006b4:RW
V3D_PCTRS7 0x7ec006bc:RW
V3D_PCTRS8 0x7ec006c4:RW
V3D_PCTRS9 0x7ec006cc:RW
DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
CAM1_CAMIPIPE_RESET 0000000000
PM_GRAFX_POWUP_LSB 0
A2W_SMPS_A_MULTI 0x7e102fa0:RW
HDMI_READ_POINTERS_DRFT_OVERFLOW_MSB 19
SMI_DSW1_WDREQ_BITS 7:7
USB_DOEPINT0_IN_TKN_TXFEMP_RESET 0x0
PM_DSI0 0x7e100050:RW
PM_DSI1 0x7e100054:RW
MS_MBOX_4_MBOX_MSB 31
MPHI_HSINDCF_MTERM_SET 0x10000000
PM_AVS_EVENT_ALERT_PERI_A_MSB 0
A2W_PLLH_AUX_CHENB_SET 0x00000100
HDMI_READ_POINTERS_DRFT_ALMOST_FULL_BITS 21:21
USB_DTXFSTS5_MASK 0xffffffff
EMMC_HWCAP1_DRV18_TYPED_CLR 0xffffffbf
CM_PLLA_LOADCCP2_CLR 0xfffffffb
PM_PADS2_SLEW_MSB 4
DMA2_DEBUG_DMA_STATE_MSB 24
GP_FSEL2_FSEL25_BITS 17:15
SD_SA_CLKSTOP_CLR 0xffffff7f
A2W_PLLH_PIXR 0x7e102d60:RW
HD_MAI_SMP_RESET 0000000000
A2W_HDMI_CTL_RCAL_MANREN_CLR 0xffffefff
CM_SYSCTL_GATE_LSB 6
MPHI_OUTDDB_HANDLE_RESET 0x0
V3D_PCTRS14_MASK 0x0000001f
USB_DOEPCTL0_NEXT_EP_LSB 11
A2W_PLLB_ANA_SCTLR_WIDTH 5
A2W_PLLA_CCP2 0x7e102600:RW
DMA5_TI_INTEN_MSB 0
PM_AVS_STAT_ALERT_H264_I_CLR 0xfffffffb
PM_GRAFX_POWOK_SET 0x00000002
L1_IC0_CONTROL_RAS_DISABLE_BITS 4:4
DMA0_CONBLK_AD_SCB_ADDR_MSB 31
GP_SET2 0x7e200024:RW
A2W_PLLC_ANA_STATR_MASK 0x00000fff
A2W_PLLB_ANA_SSCL_LIMIT_MSB 21
L2_CONT_OFF 0x7ee01000:RW
SCALER_DISPLIST0_WIDTH 32
CM_PLLTCTL_SRC_CLR 0xfffffff8
HDMI_CPU_MASK_CLEAR_RESET 0x0001ffff
CM_EMMCCTL_FRAC_MSB 9
SD_DQLCRC12_RISE_BITS 31:16
SMI_DSW0_WSETUP_LSB 24
SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_SET 0x0000ff00
SD_TMC_WIDTH 32
L2_CONT_OFF_l2_flush_mode_LSB 3
CM_DSI0PCTL_SRC_SET 0x0000000f
USB_GHWCFG4_NUM_IN_EPS_BITS 27:26
USB_DIEPCTL0_DIS_LSB 30
A2W_XOSC_CTRL_USBEN_LSB 2
SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_BITS 7:6
CM_DFTDIV_DIV_SET 0x0001f000
I2C_SPI_SLV_CR_CPHA_MSB 3
GP_FSEL5_FSEL57_LSB 21
A2W_PLLB_DIG2_RESET 0x00100401
CM_PLLD_HOLDCORE_CLR 0xffffffdf
PM_PXLDO_RSTPLLDR_MSB 17
MS_ICSET_1_ICSET_1_CLR 0xfffffffe
USB_GI2CCTL_RW_DATA_MSB 7
AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_SET 0x00000fff
A2W_PLLC_CTRL_NDIV_MSB 9
SLIM_DCC4_STAT_WIDTH 32
CM_DFTCTL_KILL_MSB 5
DMA9_DEBUG_DMA_ID_BITS 15:8
DMA4_TI_INTEN_SET 0x00000001
I2C_SPI_SLV_RSR 0x7e214004:RW
SD_MR_HI_Z_LSB 29
A2W_PLLA_CTRL_PRSTN_CLR 0xfffdffff
USB_GRSTCTL_H_SFT_RST_CLR 0xfffffffd
PCM_TX_DMA ( 2*(1<<16))
DPHY_CSR_DESCRIPTION "SDRAM Data (pin) control"
APHY_CSR_ADDR_PAD_DRV_SLEW_CTRL 0x7ee06068:RW
L1_D1_RD_THRUS 0x7ee0218c:RO
HDMI_DETECTED_VERTB0_MANUAL_VSPO0_SET 0x003ffe00
DMA12_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
OTP_MIN_ROW 8
PCM_CS_A_TXCLR_MSB 3
SMIDCS_ENABLE 0
CM_TDCLKEN_PLLDDIV2_CLR 0xffffff7f
PCM_TXC_A_CH1WEX_CLR 0x7fffffff
HDMI_PERT_CONFIG_MASK 0x00000fff
VEC_WSE_CONTROL_WIDTH 32
I2C_SPI_SLV_DR_RXFLEVEL_LSB 27
DMA10_DEBUG_DMA_ID_SET 0x0000ff00
CM_TD0CTL_KILL_SET 0x00000020
CM_INTEN_GAINH_BITS 4:4
DMA14_CS_ACTIVE_LSB 0
A2W_SMPS_L_SCV_VOLTS_CLR 0xffffffe0
DMA13_TI_WAITS_MSB 25
USB_DCTL_SGNP_IN_NAK_SET 0x00000080
SH_CMD_LONG_RESPONSE_CLR 0xfffffdff
GP_FSEL3_FSEL34_SET 0x00007000
A2W_PLLB_ANA2R_MASK 0x00ffffff
APERF0_BW0_AMAX_MASK 0x00ffffff
CM_PWMCTL_ENAB_SET 0x00000010
AC_OSETTABLE_OFFSET(t) MACRO
SH_RSP0 0x7e202010:RO
SH_RSP1 0x7e202014:RO
SH_RSP2 0x7e202018:RO
SH_RSP3 0x7e20201c:RO
USB_HCINT0_AHB_ERR_CLR 0xfffffffb
PM_STATUS 0x7e100018:RO
L2_CONT_OFF_l2_flush_core_limit_MSB 23
SD_RWC_MARGIN_RESET 0x1
L1_L1_SANDBOX_START1_START_ADDR_LSB 5
DMA5_CONBLK_AD_SCB_ADDR_BITS 31:5
GP_FSEL6_FSEL65_BITS 17:15
A2W_PLLC_ANA_KAIP_MASK 0x0000077f
DMA2_TI_NO_WIDE_BURSTS_SET 0x04000000
GP_PUDCLK2_WIDTH 6
DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
USB_DOEPCTL0_NAK_STS_LSB 17
TH1T0UD 0x1A008000 + 0x14:RW
SYSAC_DMA_ARBITER_CONTROL_PER_MASK 0x0000ffff
DSI0_PR_TO_CNT 0x7e20903c:RW
DMA6_STRIDE_S_STRIDE_CLR 0xffff0000
CPG_Config_MASK 0xffffffff
SYSAC_L2_ARBITER_CONTROL_LIMIT_MSB 1
CM_BURSTCNT_CNT_BITS 23:0
EMMC_DMA_STATUS_ERR_AT_BITS 1:0
ARM_IF_ILLEGAL 0x00000046
DMA15_STRIDE_D_STRIDE_MSB 31
DMA10_TI_SRC_DREQ_CLR 0xfffffbff
APERF0_BW2_CTRL_EN_MSB 30
GP_FSEL4_FSEL49_BITS 29:27
PM_PADS6_PD_MSB 8
HDMI_RAM_GCP_0_MASK 0xffffffff
HDMI_HDCP_KEY_2_MASK 0xffffffff
DMA9_TI_SRC_DREQ_MSB 10
OTP_DESCRIPTION "One Time programmable"
DMA13_SOURCE_AD_WIDTH 32
SH_HCFG 0x7e202038:RW
V3D_PCTRE_WIDTH 32
SYSAC_DMA_ARBITER_CONTROL_PER 0x7e009058:RW
DMA12_DEBUG_DMA_ID_BITS 15:8
USB_GPVNDCTL_STS_DONE_LSB 27
GP_REN0_RENn0_CLR 0x00000000
PCM_CS_A_TXE_BITS 21:21
USB_DIEPTSIZ0_PKT_CNT_LSB 19
PWMCTL_CLRF1 6
DMA5_CS_ABORT_CLR 0xbfffffff
DSI0_TST_MON_WIDTH 8
CM_CAM0CTL_FRAC_CLR 0xfffffdff
SMI_CS_INTD_BITS 9:9
A2W_PLLH_DIG3R_WIDTH 24
SYSAC_DUMMY_STATUS_IDLE_LSB 0
GP_LEV1_WIDTH 32
SD_DQLCRC2_RISE_SET 0xffff0000
DMA5_STRIDE_S_STRIDE_LSB 0
DMA0_TI_SRC_INC_BITS 8:8
DMA5_DEST_AD_D_ADDR_CLR 0x00000000
A2W_PLLA_PER_DIV_LSB 0
DMA13_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_SET 0x00000fff
SLIM_DCC6_PROT_WIDTH 32
PM_RSTS_HADDRF_BITS 1:1
EMMC_INTERRUPT_ERR_BITS 15:15
ASB_ISP_S_CTRL_CLR_ACK_BITS 1:1
ADC_BASE_ADDRESS 0x1C00E000
DMA15_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
PM_GRAFX_MEMREP_BITS 3:3
DMA7_TI_INTEN_BITS 0:0
USB_GRXSTSP_DEV_FN_LSB 21
EMMC_BUS_CTRL_BE_PWR_BITS 30:24
HDMI_RAM_PACKET_12_0_WIDTH 32
AVE_OUT_CTRL_ERROR_IRQ_EN_MSB 0
I2C_SPI_SLV_FR_TXFLEVEL_CLR 0xffffffff111
DMA_ENABLE_EN11_CLR 0xfffff7ff
I2C_SPI_SLV_CR_INV_TXF_SET 0x00002000
CAM0_CAMIDCD_RESET 0000000000
DMA15_TI_WIDTH 27
SD_PHYC_MASK 0x01111111
CM_DFTCTL_ENAB_CLR 0xffffffef
SD_SB_ROWBITS_CLR 0xfffffff3
GP_SEN0_WIDTH 32
DMA4_DEBUG_DMA_ID_MSB 15
GP_CLR0_CLRn0_CLR 0x00000000
HD_MAI_CTL_CHALIGN_RESET 0x0
DMA_CS_DREQ (1<<3)
SD_SC_T_RRD_SET 0x00f00000
DMA11_CS_PRIORITY_CLR 0xfff0ffff
MS_ICCLR_1_RESET 0000000000
HDMI_FIFO_CTL_RECENTER_SET 0x00000040
GP_FSEL5_FSEL50_CLR 0xfffffff8
A2W_XOSC1_RESET 0x00000006
PCM_INTEN_A_TXW_SET 0x00000001
AVE_OUT_CTRL_MODE_MSB 5
CAM0_CAMIDI1_MASK 0xffffffff
PCMMODE_FSI (1 << 20)
MPHI_C1INDCF_MTERM_BITS 28:28
UART_MSR_DSR_BITS 5:5
DPHY_CSR_DQ_SPR_RO 0x7ee07074:RW
ARM_EH_ILLADDRS1 0x00000002
ARM_EH_ILLADDRS2 0x00000004
DSI_DISP1_CTRL 0x7e209000 + 0x1C:RW
DPHY_CSR_DQ_SPR_RW 0x7ee0706c:RW
CM_DPICTL_SRC_BITS 3:0
DMA15_TXFR_LEN_XLENGTH_BITS 15:0
A2W_HDMI_CTL0R_WIDTH 24
CM_EVENT_FLOSSC_MSB 16
I2CFIFO_1 0x7e804000 + 0x10:RW
L1_APB_ID 0x4c314343
I2CFIFO_3 I2C_BASE_3 + 0x10:RW
USB_GINTMSK_HCH_INT_RESET 0x0
DSI1_INT_STAT_MASK 0xffffffff
EMMC_IRPT_EN_ADMA_ERR_BITS 25:25
PM_AVS_STAT_ALERT_H264_I_SET 0x00000004
OTP_CODE_SIGNING_FLAG_SIZE_IN_ROWS 1
A2W_PLLC_DIG3_MASK 0x00ffffff
HD_CSC_CTL_PADMSB_MSB 4
HDMI_AN1_MASK 0xffffffff
APERF1_BW2_CTRL_EN_BITS 30:30
CM_TIMERCTL_ENAB_MSB 4
CM_CAM0DIV_RESET 0000000000
GP_FSEL0_FSEL09_MSB 29
L1_L1_SANDBOX_START5_START_ADDR_CLR 0xc000001f
DSI1_DISP0_CTRL 0x7e700028:RW
A2W_PLLC_CTRL_PRSTN_MSB 17
JP_C2S 0x7e005060:RW
DMA1_CS_DISDEBUG_BITS 29:29
DMA13_TI_MASK 0x03fffff9
SPI_CS_INTR_BITS 10:10
DMA15_CS_ERROR_LSB 8
SD_DQRCRC4_RISE_SET 0xffff0000
ARM_IRQ_DIBL1 0x7E00B000 +0x21C:RW
ARM_IRQ_DIBL2 0x7E00B000 +0x220:RW
ARM_IRQ_DIBL3 0x7E00B000 +0x224:RW
DMA14_SOURCE_AD_S_ADDR_BITS 31:0
DMA5_TI_DEST_WIDTH_LSB 5
USB_DOEPTSIZ8_WIDTH 32
I2CFIFO_x(x) MACRO
SMI_DSR1_RSETUP_MSB 29
DMA3_CS_PAUSED_MSB 4
A2W_SMPS_CTLC1R_WIDTH 24
CM_DFTCTL 0x7e101168:RW
PM_AVS_RSTDR_H264_I_BITS 2:2
A2W_PLLB_SP0R_WIDTH 10
SD_DQLCRC9_FALL_BITS 15:0
TE_1TIMER 0x7e20e014:RW
I2C_SPI_SLV_CR_RXE_MSB 9
GP_PUDCLK0 0x7e200098:RW
GP_PUDCLK1 0x7e20009c:RW
DSI1_TXPKT1_H_RESET 0000000000
L1_D1_RD_MISSES 0x7ee02188:RO
CM_DPICTL_KILL_SET 0x00000020
SD_SA_PGEHLDE_BITS 8:8
SD_SECSRT1_ADDR_LS_MSB 12
SCALER_DISPSTAT_DSP0_IRQ_SET 0xfffffffe
CM_DSI0PCTL_ENAB_BITS 4:4
CM_PLLD_LOADDSI0_MSB 0
SPI_CS_DONE_LSB 16
PM_IMAGE_POWUP_SET 0x00000001
DMA9_CS_DREQ_STOPS_DMA_SET 0x00000020
ASB_V3D_M_CTRL_FULL_MSB 3
EMMC_BLKSIZECNT_SDMA_BLKSIZE_BITS 14:12
A2W_XOSC_CTRL_PLLBEN_SET 0x00000080
PM_AVS_RSTDR_MASK 0x0000003f
ARM_MS_LEVEL 0x400000FF
USB_DOEPINT0_AHB_ERR_BITS 2:2
DMA11_DEBUG_FIFO_ERROR_LSB 1
SH_EDM_STATE_MACHINE_CLR 0xfffffff0
PM_PROC 0x7e100110:RW
HDMI_FIFO_CTL_INV_CLK_XFR_CLR 0xfffffff7
DMA8_CS_END_LSB 1
DSI0_PHYC_clane_hsen_sync_BITS 8:8
HD_CSC_CTL_WIDTH 8
CCP2TX_TIC_TIIE_SET 0x00000001
CM_UARTDIV_DIV_LSB 0
DMA15_TXFR_LEN_YLENGTH_SET 0x3fff0000
EMMC_IRPT_EN_CCRC_ERR_LSB 17
CM_VPUCTL_SRC_BITS 3:0
USB_GRSTCTL_TXF_NUM_MSB 10
GP_FSEL1_FSEL19_SET 0x38000000
EMMC_HWCAP1_SDR50_SET 0x00000001
SCALER_DISPBKGND1_MASK 0xffffffff
CM_LOCK_FLOCKC_MSB 10
SD_DQRCRC13_FALL_CLR 0xffff0000
EMMC_HWMAXAMP0_AMP_33V_LSB 0
SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_MSB 15
I2C0_A_MASK 0x0000007f
CM_ARMCTL_SRC_MSB 3
A2W_PLLB_DIG0_WIDTH 24
USB_GINTMSK_ULPI_CK_INT_CLR 0xfffffeff
DSI1_TXPKT2_C 0x7e70000c:RW
APERF0_BW1_CTRL_BUS_SET 0x0000001f
A2W_PLLC_CTRL_MASK 0x000373ff
DSI1_TXPKT2_H 0x7e700010:RW
USB_DPTXFSIZ8_MASK 0xffffffff
SLIM_DCC1_PA0_WIDTH 24
EMMC_FORCE_IRPT_CEND_ERR_SET 0x00040000
CM_TDCLKEN_PLLDBYP_SET 0x00000008
USB_GRXSTSP_DEV_PKT_STS_SET 0x001e0000
GP_FSEL6_FSEL60_LSB 0
SMI_DSW1_WPACEALL_LSB 15
APHY_CSR_GLBL_ADDR_DLL_RECAL 0x7ee06008:RW
PIXELVALVE2_VERTA_EVEN 0x7e80701c:RW
CM_ISPCTL_ENAB_CLR 0xffffffef
MS_SEMA_24_MASK_CLR 0xfffffffe
SH_EDM_STATE_MACHINE_MSB 3
HDMI_READ_POINTERS_DRFT_HOLD_RD_CLR 0xffbfffff
CM_DSI0HSCK_SELPLLD_MSB 0
PM_SMPS_CTRLEN_LSB 0
PCM_CS_A_RXON_MSB 1
ASB_CPR_CTRL_RCOUNT_MSB 13
DMA3_CS_ACTIVE_SET 0x00000001
EMMC_CONTROL1_MASK 0x070fffe7
HDMI_RAM_PACKET_8_7_RESET 0000000000
DMA_INT_STATUS_INT4_CLR 0xffffffef
USB_HCCHAR0_CH_DIS_BITS 30:30
CM_SMICTL 0x7e1010b0:RW
A2W_PLLB_ANA_STATR_WIDTH 12
GRSPCT 0x1A005800 + 0x18:RW
SD_SF_PGEHLD_T_MSB 28
CM_PLLTCTL_SRC_SET 0x00000007
GROPCTR_TU1_CACHE_ACCESSES 0x19
TB_TASK_PARAM1 0x7e20b004:RW
CM_CAM0CTL_BUSY_BITS 7:7
USB_GOTGCTL_HNP_REQ_LSB 9
AVE_OUT_CB_COEFF_RED_COEFF_SET 0x3ff00000
CM_OTPDIV_WIDTH 17
A2W_SMPS_L_SPA_RESET 0000000000
STCLO_1 0xffffffff:RO
A2W_PLLA_DIG1R_WIDTH 24
SLIM_MC_IN_STAT_RESET 0000000000
SPI_FIFO_RESET 0000000000
I2C_SPI_SLV_DMACR_TXDMAE_CLR 0xfffffffd
CPG_Param2_MASK 0xffffffff
PM_PADS0_MASK 0x0000003f
FPGA_CTRL0_DIS_BL_LSB 1
CCP2TX_TAC_APD_MSB 1
GP_SET0_SETn0_SET 0xffffffff
HDMI_CTS_PERIOD_1_RESET 0x010124f8
EMMC_CONTROL0_HCTL_LED_LSB 0
DMA14_DEBUG_DMA_ID_MSB 15
EMMC_FORCE_IRPT_ADMA_ERR_BITS 25:25
GP_FSEL0_FSEL05_LSB 15
MPHI_INTCTRL 0x7e006058:RW
SD_DQRCRC11_RISE_BITS 31:16
EMMC_IRPT_MASK_INT_A_CLR 0xfffffdff
CM_TIMERCTL_KILL_CLR 0xffffffdf
GP_EDS2_EDSn64_BITS 5:0
SLIM_DCC3_PROT_WIDTH 32
DMA2_TI_INTEN_LSB 0
SCALER_DISPECTRL_GT8_BURST_CLR 0x00ffffff
CM_ISPCTL_BUSYD_BITS 8:8
USB_DOEPINT1_MASK 0xffffffff
EMMC_HWMAXAMP0_AMP_18V_CLR 0xff00ffff
USB_DCTL_RMT_WKUP_SIG_LSB 0
HDMI_CP_INTEGRITY_CFG_MASK 0x0001ffff
SD_DQLCRC9_RISE_SET 0xffff0000
STCLO_x(x) MACRO
I2C_SPI_SLV_SLV_ADDR_MSB 6
SD_CS_ASHDNE_SET 0x00020000
DMA6_TI_NO_WIDE_BURSTS_SET 0x04000000
EMMC_INTERRUPT_BLOCK_GAP_LSB 2
A2W_PLLD_ANA_KAIP_KA_MSB 10
PM_RSTS_HADSRH_MSB 10
DMA2_CS_MASK 0xf0ff017f
DMA3_TI_PERMAP_MSB 20
A2W_SMPS_A_VOLTSR 0x7e102aa0:RW
CM_TIMERCTL_SRC_BITS 1:0
DMA5_DEBUG_WIDTH 29
CM_TDCLKEN_PLLBBYP_CLR 0xfffffffd
PCMTXC PCM_BASE_ADDRESS + 0x10:RW
A2W_PLLC_PER 0x7e102520:RW
L1_L1_SANDBOX_START7_START_ADDR_MSB 29
SYSAC_L2_ARBITER_CONTROL_THRESHOLD_BITS 5:4
DMA9_TI_BURST_LENGTH_MSB 15
VPU_ARB_CTRL_L2_CHANNEL_INIBIT_BITS 15:8
USB_DIEPINT0_XFER_COMPL_SET 0x00000001
AVE_OUT_CTRL_INVERT_EVEN_FIELD_SET 0x00010000
A2W_PLLC_ANA_SCTLR_WIDTH 5
A2W_PLLA_CTRL_PWRDN_CLR 0xfffeffff
DMA10_DEBUG_DMA_STATE_MSB 24
FPGA_CTRL0_SD_PSU_EN_BITS 4:4
SD_VIN_WRITE_LSB 16
APERF1_BW2_CTRL_RESET_CLR 0x7fffffff
EMMC_FORCE_IRPT_DATA_DONE_BITS 1:1
SPI_CS_CPHA_MSB 2
DMA_ENABLE_EN3_SET 0x00000008
DMA11_CS_DISDEBUG_BITS 29:29
DSI0_PHYC_forcehsstop_sync_MSB 2
TB_BOOT_SECURE_MODE_JTAG_SECURE_BITS 1:0
USB_HPRT_EN_CHNG_BITS 3:3
USB_DIEPDMAB10_MASK 0xffffffff
USB_DIEPTSIZ12 0x7e980a90:RW
USB_DIEPTSIZ13 0x7e980ab0:RW
USB_DIEPTSIZ14 0x7e980ad0:RW
USB_DIEPTSIZ15 0x7e980af0:RW
DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
PWM_CTL_MSEN3_MSB 23
CCP2TX_TS_IEB_MSB 1
USB_HCSPLT0_SPLT_ENA_RESET 0x0
SYSAC_ISP_PRIORITY_PRIORITY_BITS 3:0
CM_CAM1CTL_BUSY_CLR 0xffffff7f
DMA9_SOURCE_AD_S_ADDR_SET 0xffffffff
SMI_A_DEVICE_BITS 9:8
USB_GHWCFG4_HSPHY_DWIDTH_LSB 14
EMMC_IRPT_MASK_OEM_ERR_BITS 31:30
AVE_IN_OVERRUN_ADDRESS_MASK 0xffffffff
ASB_ISP_S_CTRL_RCOUNT_MSB 13
USB_HCCHAR0_LSPD_DEV_LSB 17
I2C_SPI_SLV_TDR_WIDTH 8
CCP2TX_TDL_RESET 0000000000
DMA8_DEBUG_VERSION_SET 0x0e000000
CMACIS 0x7C:RW
SLIM_DCC6_PA1_WIDTH 24
SH_VDD_POWER_ON_MSB 0
CM_TD0CTL_BUSY_MSB 7
I2C_SPI_SLV_CR_TESTFIFO_BITS 11:11
EMMC_CONTROL0_HCTL_CRDDET_S_SET 0x00000080
AVE_OUT_CTRL_INVERT_CSYNC_MSB 17
CM_PLLA_LOADPER_SET 0x00000040
USB_GOTGCTL_SES_REQ_SCS_LSB 0
CM_CKSM_OSC_BITS 19:18
USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_LSB 24
CM_V3DCTL_KILL_SET 0x00000020
CM_TD1CTL_FLIP_BITS 11:11
A2W_SMPS_C_CTL_UPEN_LSB 1
ASB_H264_S_CTRL_FULL_MSB 3
EMMC_IRPT_MASK_CCRC_ERR_SET 0x00020000
USB_DIEPDMAB4_WIDTH 32
PWM_RNG4_WIDTH 0
SLIM_FS_RESET 0000000000
PM_PADS2_POWOK_SET 0x00000020
EMMC_INTERRUPT_DMA_MSB 3
CM_OTPCTL_BUSYD_SET 0x00000100
A2W_PLLH_DIG3R 0x7e10286c:RW
EMMC_BUS_CTRL_BE_PWR_LSB 24
PWM_CTL_POLA1_LSB 4
EMMC_CMDTM_CMD_CRCCHK_EN_BITS 19:19
I2C_SPI_SLV_DMACR_RESET 0000000000
HD_VID_CTL_CLRSYNC_MSB 24
AVE_IN_CTRL_LOW_PRIORITY_CLR 0xfff0ffff
SYSAC_UC_ARBITER_CONTROL_THRESHOLD_SET 0x00000030
PCM_INTSTC_A_TXW_BITS 0:0
GR_TU_DBG_BASE 0x1A005300
SD_DQRCRC13_WIDTH 32
USB_HCSPLT0_COMP_SPLT_CLR 0xfffeffff
DMA8_CS_DISDEBUG_LSB 29
DSI1_PHYC_WIDTH 32
USB_DOEPINT0_IN_EP_NAK_EFF_SET 0x00000040
A2W_PLLD_CORE_BYPEN_SET 0x00000200
CM_OSCFREQF_RESET 0000000000
DMA2_TI_BURST_LENGTH_SET 0x0000f000
AVE_OUT_CTRL_COEFF_IRQ_EN_BITS 1:1
SD_SECSRT2_ADDR_MS_BITS 31:13
A2W_PLLB_DIG0_RESET 0000000000
DMA15_STRIDE_D_STRIDE_CLR 0x0000ffff
TB_JTB_CONFIG_OUT_MS_CLR 0xffffffbf
PIXELVALVE2_VSYNCD_EVEN 0x7e807008:RW
APHY_CSR_PHY_BIST_CA_CRC_SPR 0x7ee06084:RW
CM_VECDIV_MASK 0x0000f000
SD_VIN_WRITE_SET 0x00010000
MS_VPUSEMA_1_VPUSEMA_1_LSB 0
L1_IC0_CONTROL_START_FLUSH_BITS 1:1
L1_L1_SANDBOX_START4_RESET 0000000000
PWM_STA_STA2_SET 0x00000400
A2W_PLLH_ANA0_WIDTH 24
L1_IC0_CONTROL_RAS_DISABLE_LSB 4
DMA13_CS_ACTIVE_MSB 0
SCALER_DISPECTRL_PANIC_CTRL_SET 0x0000007f
A2W_PLLB_ANA_MULTI_MASK 0000000000
CM_EVENT_WRFAIL_LSB 19
EMMC_CONTROL0_ALT_BOOT_EN_CLR 0xffbfffff
HDMI_RAM_PACKET_9_0_MASK 0xffffffff
USB_DCTL_GNP_IN_NAK_STS_SET 0x00000004
DMA11_TI_SRC_DREQ_CLR 0xfffffbff
EMMC_CONTROL0_GAP_RESTART_CLR 0xfffdffff
TE_0VSWIDTH_WIDTH 32
USB_DIEPTXF11_MASK 0xffffffff
CM_DSI1EDIV_DIV_LSB 4
USB_GHWCFG4_EN_A_VALID_FILTER_MSB 22
TB_BOOT_OPT_TB_PRESENT_BITS 31:31
DMA11_DEBUG_VERSION_SET 0x0e000000
DMA10_TI_SRC_INC_CLR 0xfffffeff
DSI0_PHYC_txulps_clk_sync_MSB 9
DMA11_SOURCE_AD_WIDTH 32
DSI0_HS_CLT1_MASK 0x000003fc
SD_SA_POWSAVE_CLR 0xfffffffe
CM_EMMCDIV_WIDTH 16
PIARBCTL_CAM_LIMIT_SET 0x00000003
I2C_SPI_SLV_VCSTAT_DATA_SET 0x0000000f
CM_GP2CTL_WIDTH 10
A2W_PLLH_AUX_CHENB_LSB 8
USB_DOEPTSIZ9_WIDTH 32
SD_DQLCRC5_WIDTH 32
SMI_DSW0_WHOLD_SET 0x003f0000
A2W_PLLC_CORE1 0x7e102420:RW
DMA1_TI_SRC_INC_BITS 8:8
USB_DSTS_SOF_FN_RESET 0x0
SYSAC_HVSM_PRIORITY_MASK 0x000000ff
I2CDLEN 0x7e205000 + 0x08:RW
CM_DPICTL_SRC_SET 0x0000000f
CM_GP2DIV_MASK 0x00ffffff
SCALER_DISPLSTAT_WIDTH 32
HDMI_VERTA1_MANUAL_VFP1_BITS 19:13
EMMC_STATUS_DAT_LEVEL0_MSB 23
HDMI_VERTB0_MANUAL_VSPO0_BITS 21:9
PM_AVS_RSTDR_RESET 0000000000
PM_RSTC_HRCFG_MSB 21
DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
EMMC_CONTROL1_SRST_DATA_SET 0x04000000
DMA3_STRIDE_D_STRIDE_BITS 31:16
CM_PLLC_LOADCORE1_CLR 0xfffffffb
USB_DIEPTSIZ3_MASK 0xffffffff
SYSAC_TRANS_PRIORITY_N_PRIORITY_SET 0x0000000f
ARM_ID 0x7E00B000 +0x44C:RW
CM_LOCK_MASK 0x00001f1f
CM_SLIMCTL_KILL_SET 0x00000020
MPHI_MINFS_LEVEL_CLR 0xfffffc00
DMA3_SOURCE_AD_S_ADDR_LSB 0
SD_MR_DONE_CLR 0x7fffffff
DMA4_TI_DEST_WIDTH_MSB 5
SMI_CS_INTT_RESET 0x0
MPHI_INTCTRL_HSDISC_SET 0x00010000
DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
IC1_MASK2_MASK 0x77777777
DMA12_CS_PRIORITY_CLR 0xfff0ffff
DSI0_PIX_FIFO 0x7e209020:RW
I2C1_DIV_RESET 0x000005dc
CCP2TX_TD_TCS_CLR 0xffffffe0
EMMC_CMDTM_CMD_CRCCHK_EN_SET 0x00080000
A2W_PLLC_CTRL_PWRDN_MSB 16
CM_GNRICCTL_SRC_LSB 0
ASB_V3D_M_CTRL_CLR_REQ_CLR 0xfffffffe
A2W_PLLH_ANA1_RESET 0x00000014
EMMC_STATUS_NEW_READ_DATA_SET 0x00000800
MPHI_C0INDCF_MTERM_LSB 28
EMMC_IRPT_MASK_WRITE_RDY_LSB 4
IC1_FORCE0_CLR_RESET 0000000000
L1_L1_SANDBOX_START5_CTRL_BITS 0:0
CM_ISPCTL_BUSYD_SET 0x00000100
DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
SLIM_DCC0_PROT_WIDTH 32
UART_MCR_MASK 0x0000001f
I2C_SPI_SLV_CR_TESTFIFO_SET 0x00000800
HDMI_RAM_PACKET_8_5_WIDTH 32
SD_SB_STBY_T_RESET 0x0
EMMC_INTERRUPT_CTO_ERR_LSB 16
APERF1_BW1_CTRL_ID_BITS 12:8
ISP_BASE 0x7ea00000
APERF0_BW0_WMAX 0x7e009858:RO
GP_FSEL4_FSEL44_MSB 14
DMA8_CS_ABORT_BITS 30:30
SYSAC_HVSM_PRIORITY_P_PRIORITY_BITS 7:4
HDMI_RAM_PACKET_12_5_WIDTH 32
DMA9_CS_ERROR_LSB 8
DMA9_NEXTCONBK_ADDR_MSB 31
GP_FSEL6_FSEL65_CLR 0xfffc7fff
SD_PRE_RESET 0000000000
A2W_PLLD_ANA_SCTL_SEL_BITS 2:0
AVE_OUT_Y_COEFF_GREEN_COEFF_CLR 0xfff003ff
A2W_HDMI_CTL0_MASK 0x00ffffff
EMMC_CONTROL1_CLK_EN_MSB 2
HDMI_VERTA1_MANUAL_VSP1_BITS 24:20
EMMC_TUNE_STEP_DELAY_LSB 0
HDMI_RAM_PACKET_4_7_WIDTH 32
I2C_SPI_SLV_DR_MASK 0xffff3fff
PM_GNRIC_ENAB_LSB 12
PCM_RXC_A_MASK 0xffffffff
PM_AVS_INTEN_ALERT_PERI_A_MSB 0
JNCB 0x7e005000 + 0x14:RW
EMMC_INTERRUPT_ACMD_ERR_CLR 0xfeffffff
DMA_INT_STATUS_INT12_LSB 12
DMA7_DEST_AD_D_ADDR_MSB 31
L1_IC1_PRIORITY_IC1_APRIORITY3_SET 0x0000f000
A2W_PLLC_PERR_MASK 0x000003ff
USB_DIEPDMAB13_WIDTH 32
HD_MAI_CTL_CHALIGN_CLR 0xffffdfff
VPU_ARB_CTRL_L2_LIMIT_MSB 1
IC0_PROFILE 0x7e002038:RW
DMA3_TI_SRC_INC_CLR 0xfffffeff
CM_TIMERDIV 0x7e1010ec:RW
EMMC_CONTROL0_HCTL_CRDDET_CLR 0xffffffbf
USB_MDIO_CSR 0x7e980000 + 0x80:RW
EMMC_CMDTM_TM_MULTI_BLOCK_SET 0x00000020
HDMI_READ_POINTERS_DRFT_WR_ADDR_CLR 0xffff00ff
USB_GUSBCFG_IND_COMP_CLR 0xff7fffff
DMA6_DEBUG_READ_ERROR_MSB 2
DMA15_CS_PRIORITY_SET 0x000f0000
USB_DPTXFSIZ11 0x7e98012c:RW
USB_DPTXFSIZ12 0x7e980130:RW
SD_RWC_MAXCNT_MSB 28
HDMI_RAM_PACKET_10_6_MASK 0xffffffff
USB_DPTXFSIZ15 0x7e98013c:RW
USB_GNPTXFSIZ_NP_TXF_DEP_MSB 31
SD_DQLCRC14_FALL_LSB 0
DMA2_TI_SRC_IGNORE_CLR 0xfffff7ff
L2_CONT_OFF_l2_flush_mode_CLR 0xffffffe7
USB_GRSTCTL_TXF_NUM_LSB 6
DSI0_PHYC_txulpshs_1_sync_CLR 0xffffffbf
CM_BURSTCTL_BUSY_CLR 0xffffff7f
CM_INTEN_LOSSH_CLR 0xfffffdff
DMA4_TI_BURST_LENGTH_CLR 0xffff0fff
AVE_OUT_Y_COEFF_BLUE_COEFF_CLR 0xfffffc00
SMI_DSW3_WSWAP_BITS 22:22
PWM_RNG1 0x7e20c010:RW
PWM_RNG2 0x7e20c020:RW
PWM_RNG3 0x7e20c030:RW
PWM_RNG4 0x7e20c040:RW
L2_CONT_OFF_l2_enable_stats_SET 0x00000020
SMI_DSW0_WWIDTH_BITS 31:30
EMMC_INTERRUPT_ATA_ERR_SET 0x20000000
DMA1_TI_WAIT_RESP_BITS 3:3
PCMMODE_FSM (1 << 21)
HDMI_RAM_PACKET_6_4_RESET 0000000000
CM_GP1CTL_BUSY_SET 0x00000080
USB_GHWCFG2_ARCHITECTURE_MSB 4
HD_MAI_CTL_ERRORF_RESET 0x0
I2C_SPI_SLV_HCTRL_RESET 0000000000
OTP_CTRL_HI_REG_WIDTH 16
GP_FSEL5_FSEL54_SET 0x00007000
HDMI_HDCP_CTL_MASK 0x0001030f
FPGA_CTRL0_CAM_CTL0_SET 0x00000001
SD_SD_T_XP_RESET 0x2
AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_BITS 29:29
PWMSTA_GAPO2 5
CM_CCP2CTL_BUSYD_BITS 8:8
USB_GHWCFG4_EN_A_VALID_FILTER_BITS 22:22
L1_L1_SANDBOX_START0_CTRL_LSB 0
ST_C1_RESET 0000000000
FPGA_CTRL0_TERMEN_DO_SET 0x00010000
CM_OTPCTL_SRC_MSB 1
USB_GPVNDCTL_REG_WR_LSB 22
I2C_SPI_SLV_DR_RXBUSY_BITS 21:21
A2W_PLLC_ANA_SCTL_RESET_SET 0x00000010
V3D_PCTRS7_WIDTH 5
CM_LOCK_LOCKA_BITS 0:0
HDMI_RAM_PACKET_2_6_RESET 0000000000
TB_JTB_BITCNT 0x7e20b810:RW
HDMI_RAM_PACKET_5_3_MASK 0xffffffff
CM_PLLH_DIGRST_SET 0x00000200
DSI1_HS_DLT4_WIDTH 32
DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
USB_DIEPTXF6_MASK 0xffffffff
HDMI_HORZA_MANUAL_VPOL_CLR 0xffffbfff
A2W_PLLA_DIG3R_RESET 0x00000004
DMA12_TI_SRC_INC_MSB 8
MS_VPU_STAT_VPU_STAT_BITS 0:0
CM_GP1CTL 0x7e101078:RW
CM_EVENT_WRFAIL_BITS 19:19
DMA_INT_STATUS_INT15_CLR 0xffff7fff
PM_AVS_EVENT_ALERT_H264_I_SET 0x00000004
SMI_A 0x7e600008:RW
MS_MBOX_5_MBOX_CLR 0x00000000
HDMI_PERT_LFSR_FEEDBACK_MASK_RESET 0000000000
USB_DCTL_TST_CTL_CLR 0xffffff8f
SMI_L 0x7e600004:RW
CM_EVENT_OCDONE_SET 0x00200000
DMA4_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
EMMC_IRPT_MASK_DMA_ERR_CLR 0xefffffff
EMMC_TUNE_STEP_DELAY_SET 0x00000007
USB_HCCHAR0_CH_ENA_MSB 31
A2W_PLLA_CCP2R_WIDTH 10
PM_PADS3_SLEW_CLR 0xffffffef
EMMC_IRPT_MASK_CMD_DONE_CLR 0xfffffffe
TE_1TIMER_WIDTH 32
PWM_CTL_WIDTH 32
A2W_PLLC_ANA_STATR_WIDTH 12
USB_HCINTMSK4_WIDTH 32
PM_DSI1_LDOLPEN_CLR 0xfffffffd
CMCORE 0x7C:RW
A2W_SMPS_CTLB2_WIDTH 24
A2W_PLLD_DIG1R 0x7e102844:RW
SMI_DSR0_RSETUP_BITS 29:24
PM_PADS5_I2CMODE_MSB 6
A2W_XOSC_CPR_DIV_LSB 0
GRSDOU 0x1A005800 + 0x28:RW
PM_CAM1_LDOCTRL_SET 0x001ffff8
SD_RWC_RSTMAX_CLR 0x7fffffff
CM_CKSM_AUTO_CLR 0xffefffff
HDCP_KEY_KY0 0x7e809008:RW
HDCP_KEY_KY1 0x7e80900c:RW
CM_PLLD_HOLDCORE_SET 0x00000020
GP_FSEL4_FSEL40_LSB 0
UART_LSR_MASK 0x000000ff
A2W_PLLC_ANA_SSCS_MODE_LSB 16
SD_CS_CLKOFF_BITS 14:14
PWM_CTL_SBIT4_MSB 27
EMMC_TUNE_STEPS_DDR_STEPS_MSB 5
MPHI_INTSTAT_RX0DISC_RESET 0x0
ARM_0_MAIL0_SND (0x7E00B000 +0x800)+0x94:RW
PM_PXLDO_RSTOSCDR_CLR 0xfffeffff
I2C_SPI_SLV_CR_RXE_LSB 9
DMA10_TI_WAITS_CLR 0xfc1fffff
DSI0_PR_TO_CNT_RESET 0000000000
L1_L1_SANDBOX_START2_WIDTH 30
CM_EVENT_LOSSB_SET 0x00000040
PWM_STA_EMPT1_BITS 1:1
DMA6_TXFR_LEN 0x7e007614:RO
USB_DCTL_IGN_FRM_NUM_CLR 0xffff7fff
A2W_XOSC_CPR_CPR1_BITS 4:4
CPG_Param0_WIDTH 32
CM_ISPCTL_FRAC_SET 0x00000200
USB_DIEPEMPMSK_EP_TXF_EMP_MSK_MSB 15
EMMC_INTERRUPT_ERR_MSB 15
CAM0_CAMICTL_WIDTH 32
CMI_CAMTEST_ENAB_CLR 0xffffffef
DMA14_TI_WAIT_RESP_LSB 3
I2C_SPI_SLV_IMSC_MASK 0x0000000f
SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_MSB 7
CM_DFTDIV_DIV_MSB 16
HDMI_VERTA1_MANUAL_VSP1_SET 0x01f00000
HD_VID_CTL_FULSYNC_SET 0x00400000
ASB_ISP_S_CTRL_CLR_REQ_LSB 0
PM_PROC_ENAB_CLR 0xffffefff
DMA8_TI_DEST_INC_BITS 4:4
PM_SMPS_WIDTH 3
A2W_SMPS_L_SPVR_MASK 0x0000001f
USB_DIEPDMAB14 0x7e980ad8:RW
CM_OTPCTL_FRAC_CLR 0xfffffdff
A2W_PLLD_ANA_SCTLR_WIDTH 5
DMA10_TI_INTEN_BITS 0:0
MS_ICSET_1_ICSET_1_SET 0x00000001
USB_DIEPDMA10 0x7e980a54:RW
A2W_PLLD_DIG3R 0x7e10284c:RW
PCM_DREQ_A_TX_PANIC_CLR 0x80ffffff
L1_D0_WR_HITS 0x7ee02150:RO
USB_DIEPDMA14 0x7e980ad4:RW
USB_DIEPDMA15 0x7e980af4:RW
TB_JTB_CONFIG_INV_CLK_LSB 7
A2W_PLLH_DIG1_WIDTH 24
DMA5_TI_SRC_INC_MSB 8
SD_SECSRT2_EN_SET 0x00000001
V3D_PCTR9_WIDTH 32
A2W_SMPS_CTLB2R_WIDTH 24
MPHI_OUTDDB_HANDLE_SET 0x0ff00000
I2C_SPI_SLV_CR_ENSTAT_CLR 0xffffffdf
I2C_SPI_SLV_DR_TXDMAPREQ_CLR 0xfffffbff
SD_CS_ASHDNE_CLR 0xfffdffff
CM_ARMCTL_BUSYD_MSB 8
SD_DQLCRC2_FALL_SET 0x0000ffff
SD_DQRCRC14_RISE_RESET 0x0
USB_DIEPINT1_MASK 0xffffffff
A2W_PLLD_ANA1R_MASK 0x00ffffff
CM_PERIIDIV_RESET 0x00001000
USB_DOEPINT10_WIDTH 32
CM_DFTDIV_DIV_BITS 16:12
SD_SECEND3_ADDR_MS_MSB 31
DMA_INT_STATUS_INT8_SET 0x00000100
CM_DSI0ECTL_BUSY_SET 0x00000080
USB_GOTGINT_HST_NEG_DET_MSB 17
PM_CCP2TX_LDOEN_CLR 0xfffffffd
CM_TSENSDIV_RESET 0000000000
CM_CAM1DIV_RESET 0000000000
A2W_PLLB_SP2_DIV_LSB 0
AVE_IN_FRAME_NUM_FRAME_NUM_CLR 0xfffff000
A2W_XOSC_CTRL_PLLBEN_CLR 0xffffff7f
A2W_PLLB_SP2_DIV_SET 0x000000ff
DMA6_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
PCMINTEN 0x7e203000 + 0x18:RW
DMA14_TXFR_LEN 0x7e007e14:RO
SMI_DSR2_MODE68_CLR 0xff7fffff
USB_DOEPDMA0_MASK 0xffffffff
DMA14_TI_SRC_WIDTH_LSB 9
CAM1_CAMSTA_WIDTH 32
SMI_DSR0_RPACE_CLR 0xffff80ff
L1_IC0_CONTROL_START_FLUSH_LSB 1
I2C_SPI_SLV_FR_RXBUSY_SET 0x00000020
APERF0_BW2_WMAX 0x7e0098d8:RO
SMI_DSR3_RDREQ_CLR 0xffffff7f
ASB_CPR_CTRL_EMPTY_BITS 2:2
GRSPSZ 0x1A005800 + 0x34:RW
HD_VID_CTL_EMPSYNC_CLR 0xffefffff
A2W_PLLB_ANA_SCTL_UPDATE_CLR 0xfffffff7
HDMI_RAM_PACKET_7_7_MASK 0xffffffff
CM_DSI1ECTL 0x7e101158:RW
HDCP_KEY_CTL_START_SET 0x00000001
DMA11_DEBUG_READ_ERROR_SET 0x00000004
CM_PLLD_HOLDPER_CLR 0xffffff7f
HDMI_RAM_PACKET_1_6_MASK 0xffffffff
USB_GUSBCFG_ULPI_FS_LS_CLR 0xfffdffff
SD_CS_DLLCAL_RESET 0x0
A2W_PLLH_MULTI_RESET 0000000000
DMA5_TI_DEST_IGNORE_BITS 7:7
A2W_HDMI_CTL_RCAL_MASK 0x00011f33
DMA3_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
CM_DSI0PCTL 0x7e101060:RW
APERF0_BW2_RTWAIT 0x7e0098e0:RO
DMA11_CS_ERROR_MSB 8
A2W_PLLD_ANA_VCO_WIDTH 1
MPHI_HSINDS_WORDS_SET 0x001fffff
ASB_H264_M_CTRL_WCOUNT_BITS 23:14
HW_REGISTER_RO(addr) MACRO
CM_LOCK_LOCKC_CLR 0xfffffffb
SMI_DSW0_WSWAP_BITS 22:22
USB_DIEPDMAB9_MASK 0xffffffff
HW_REGISTER_RW(addr) MACRO
PM_CAM0_CTRLEN_BITS 0:0
UART_LSR_OE_LSB 1
SYSAC_DBG_PRIORITY_PRIORITY_CLR 0xfffffff0
SMI_DA 0x7e600038:RW
CPG_IntStatus_WIDTH 32
IC0_SRC0_MASK 0xffffffff
SD_PHYC_CRC_EN_CLR 0xffefffff
VPU_ARB_CTRL_L2_RESET 0000000000
SLIM_DMA_MC_STAT_RESET 0000000000
TB_TASK_RXDATA2 0x7e20b088:RW
HDMI_VERTA1_RESET 0x002141e0
SMI_DSW2_WSETUP_LSB 24
HDMI_SCHEDULER_CONTROL_ALWS_VERT_KEEPOUT_LSB 3
SYSAC_ISP_PRIORITY 0x7e00901c:RW
TS_TSENSCTL_RESET 0000000000
IS_ALIAS_NONALLOCATING(x) MACRO
SH_HCFG_WIDE_INT_BUS_SET 0x00000002
DSI1_HS_CLT0_RESET 0000000000
GP_CLR0_MASK 0xffffffff
SD_DQLCRC15_FALL_SET 0x0000ffff
OTP_PUBLIC_KEY_ROW ((((((((((((((8 +4)+4)+1)+1)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)
DMA0_TI_DEST_DREQ_LSB 6
DMA3_CS_DREQ_STOPS_DMA_LSB 5
EMMC_IRPT_EN_CARD_OUT_MSB 7
DMA12_SOURCE_AD_S_ADDR_BITS 31:0
CM_DSI1ECTL_ENAB_SET 0x00000010
SD_DQRCRC4_FALL_SET 0x0000ffff
PCM_TXC_A_CH1EN_CLR 0xbfffffff
USB_DSTS_ERRTIC_ERR_BITS 3:3
SD_DQRCRC7_RISE_BITS 31:16
SCALER_DISPBASE_1 0x7e400000 + 0x5C:RW
SCALER_DISPBASE_2 0x7e400000 + 0x6C:RW
DMA12_TI_SRC_DREQ_CLR 0xfffffbff
A2W_SMPS_B_STAT_BSTPWMB_LSB 8
EMMC_SPI_INT_SPT_SELECT_CLR 0xffffff00
AVE_OUT_STATUS_PXL_FORMAT_ERROR_MSB 0
L1_L1_SANDBOX_START7_CTRL_LSB 0
CM_AVEODIV 0x7e1011bc:RW
PCM_CS_A_RXCLR_BITS 4:4
USB_HCDMA0_WIDTH 32
DMA15_SOURCE_AD_WIDTH 32
A2W_PLLB_SP2_CHENB_BITS 8:8
USB_DOEPINT0_OUT_TKN_EP_DIS_LSB 4
GP_AFEN0_AFENn0_MSB 31
EMMC_EXRDFIFO_CFG_RD_THRSH_BITS 2:0
HDMI_SCHEDULER_CONTROL_POSTLN_AVOID_MSB 13
PCM_MODE_A_FRXP_LSB 25
SD_DQLCRC13_WIDTH 32
HDMI_RAM_PACKET_6_2_WIDTH 32
CDP_DEBUG0 0x1C00E000 + 0x0C:RW
CDP_DEBUG1 0x1C00E000 + 0x10:RW
USB_GHWCFG4_HSPHY_DWIDTH_SET 0x0000c000
SMI_DSW2_WSWAP_CLR 0xffbfffff
DMA11_TI_SRC_WIDTH_CLR 0xfffffdff
APERF0_GEN_CTRL_ENABLE_LSB 0
CM_INTEN_FLOSSA_LSB 14
CM_CAM1DIV_DIV_SET 0x0000fff0
SMI_DC_DMAP_BITS 24:24
A2W_XOSC_CTRL_DDREN_MSB 4
USB_DPTXFSIZ1_MASK 0xffffffff
CM_EMMCDIV_MASK 0x0000fff0
EMMC_IRPT_MASK_INT_C_BITS 11:11
PWM_CTL_MODE4_CLR 0xfdffffff
DMA2_TI_SRC_INC_BITS 8:8
INTERRUPT_CAM1 ((64) + 39 )
USB_HCINT0_XACT_ERR_BITS 7:7
GP_FSEL1_FSEL13_CLR 0xfffff1ff
DMA11_TI_SRC_INC_BITS 8:8
IC0_C_WIDTH 4
APERF0_BW0_CTRL_ID_EN_CLR 0xdfffffff
MPHI_INTSTAT_OMFUFLW_LSB 28
CM_PLLA_LOADDSI0_CLR 0xfffffffe
CM_TSENSCTL_FRAC_LSB 9
MS_SEMA_18_MASK_SET 0x00000001
I2C_SPI_SLV_CR_TXE_CLR 0xfffffeff
HDMI_RAM_PACKET_2_4_WIDTH 32
SMI_FD 0x7e600040:RW
CM_SDCCTL_ACCPT_SET 0x00010000
ARM_0_MAIL0_STA (0x7E00B000 +0x800)+0x98:RW
SD_SECSRT3_ADDR_MS_SET 0xffffe000
HDMI_FIFO_CTL_RECENTER_DONE_MSB 14
CM_GNRICCTL_MASK 0x000fffff
MPHI_OUTDFS_DFIFOLVL_CLR 0xffff0000
PM_GNRIC_MEMREP_SET 0x00000008
SMI_DCS_DONE_SET 0x00000004
HDMI_SCHEDULER_CONTROL_USE_POSTLN_AVOID_SET 0x00004000
CM_CKSM 0x7e101124:RW
PM_RSTC_RESET 0x00000102
VPU_ARB_CTRL_UC_THRESHOLD_MSB 5
SD_MR_HI_Z_BITS 29:29
PM_DSI0_LDOHPEN_CLR 0xfffffffb
DMA5_CS_ACTIVE_CLR 0xfffffffe
DMA13_CS_PRIORITY_CLR 0xfff0ffff
SD_SB_BANKLOW_SET 0x00000060
DMA3_TI_DEST_DREQ_BITS 6:6
SH_CMD_BUSY_CMD_BITS 11:11
DMA10_NEXTCONBK 0x7e007a1c:RO
USB_DOEPCTL0_CNAK_SET 0x04000000
SCALER_DISPECTRL_TWOD_SINGLE_MSB 31
SCALER_DISPECTRL_Y_BUSY_LSB 9
MPHI_CTRL_STBY_CLR 0xf7ffffff
JP_C0S 0x7e005058:RW
SD_DQLCRC14_FALL_RESET 0x0
SD_PT2_T_INIT5_MSB 15
JP_C0W 0x7e005064:RW
TH1_ADDR_MASK 0x0000003F
DMA4_CS_RESET_SET 0x80000000
HDMI_RAM_PACKET_4_1_RESET 0000000000
SMI_DSR3_RPACEALL_MSB 15
CM_AVEOCTL_ENAB_CLR 0xffffffef
SCALER_DISPSTAT_2 0x7e400000 + 0x68:RW
DMA8_CS_PRIORITY_BITS 19:16
MPHI_C1INDS_WIDTH 32
HDMI_HORZA_MANUAL_VPOL_BITS 14:14
DMA_INT_STATUS_INT15_LSB 15
SD_VIN_MASK 0x9113ffff
MS_IREQ_1_IREQ_1_CLR 0x00000000
CM_PLLTCNT3_RESET 0000000000
GP_FSEL0_FSEL02_SET 0x000001c0
EMMC_EXRDFIFO_EN_MASK 0x00000001
GP_SET0_RESET 0000000000
GP_SEN0_SEN_CLR 0x00000000
USB_GINTMSK_GOUT_NAK_EFF_CLR 0xffffff7f
L1_L1_SANDBOX_END3_WIDTH 30
APERF0_BW2_CTRL_ID_RESET 0x0
APERF1_BW0_CTRL_ID_BITS 12:8
INTERRUPT_GPIO0 ((64) + 48 )
INTERRUPT_GPIO1 ((64) + 49 )
INTERRUPT_GPIO2 ((64) + 50 )
INTERRUPT_GPIO3 ((64) + 52 )
HDCP_KEY_CTL_DONE_BITS 1:1
CM_DSI0PCTL_FRAC_CLR 0xfffffdff
CM_V3DCTL_ENAB_BITS 4:4
A2W_SMPS_B_STAT_RESET 0000000000
JP_C1S 0x7e00505c:RW
PCM_RXC_A_CH2EN_LSB 14
I2C_SPI_SLV_CR_CPOL_BITS 4:4
JP_C1W 0x7e005068:RW
CAM1_CAMICC_MASK 0xffffffff
FPGA_DCM_CTRL_PERI_WR_EN_BITS 31:28
SCALER_DISPBASE1_WIDTH 32
I2C_SPI_SLV_DR_RXFE_LSB 17
DMA3_CS_ABORT_SET 0x40000000
DSI1_RXPKT1_H 0x7e700014:RO
GROPCTR_FBC_CZ_FE_HITS 0x2D
INTERRUPT_GPION ((64) + 51 )
A2W_PLLH_FRAC_WIDTH 20
MS_STATUS_WIDTH 32
DMA0_TI_NO_WIDE_BURSTS_LSB 26
PIXELVALVE1_C_WIDTH 24
CM_UARTCTL_ENAB_CLR 0xffffffef
JMCTRL_CMP(n) MACRO
MPHI_C0INDDA_START_CLR 0x00000000
ASB_CPR_CTRL_CLR_ACK_LSB 1
A2W_PLLH_PIX_CHENB_BITS 8:8
DMA13_DEBUG_OUTSTANDING_WRITES_LSB 4
DMA4_CS_DISDEBUG_MSB 29
DMA_ENABLE_EN0_SET 0x00000001
SH_CMD_FAIL_FLAG_MSB 14
PM_RSTC_MASK 0x00333333
CM_SMICTL_BUSY_MSB 7
USB_HCTSIZ2_MASK 0xffffffff
CM_VPUCTL_GATE_CLR 0xffffffbf
SMI_DSW0_WSTROBE_LSB 0
DMA1_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
CM_EVENT_LOSSH_BITS 9:9
CSI2_RC_x(x) MACRO
A2W_PLLA_CORE_DIV_SET 0x000000ff
EMMC_IRPT_MASK_CARD_IN_SET 0x00000040
HDMI_RAM_PACKET_8_6 0x7e902538:RW
JP_C2W 0x7e00506c:RW
SCALER_DISPSTAT_DMA_ERR_BIT0_LSB 14
HD_MAI_CTL_CHALIGN_BITS 13:13
SD_DQLCRC12_RISE_SET 0xffff0000
SD_DQLCRC9_FALL_SET 0x0000ffff
APERF0_BW0_CTRL_LATHALT_CLR 0xefffffff
GRFZBA 0x1A005400 + 0x20:RW
PM_GNRIC 0x7e100000:RW
DMA12_TI_BURST_LENGTH_CLR 0xffff0fff
USB_DOEPCTL0_SET_ODD_FR_CLR 0xdfffffff
HDMI_RAM_PACKET_8_7 0x7e90253c:RW
AVE_OUT_STATUS_PXL_OUTPUT_ERROR_LSB 1
AVE_OUT_STATUS_PXL_FORMAT_ERROR_SET 0x00000001
HDMI_DETECTED_HORZA_MANUAL_HAP_SET 0x00001fff
A2W_SMPS_L_SIA_ANA_BITS 9:0
PWM_STA_STA4_SET 0x00001000
DMA9_DEBUG_DMA_ID_MSB 15
DMA11_CS_END_SET 0x00000002
SD_SD_T_RAS_LSB 8
MPHI_INTCTRL_RX1DISC_LSB 4
VEC_SOFT_RESET_MASK 0xffffffff
DMA1_TXFR_LEN_MASK 0x3fffffff
CPG_Debug0_MASK 0xffffffff
SD_SD_T_RC_SET 0x01f00000
HDMI_RAM_PACKET_8_8 0x7e902540:RW
HDMI_RAM_PACKET_4_1_WIDTH 32
AVE_IN_CTRL_PRIV_MODE_SET 0x00000080
PM_AUDIO_CTRLEN_CLR 0xffefffff
EMMC_FORCE_IRPT_DATA_DONE_CLR 0xfffffffd
A2W_PLLB_ANA_SSCS_MODE_MSB 16
UART_LCR_SBC_LSB 6
USB_DIEPINT0_IN_EP_NAK_EFF_MSB 6
DMA10_TI_DEST_DREQ_LSB 6
SMI_DSR1_FSETUP_CLR 0xffbfffff
AVE_OUT_CTRL_SOFT_RESET_LSB 30
SH_HSTS_BLOCK_IRPT_BITS 9:9
RNG_FF_THRESHOLD 0x7e10400c:RW
EMMC_BUS_CTRL_IRQ_PINS_SET 0x00000038
HD_HDM_CTL_ENABLE_BITS 0:0
GP_REN2_WIDTH 6
CM_PLLD_HOLDDSI1_MSB 3
PM_CCP2TX_LDOCTRL_SET 0x0007fffc
GP_FSEL6_FSEL69_SET 0x38000000
GRFZCV 0x1A005400 + 0x24:RW
PM_PADS2_POWOK_LSB 5
FPGA_CTRL0_DIS_RST_SET 0x00000008
CAM0_CAMIDI0_WIDTH 32
AVE_IN_BUF1_ADDRESS_WIDTH 32
USB_GPVNDCTL_NEW_REG_REQ_CLR 0xfdffffff
I2CC_START (1 << 7)
EMMC_IRPT_MASK_DCRC_ERR_BITS 21:21
APERF1_BW1_CTRL_ID_RESET 0x0
SMI_DSR1_FSETUP_BITS 22:22
CM_DSI0PCTL_FRAC_BITS 9:9
DMA7_CS_RESET_BITS 31:31
A2W_XOSC_CTRL_SMPSEN_CLR 0xfffffff7
A2W_PLLD_DIG3_RESET 0x00000004
SH_HBLC_RESET 0000000000
MPHI_RXAXICFG_RXPPRIO_RESET 0x0
PWM_CTL_PWEN3_SET 0x00010000
EMMC_INTERRUPT_CEND_ERR_LSB 18
DPHY_CSR_GLBL_DQ_DLL_RESET 0x7ee07004:RW
L1_IC0_PRIORITY_IC0_APRIORITY2_SET 0x00000f00
HD_CSC_CTL_ENABLE_LSB 0
USB_DPTXFSIZ9_WIDTH 32
MS_ICSET_0_ICSET_0_MSB 0
EMMC_CONTROL1_DATA_TOUNIT_BITS 19:16
USB_HCCHAR0_ODD_FRM_LSB 29
MS_SEMA_29_MASK_BITS 0:0
A2W_PLLA_ANA_VCO_RANGE_BITS 0:0
A2W_PLLH_ANA_VCO 0x7e102670:RW
CM_PLLB_DIGRST_SET 0x00000200
DMA6_CS_ABORT_BITS 30:30
I2C_SPI_SLV_RSR_OE_CLR 0xfffffffe
A2W_PLLD_ANA_STATR_WIDTH 12
APERF1_BW1_CTRL_RESET_LSB 31
APERF1_BW2_CTRL_ID_LSB 8
APERF0_BW2_RTRANS_MASK 0xffffffff
L1_L1_SANDBOX_START2_START_ADDR_CLR 0xc000001f
DMA3_DEBUG_FIFO_ERROR_MSB 1
PM_GRAFX_POWUP_BITS 0:0
SMI_DSW2_WDREQ_SET 0x00000080
SMI_DA_WRITE_SET 0x00000300
USB_DIEPINT0_OUT_TKN_EP_DIS_SET 0x00000010
DMA4_TI_WAITS_CLR 0xfc1fffff
PCM_RXC_A_CH1EN_CLR 0xbfffffff
SCALER_DISPCTRL 0x7e400000:RW
A2W_PLLA_ANA1R_WIDTH 24
SH_EDM_READ_THRESHOLD_MSB 18
USB_HPTXSTS_HPTXQTOP_MSB 31
SPI_CS_RXF_MSB 20
A2W_PLLB_SP2_WIDTH 10
A2W_PLLD_ANA3R_MASK 0x00ffffff
CM_TDCLKEN_MPHIRDFT_CLR 0xfffffbff
SMI_CS_TEEN_MSB 8
SD_TMC_TSTPAT_LSB 16
MPHI_C1INDS_VALID_LSB 30
DSI1_PR_TO_CNT_RESET 0000000000
USB_GHWCFG2_HSPHY_INTERFACE_BITS 7:6
DMA5_TXFR_LEN_XLENGTH_BITS 15:0
DMA8_TI_DEST_WIDTH_BITS 5:5
USB_HPRT_PWR_LSB 12
USB_DOEPTSIZ1_WIDTH 32
SMIDC_REQR 6
SD_VAD 0x7ee00084:RO
SLIM_DCC8_PA1_MASK 0x00ffff3f
VPU_ARB_CTRL_UC_CHANNEL_INIBIT_RESET 0x0
SD_MR_RDATA_BITS 23:16
SD_SECEND3_MASK 0xffffffff
L1_L1_SANDBOX_END7_MASK 0x3fffffe0
GP_FSEL5_FSEL55_LSB 15
EMMC_CONTROL0_WAKE_ONINT_EN_CLR 0xfeffffff
FPGA_CTRL0_CAM_CTL1_LSB 1
PCM_MODE_A_PDMN_CLR 0xf7ffffff
SD_SC_WL_MSB 2
DMA8_CS_ERROR_LSB 8
A2W_SMPS_A_GAINR_WIDTH 3
PM_IMAGE_ISPOW_BITS 2:2
DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
SD_CS_ASHDNE_RESET 0x0
DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
MS_SEMA_31_RESET 0000000000
USB_GHWCFG4_EN_DED_TX_FIFO_LSB 25
CM_EMMCCTL_KILL_BITS 5:5
A2W_SMPS_A_MODE_BSTPWMB_MSB 0
CM_TDCLKEN_USBDFT_MSB 11
DMA7_CS_DREQ_STOPS_DMA_LSB 5
A2W_PLLA_ANA_SSCL_LIMIT_CLR 0xffc00000
DMA15_CS_PANIC_PRIORITY_SET 0x00f00000
TS_TSENSCTL_CTRL_LSB 2
SD_DQLCRC4_RISE_MSB 31
SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_LSB 4
CM_HSMDIV_DIV_MSB 15
USB_DIEPINT0_IN_TKN_EP_MIS_RESET 0x0
DMA_CB_SA(n) MACRO
GRTDIM0 0x1A005200 + 0x08:RW
GRTDIM1 0x1A005220 + 0x08:RW
GRTDIM2 0x1A005240 + 0x08:RW
GRTDIM3 0x1A005260 + 0x08:RW
GRTDIM4 0x1A005280 + 0x08:RW
GRTDIM5 0x1A0052A0 + 0x08:RW
GRTDIM6 0x1A0052C0 + 0x08:RW
PM_WDOG_WIDTH 20
SH_HSTS_REW_TIME_OUT_MSB 7
PCMCS_SYNC (1 << 24)
USB_HPTXSTS_HPTXQSPCAVAIL_BITS 23:16
HDMI_READ_POINTERS_DRFT_WR_ADDR_BITS 15:8
SD_DQRCRC5_RISE_RESET 0x0
L2_CONT_OFF_l2_flush_CLR 0xfffffffb
I2CDEL_0 0x7e205000 + 0x18:RW
I2CDEL_1 0x7e804000 + 0x18:RW
I2CDEL_2 0x7e805000 + 0x18:RW
I2CDEL_3 I2C_BASE_3 + 0x18:RW
SD_CS_STBY_SET 0x00000008
SMIDC_DMAP 24
MPHI_INTSTAT_RX1TEND_RESET 0x0
DMA7_TI_WAIT_RESP_SET 0x00000008
SMI_DSR2_RSETUP_SET 0x3f000000
USB_DOEPINT0_EP_DISBLD_MSB 1
CM_VECCTL_SRC_MSB 3
SH_RSP3_CID_CSD_CLR 0x00000000
SD_DQRCRC0_FALL_LSB 0
SMI_CS_START_RESET 0x0
MPHI_INTCTRL_OMFUFLW_SET 0x00001000
DMA_TI_BURST_N(n) MACRO
CM_V3DCTL_GATE_SET 0x00000040
TB_BOOT_OPT_BANK_MODE_LSB 8
L1_D1_RD_SNOOPS 0x7ee02184:RO
A2W_PLLB_ANA0R_MASK 0x00ffffff
PWM_CTL_RPTL1_BITS 2:2
DMA2_TI_WAITS_BITS 25:21
SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_MSB 15
CM_CAM1CTL_KILL_SET 0x00000020
USB_DCFG_DEV_ADDR_BITS 10:4
SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_LSB 8
ARM_AIS_BELL0 0x00000001
ARM_AIS_BELL1 0x00000002
ARM_AIS_BELL2 0x00000004
ARM_AIS_BELL3 0x00000008
HDMI_SCHEDULER_CONTROL_HSYNC_PHYST_EN_SET 0x00010000
HDMI_DETECTED_VERTA0_WIDTH 25
DMA9_DEBUG_FIFO_ERROR_CLR 0xfffffffd
L1_IC1_CONTROL_BP_DISABLE_SET 0x00000008
CM_GNRICCTL_BUSYD_LSB 8
DMA15_CS_ABORT_CLR 0xbfffffff
I2CDEL_x(x) MACRO
USB_DCTL_CGNP_IN_NAK_CLR 0xfffffeff
AVE_IN_LINE_LENGTH_RESET 0000000000
HD_CSC_CTL_ENABLE_CLR 0xfffffffe
GP_AFEN1_MASK 0xffffffff
CM_GP2CTL_ENAB_MSB 4
PWM_STA_FULL1_MSB 0
CM_PLLTCNT1_WIDTH 24
SMI_DSW2_WSTROBE_CLR 0xffffff80
USB_GOTGINT_SES_END_DET_MSB 2
CM_H264CTL_KILL_LSB 5
DSI0_LP_DLT7_RESET 0000000000
PCM_CS_A_RXR_LSB 18
I2C_SPI_SLV_DR_TXFLEVEL_CLR 0xf83fffff
USB_GI2CCTL_DAT_SE0_LSB 28
SYSAC_HVSM_PRIORITY_P_PRIORITY_RESET 0x0
CM_EVENT_LOSSC_LSB 7
USB_DOEPTSIZ12_WIDTH 32
HDMI_RAM_PACKET_6_0 0x7e9024d8:RW
HDMI_RAM_PACKET_6_1 0x7e9024dc:RW
USB_DIEPDMA0_MASK 0xffffffff
HDMI_RAM_PACKET_6_3 0x7e9024e4:RW
HDMI_RAM_PACKET_6_4 0x7e9024e8:RW
HDMI_RAM_PACKET_6_5 0x7e9024ec:RW
HDMI_RAM_PACKET_6_6 0x7e9024f0:RW
HDMI_RAM_PACKET_6_7 0x7e9024f4:RW
HDMI_RAM_PACKET_6_8 0x7e9024f8:RW
MPHI_HSINDCF_LENERR_RESET 0x0
GP_FSEL1_MASK 0x3fffffff
I2C_SPI_SLV_DR_RXFF_BITS 19:19
CM_PLLD_ANARST_LSB 8
CM_DSI1PDIV_RESET 0x00001000
SD_DQRCRC6_RISE_MSB 31
TXP_CTRL_EI_BITS 2:2
PM_GRAFX_ISPOW_MSB 2
A2W_SMPS_C_CLK_USEOSC_MSB 2
APERF0_BW0_CTRL_BUS_MSB 4
MPHI_MINFS_WPTR_MSB 19
SMI_CS_TXW_BITS 26:26
USB_HCFG_LS_SUPP_CLR 0xfffffffb
SCALER_DISPECTRL 0x7e40000c:RW
CM_V3DDIV_DIV_LSB 4
SD_DQRCRC8_WIDTH 32
PWM_DMAC_ENAB_LSB 31
PCM_CS_A_TXD_LSB 19
MS_IREQ_1_RESET 0000000000
DMA13_TI_SRC_DREQ_CLR 0xfffffbff
CAM0_CAMDBG3_RESET 0000000000
CAM1_CAMCAP1_WIDTH 32
SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_CLR 0xffffffcf
GP_EDS0 0x7e200040:RW
CM_TD0CTL_BUSYD_SET 0x00000100
SD_MR_TIMEOUT_BITS 30:30
DSI0_TA_TO_CNT_WIDTH 32
USB_GHWCFG2_HSPHY_INTERFACE_MSB 7
GP_HEN1_HENn32_LSB 0
L1_L1_SANDBOX_START4_START_ADDR_MSB 29
USB_PCGCR_STOP_PCLK_BITS 0:0
SCALER_DISPCTRL_DSP2_IRQ_CTRL_CLR 0xffffe7ff
USB_HCSPLT0_HUB_ADDR_LSB 7
HDMI_RAM_PACKET_7_6_RESET 0000000000
V3D_PCTR15_MASK 0xffffffff
DMA0_NEXTCONBK_WIDTH 32
DMA4_TI_NO_WIDE_BURSTS_LSB 26
DMA2_CS_RESET_LSB 31
SCALER_DISPCTRL_HVS_EN_CLR 0x7fffffff
UART_EN_WIDTH 2
A2W_XOSC_PWR 0x7e102490:RW
PCM_TXC_A_CH2WID_LSB 0
DSI1_INT_EN_MASK 0x0fffffff
DMA_INT_STATUS_INT9_LSB 9
A2W_PLLA_DIG3_RESET 0x00000004
A2W_PLLB_DIG1R_WIDTH 24
CM_AVEOCTL_KILL_SET 0x00000020
DMA3_TI_SRC_INC_BITS 8:8
ASB_CPR_CTRL_RCOUNT_BITS 13:4
MS_SEMA_4_MASK_LSB 0
PM_PADS3_SLEW_LSB 4
CM_CKSM_FRCE_BITS 15:8
SYSAC_UC_ARBITER_CONTROL_ALGORITHM_SET 0x000000c0
CM_V3DDIV_WIDTH 16
CM_EVENT_FLOSSA_MSB 14
USB_DIEPDMAB3 0x7e980978:RW
USB_DIEPDMAB4 0x7e980998:RW
USB_DIEPDMAB5 0x7e9809b8:RW
USB_DIEPDMAB6 0x7e9809d8:RW
USB_DIEPDMAB7 0x7e9809f8:RW
USB_DIEPDMAB8 0x7e980a18:RW
USB_DIEPDMAB9 0x7e980a38:RW
SD_RWC_LASTCNT_SET 0x001f0000
USB_GHWCFG4_NUM_CRL_EPS_LSB 16
CM_TIMERCTL_BUSYD_MSB 8
CM_DSI0ECTL_BUSY_MSB 7
A2W_PLLB_CTRLR_WIDTH 18
DMA13_DEBUG_VERSION_CLR 0xf1ffffff
CM_SMIDIV_DIV_MSB 15
L2_CONT_OFF_l2_flush_mode_BITS 4:3
APERF0_BW1_ATRANS_WIDTH 32
A2W_PLLC_FRAC_FRAC_BITS 19:0
SCALER_DISPCTRL_DSP2_PANIC_SET 0x30000000
SD_PHYC_CRC_CLR_RESET 0x0
GP_PUDCLK0_PUDCLKn0_MSB 31
A2W_PLLC_CORE2_WIDTH 10
USB_HCINT0_DATA_TGL_ERR_SET 0x00000400
CMI_CAM0_RX0SRC_MSB 3
DMA5_TI_DEST_DREQ_BITS 6:6
CM_DFTCTL_WIDTH 10
GP_FSEL2_FSEL28_CLR 0xf8ffffff
CCP2TX_TS_ARE_MSB 2
A2W_PLLA_ANA3R_MASK 0x00ffffff
HDMI_HOTPLUG_RESET 0000000000
A2W_PLLD_DIG1_WIDTH 24
HDMI_DETECTED_HORZB_MANUAL_HBP_CLR 0xc00fffff
CM_EMMCCTL_BUSYD_BITS 8:8
L1_D0_RD_MISSES_WIDTH 0
CM_PULSEDIV_WIDTH 24
HDMI_BASE 0x7e902000
I2C_SPI_SLV_ICR_RXIC_MSB 0
I2C_SPI_SLV_RSR_TXDMAPREQ_LSB 2
MPHI_C0INDS_DISCARD_SET 0x80000000
USB_DOEPINT7_WIDTH 32
DMA6_TI_SRC_DREQ_BITS 10:10
A2W_PLLD_ANA_VCOR 0x7e102e50:RW
CM_ARMCTL_BUSY_CLR 0xffffff7f
FPGA_STATUS0_SD_CD_SET 0x00000020
L2_WR_HITS 0x7ee01108:RO
SYSAC_HOST_PRIORITY_PRIORITY_CLR 0xfffffff0
APERF0_BW1_RPEND_RESET 0000000000
GP_LEN0_LENn0_LSB 0
PM_DUMMY_MASK 0x00000001
V3D_PCTR5_WIDTH 32
DMA_ENABLE_EN5_MSB 5
USB_DOEPCTL0_NAK_STS_BITS 17:17
L1_IC0_CONTROL_BP_DISABLE_CLR 0xfffffff7
A2W_SMPS_CTLC1R_MASK 0x00ffffff
SMI_DSW0_WFORMAT_BITS 23:23
AUX_MU_STAT_TX_FULL 0x00000020
A2W_PLLA_CORE_BYPEN_SET 0x00000200
HDMI_DETECTED_VERTA1_MANUAL_VFP1_BITS 19:13
DMA1_CS_ABORT_SET 0x40000000
HD_MAI_CTL_PAREN_CLR 0xfffffeff
USB_HCINT5_WIDTH 32
CM_CAM1CTL_SRC_LSB 0
PCM_TXC_A_CH2WEX_SET 0x00008000
DMA5_DEBUG_FIFO_ERROR_MSB 1
L1_L1_SANDBOX_START5_CTRL_SET 0x00000001
USB_GRSTCTL_AHB_IDLE_CLR 0x7fffffff
CM_GP2CTL_KILL_CLR 0xffffffdf
CM_CKSM_STEP_BITS 21:21
HDMI_READ_POINTERS_DRFT_RD_ADDR_MSB 7
A2W_PLLA_FRAC_FRAC_CLR 0xfff00000
DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
SLIM_DCC_STAT(n) MACRO
APERF0_BW1_ATRANS_MASK 0xffffffff
DMA15_SOURCE_AD_S_ADDR_SET 0xffffffff
AVE_OUT_CTRL_ERROR_IRQ_EN_CLR 0xfffffffe
A2W_XOSC_CTRL_RESET 0000000000
CM_GP2CTL_ENAB_BITS 4:4
CM_GNRICCTL_WIDTH 20
INTERRUPT_HARDINT_NUM 64
PWM_STA_GAPO4_SET 0x00000080
I2C_SPI_SLV_CR_ENCTRL_LSB 6
I2C_SPI_SLV_IFLS_RXIFPSEL_MSB 11
MS_IREQ_0_IREQ_0_LSB 0
USB_GUSBCFG_TERM_SEL_DL_PULSE_RESET 0x0
GP_FSEL1_FSEL17_SET 0x00e00000
A2W_PLLD_ANA_VCOR_MASK 0x00000001
USB_HCINT1_WIDTH 32
APERF1_BW0_CTRL_BUS_RESET 0x0
CM_LOCK_FLOCKA_MSB 8
SD_VIN 0x7ee00088:RW
AVE_IN_CTRL_PRIORITY_LIMIT_LSB 24
CM_GP2CTL_SRC_BITS 3:0
SMI_DSR1_RPACE_SET 0x00007f00
SD_DQRCRC2_RISE_RESET 0x0
SYSAC_HOST_PRIORITY_RESET 0000000000
APERF1_BW0_CTRL_ID_EN_RESET 0x0
A2W_PLLC_ANA_SCTL_RESET 0000000000
USB_HPTXSTS_WIDTH 32
DMA5_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
USB_GRXSTSP_DEV_DPID_MSB 16
L2_CONT_OFF_MASK 0x00ff0c3f
CM_HSMCTL_FRAC_MSB 9
PM_PADS2_HYST_CLR 0xfffffff7
SMI_A_MASK 0x0000033f
PM_USB_CTRLEN_MSB 0
SH_DATA_WIDTH 32
DMA10_CS_INT_LSB 2
DMA10_DEBUG_LITE_CLR 0xefffffff
DMA9_TXFR_LEN_XLENGTH_SET 0x0000ffff
CM_BURSTCTL_KILL_SET 0x00000020
PWM_CTL_POLA3_MSB 20
EMMC_CONTROL1_DATA_TOUNIT_CLR 0xfff0ffff
AVE_OUT_OFFSET_RED_OFFSET_MSB 23
USB_GRSTCTL_MASK 0xc00007ff
MPHI_HSINDDB_TENDINT_MSB 29
NU_BASE 0x7e008000
HD_HDM_CTL_PDSTBY_SET 0x00000030
USB_HFNUM_NUM_MSB 15
CM_INTEN_GAIND_SET 0x00000008
USB_DIEPDMA12_WIDTH 32
MPHI_INTSTAT_HSTEND_MSB 31
AVE_IN_STATUS_BUF_NOT_SERV_CLR 0xfffffff7
CM_PLLA_LOADCORE_CLR 0xffffffef
DMA_INT_STATUS_INT2_CLR 0xfffffffb
L1_L1_SANDBOX_START1_CTRL_SET 0x00000001
AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_LSB 0
SLIM_DCC4_PA0_RESET 0000000000
CM_UARTCTL_FRAC_SET 0x00000200
HDMI_DETECTED_VERTB1 0x7e90214c:RW
AVE_OUT_CTRL_INTERLEAVE_LSB 12
SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_CLR 0xffff00ff
EMMC_STATUS_WRITE_TRANSFER_MSB 8
SYSAC_SRC_ARBITER_CONTROL_DELAY_RESET 0x0
HDMI_RAM_PACKET_3_8 0x7e90248c:RW
USB_GINTMSK_PRT_INT_SET 0x01000000
TS_TSENSCTL_EN_INT_BITS 5:5
MPHI_INTSTAT_RX0TEND_CLR 0xffffffef
CM_PCMCTL_BUSYD_CLR 0xfffffeff
A2W_PLLD_PER_DIV_CLR 0xffffff00
CAM1_CAMIBLS 0x7e801118:RW
MPHI_HSINDS_VALID_RESET 0x0
DMA12_TI_INTEN_LSB 0
SYSAC_PERI_ARBITER_CONTROL_DELAY_RESET 0x0
SPI_CS_RXR_BITS 19:19
DMA1_DEBUG_DMA_STATE_CLR 0xfe00ffff
USB_GINTMSK_INCOMPL_ISO_OUT_RESET 0x0
DMA15_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
HD_CSC_CTL_COLORD_CLR 0xffffff1f
SCALER_DISPCTRL_VSCL_DIS_CLR 0x3fffffff
APERF1_BW1_CTRL_RESET_MSB 31
DMA9_CS_INT_LSB 2
APERF1_BW2_AMAX 0x7ee080cc:RO
CM_PLLA_ANARST_LSB 8
DMA0_CS_ACTIVE_CLR 0xfffffffe
DMA9_TI_SRC_IGNORE_LSB 11
DMA5_CS_PAUSED_LSB 4
GP_FSEL0_FSEL03_LSB 9
HDMI_AN_INFLUENCE_2_WIDTH 32
I2C1_S_RESET 0x00000050
EMMC_CMDTM_CMD_RSPNS_TYPE_MSB 17
CCP2TX_TAC_DLAC_BITS 15:8
PM_AVS_STAT_WIDTH 5
HDMI_RAM_PACKET_5_7_RESET 0000000000
DMA13_CS_DISDEBUG_LSB 29
EMMC_EXRDFIFO_EN_ENABLE_CLR 0xfffffffe
SD_CS_RDH_IDLE_BITS 16:16
USB_DIEPCTL11_WIDTH 32
A2W_PLLB_ARM_CHENB_MSB 8
EMMC_HWCAP1_DDR50_MSB 2
HDMI_RAM_PACKET_11_8_WIDTH 32
SYSAC_JPEG_PRIORITY_WIDTH 8
USB_HCINT7_MASK 0xffffffff
DMA12_CONBLK_AD_SCB_ADDR_MSB 31
CM_TECCTL_KILL_MSB 5
SD_MR_RW_RESET 0x0
PM_RSTS_HADSRF_MSB 9
UART_LSR_RFE_MSB 7
DMA3_TI_DEST_DREQ_SET 0x00000040
SMI_CS_PAD_LSB 6
SYSAC_UC_ARBITER_CONTROL_DELAY_MSB 3
A2W_PLLA_PER 0x7e102500:RW
I2C_SPI_SLV_RIS_MASK 0x0000000f
CM_PULSECTL_KILL_SET 0x00000020
DMA0_TI_SRC_INC_CLR 0xfffffeff
DMA8_TI_INTEN_SET 0x00000001
DMA_ENABLE_EN1_LSB 1
EMMC_IRPT_EN_OEM_ERR_SET 0xc0000000
SMI_DSR3_MODE68_MSB 23
DMA_INT_STATUS_INT4_MSB 4
JP_CBA 0x7e005010:RW
SD_CS_CLKOFF_CLR 0xffffbfff
DMA9_CONBLK_AD 0x7e007904:RW
DSI0_HS_DLT5_MASK 0x000003fc
ASB_V3D_S_CTRL_CLR_ACK_MSB 1
PM_GNRIC_POWUP_MSB 0
DMA_ENABLE_EN14_MSB 14
JICST_MARKER (1 << 18)
PM_GRAFX_MASK 0x007f107f
SD_DQLCRC0 0x7ee0014c:RO
SD_DQLCRC1 0x7ee00150:RO
SD_DQLCRC2 0x7ee00154:RO
SD_DQLCRC3 0x7ee00158:RO
SD_DQLCRC4 0x7ee0015c:RO
SD_DQLCRC5 0x7ee00160:RO
SD_DQLCRC6 0x7ee00164:RO
SD_DQLCRC7 0x7ee00168:RO
SD_DQLCRC8 0x7ee0016c:RO
ARM_C1_REQSTOP 0x00000200
PWM_CTL_MSEN1_MSB 7
USB_DAINT_IN_EP_INT_LSB 0
DMA11_DEBUG_RESET 0000000000
USB_GOTGCTL_DBNC_TIME_RESET 0x0
A2W_HDMI_CTL3R_WIDTH 24
A2W_PLLH_DIG2R_WIDTH 24
HDMI_RAM_PACKET_13_5_RESET 0000000000
CAM0_CAMDBG1_WIDTH 32
A2W_XOSC_CTRL_PLLDOK_SET 0x00020000
DMA9_TI_SRC_INC_SET 0x00000100
DMA_ENABLE_EN10_BITS 10:10
DSI0_HS_DLT3 0x7e209050:RW
USB_DOEPINT10 0x7e980c48:RW
DSI0_CTRL_CTRL1_MSB 1
USB_DOEPINT12 0x7e980c88:RW
USB_DOEPINT13 0x7e980ca8:RW
USB_DOEPINT14 0x7e980cc8:RW
HDMI_HORZB_MANUAL_HBP_LSB 20
A2W_PLLH_ANA0_RESET 0x00d80000
FPGA_CTRL0_DIS_CTL2_SET 0x00000004
HDMI_VERTB0_MANUAL_VBP0_SET 0x00000100
A2W_PLLH_FRAC_FRAC_LSB 0
CM_EVENT 0x7e101118:RW
TE0_VSWIDTH TECTL_BASE_ADDRESS + 0x08:RW
PM_AVS_RSTDR_PERI_A_CLR 0xfffffffe
DMA_INT_STATUS_INT4_BITS 4:4
CM_AVEODIV_DIV_MSB 15
DMA12_TI_SRC_IGNORE_LSB 11
I2C_SPI_SLV_MIS_TXMIS_SET 0x00000002
TB_JTB_CONFIG_ENABLE_MSB 11
USB_GUSBCFG_WIDTH 32
MPHI_C0INDS_VALID_MSB 30
EMMC_INTERRUPT_DATA_DONE_BITS 1:1
A2W_PLLA_DIG1_WIDTH 24
UNICAM_CLK(x) MACRO
MPHI_INTSTAT_HSDCFOFLW_LSB 27
ST_C2_MASK 0xffffffff
GP_SEN1_SEN_LSB 0
CM_TD1CTL_BUSY_BITS 7:7
HDMI_HOTPLUG_INT_MASK 0x00000007
UNICAM_CLT(x) MACRO
CM_TCNTCNT_CNT_SET 0x00ffffff
DMA9_BASE 0x7e007900
GROPCTR_TU1_CACHE_MISSES 0x1C
DMA3_TXFR_LEN_XLENGTH_LSB 0
TXP_CTRL_ABORT_MSB 14
USB_HPRT_SUSP_BITS 7:7
SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_MSB 1
TS_TSENSSTAT_VALID_MSB 10
USB_DIEPTSIZ0_RX_DPID_SET 0x60000000
AUX_SPI_CNTL1_DONEIRQ 0x00000080
EMMC_INTERRUPT_CARD_IN_LSB 6
DMA1_TI_SRC_IGNORE_SET 0x00000800
DMA14_CS_ERROR_MSB 8
SYSAC_SRC_ARBITER_CONTROL_LIMIT_SET 0x00000003
EMMC_FORCE_IRPT_ADMA_ERR_SET 0x02000000
USB_GHWCFG2_ARCHITECTURE_LSB 3
EMMC_INTERRUPT_CARD_LSB 8
APERF1_BW1_CTRL_BUS_SET 0x0000001f
PWM_CTL_PWEN4_LSB 24
A2W_PLLA_ANA0_MASK 0x00ffffff
VPU_ARB_CTRL_UC_THRESHOLD_RESET 0x0
DMA2_STRIDE_S_STRIDE_SET 0x0000ffff
APERF0_BW2_ATRANS_RESET 0000000000
A2W_SMPS_CTLB0 0x7e1020b0:RW
SPI_CLK_MASK 0x0000ffff
CM_UARTCTL_MASK 0x000003bf
DMA10_DEBUG_FIFO_ERROR_SET 0x00000002
MPHI_INTSTAT_RX1MEND_BITS 8:8
V3D_IDENT0_MASK 0xffffffff
EMMC_CONTROL1_SRST_CMD_MSB 25
A2W_PLLD_DSI0R 0x7e102b40:RW
CM_HSMCTL_ENAB_LSB 4
DMA8_CS_PRIORITY_MSB 19
JC0BA 0x7e005000 + 0x4C:RW
DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
IS_ALIAS_PERIPHERAL(x) MACRO
HDMI_READ_POINTERS_DRFT_ALMOST_FULL_SET 0x00200000
USB_DOEPTSIZ0_XFERSIZE_CLR 0xfff80000
CAM1_CAMIHWIN_RESET 0000000000
A2W_PLLB_ARM_BYPEN_CLR 0xfffffdff
IC0_MASK4_RESET 0000000000
EMMC_IRPT_EN_INT_A_CLR 0xfffffdff
HD_HDM_CTL_CECOVR_RESET 0x0
DMA14_DEBUG_DMA_STATE_MSB 24
USB_GUSBCFG_IND_COMP_BITS 23:23
CM_CKSM_WIDTH 22
USB_GI2CCTL_REG_ADDR_CLR 0xffff00ff
DMA7_CS_MASK 0xf0ff017f
AVE_IN_CTRL_LINE_IRQ_EN_MSB 4
USB_DIEPCTL8_WIDTH 32
TB_JTB_TDI_WIDTH 32
APERF1_BW0_CTRL_ID_EN_MSB 29
A2W_SMPS_CTLC0R_WIDTH 24
A2W_PLLD_DSI1R 0x7e102e40:RW
MS_SEMA_14_MASK_BITS 0:0
DMA3_CS_PRIORITY_SET 0x000f0000
A2W_PLLB_ARM_DIV_MSB 7
SD_DQLCRC0_MASK 0xffffffff
CCP2TX_TIC_TEIE_LSB 1
A2W_PLLD_DIG3 0x7e10204c:RW
AVE_IN_CHAR_CTRL_RESET 0000000000
SMI_DSR0_RPACEALL_CLR 0xffff7fff
MPHI_C1INDCF_LENERR_SET 0x40000000
A2W_PLLC_ANA_STAT_DATA_BITS 11:0
MPHI_OUTDDA_START_RESET 0x0
PM_PADS6_POWOK_CLR 0xffffffdf
GR_UNIFORM_SIZE 0x00001000
HDMI_FIFO_CTL_ON_VB_DONE_MSB 15
PM_GRAFX_POWUP_SET 0x00000001
IC1_VADDR_RESET 0000000000
SMI_DSW3_WDREQ_MSB 7
SMI_CS_WRITE_MSB 5
EMMC_HWCAP0_V3_0_LSB 25
SD_SF_MDLL_CAL_SET 0x000001ff
AVE_IN_STATUS_MAX_HIT_MSB 16
USB_GOTGCTL_A_SES_VLD_MSB 18
USB_GINTMSK_USB_SUSP_SET 0x00000800
EMMC_INTERRUPT_CARD_OUT_MSB 7
TXP_CTRL_LINEAR_UTILE_BITS 7:7
SH_CMD_NEW_FLAG_SET 0x00008000
DMA14_TI_SRC_DREQ_CLR 0xfffffbff
A2W_PLLB_FRAC 0x7e1022e0:RW
DSI1_TA_TO_CNT_WIDTH 32
CM_PLLTCNT0_MASK 0x00ffffff
USB_GRSTCTL_FRM_CNTR_RST_RESET 0x0
DMA0_DEST_AD 0x7e007010:RO
DMA_ENABLE_EN14_BITS 14:14
CM_DSI0PDIV_DIV_LSB 12
PM_IMAGE_CFG_LSB 16
PWM_CTL_CLRF1_SET 0x00000040
MPHI_HSINDDB_HANDLE_LSB 20
EMMC_CONTROL2_ACCRC_ERR_MSB 2
APERF0_BW0_CTRL_BUS_RESET 0x0
CM_DSI1EDIV_DIV_SET 0x0000fff0
DMA2_TI_SRC_INC_MSB 8
CDP_BASE 0x1C00E000
PM_PXLDO_WIDTH 18
DMA6_CS_INT_LSB 2
TXP_CTRL_EI_MSB 2
SD_DQLCRC12_FALL_SET 0x0000ffff
SD_RTC_RESET 0000000000
MPHI_C0INDS_DISCARD_MSB 31
EMMC_IRPT_EN_BOOTACK_LSB 13
AVE_OUT_CTRL_INVERT_DSYNC_CLR 0xfffbffff
SMI_DSW2_WDREQ_LSB 7
A2W_PLLH_ANA_SCTL_UPDATE_SET 0x00000008
CM_TD0CTL_MASK 0x00001bff
EMMC_IRPT_EN_CMD_DONE_BITS 0:0
RUN_ARBITER_CTRL_BASE_ADDRESS 0xffffffff:RW
SD_SD_T_RAS_RESET 0xe
PM_CAM1_LDOLPEN_LSB 1
CM_TD0DIV_DIV_BITS 23:0
PWM_CTL_SBIT3_SET 0x00080000
PM_DFT_WIDTH 2
PCM_INTEN_A_TXW_CLR 0xfffffffe
SLIM_DCC8_PA0 0x7e210300:RW
SLIM_DCC8_PA1 0x7e210304:RW
A2W_PLLC_CORE0_BYPEN_SET 0x00000200
AVE_IN_CURRENT_ADDRESS_CUR_ADDR_BITS 31:0
SLIM_DCC3_PROT 0x7e210270:RW
DMA5_CS 0x7e007500:RW
GP_FSEL4_FSEL42_MSB 8
A2W_PLLD_CTRL_NDIV_MSB 9
CM_OSCFREQI_INT_MSB 7
DMA10_CS_RESET_BITS 31:31
L2_CONT_OFF_l2_no_wr_allocate_SET 0x00000002
USB_GHWCFG2_MODE_BITS 2:0
DMA0_TI_BURST_LENGTH_CLR 0xffff0fff
JNSB 0x7e005000 + 0x1C:RW
GP_FSEL6_FSEL63_CLR 0xfffff1ff
GP_PUDCLK2_PUDCLKn64_SET 0x0000003f
USB_DPTXFSIZ1_WIDTH 32
CM_PCMCTL_BUSY_LSB 7
USB_HCINT0_AHB_ERR_RESET 0x0
CMI_CAM1_RX1SRC_BITS 5:4
MS_SEMA_13_MASK_MSB 0
EMMC_IRPT_MASK_DTO_ERR_BITS 20:20
CM_PERIADIV_WIDTH 13
DMA15_CS_PRIORITY_CLR 0xfff0ffff
CPG_BASE 0x7e211000
EMMC_CMDTM_CMD_INDEX_MSB 29
HDMI_DETECTED_HORZA_MANUAL_VPOL_LSB 14
AVE_OUT_CTRL_INTERLEAVE_SET 0x00001000
L1_D1_RD_MISSES_WIDTH 0
DMA15_CS_ACTIVE_LSB 0
USB_GUSBCFG_USB_TRD_TIM_RESET 0x0
GP_SEN1_SEN_SET 0x003fffff
ST_C3_RESET 0000000000
SD_DQRCRC0_RISE_CLR 0x0000ffff
APERF1_BW0_AMAX_MASK 0x00ffffff
USB_GPVNDCTL_NEW_REG_REQ_BITS 25:25
USB_DCTL_SFT_DISCON_LSB 1
SMI_DCS_MASK 0x0000000f
SLIM_EA0 0x7e210010:RW
SLIM_EA1 0x7e210014:RW
APERF1_BW1_RPEND_RESET 0000000000
HDMI_TX_PHY_TX_PHY_RESET_CTL_MASK 0xffffffff
AVE_OUT_STATUS_PXL_FORMAT_ERROR_CLR 0xfffffffe
HDMI_CP_INTEGRITY_CFG_RESET 0x00001000
PCM_MODE_A_FTXP_LSB 24
MS_MBOX_4_WIDTH 32
USB_DAINT_MASK 0xffffffff
A2W_PLLD_ANA_KAIP_MASK 0x0000077f
PM_XOSC_USESEC_CLR 0xfffffffe
AVE_IN_BUF0_ADDRESS_WIDTH 32
DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
SMI_DSR2_FSETUP_MSB 22
USB_DFIFO0_MASK 0xffffffff
CM_PLLC_MASK 0x000003ff
ARM_3_SEMCLRDBG (0x7E00B000 +0xB00)+0xE0:RW
SD_DQRCRC13_FALL_RESET 0x0
GP_FSEL5_FSEL52_SET 0x000001c0
APERF1_BW1_ATRANS_MASK 0xffffffff
CCP2TX_TTC_LEC_MSB 11
EMMC_IRPT_EN_DCRC_ERR_CLR 0xffdfffff
SH_HCFG_BUSY_IRPT_EN_MSB 10
USB_HFNUM_MASK 0xffffffff
AVE_IN_CTRL_HIGH_PRIORITY_MSB 23
DMA14_DEBUG_VERSION_BITS 27:25
CM_TDCLKEN_PLLABYP_CLR 0xfffffffe
ASB_ISP_M_CTRL_FULL_SET 0x00000008
IC0_MASK7_MASK 0x77777777
SD_CS_ASHDN_T_RESET 0xf
USB_HCCHAR6_MASK 0xffffffff
CM_TD1CTL_KILL_LSB 5
PM_RSTC_WRCFG_MSB 5
DMA7_TI_DEST_DREQ_MSB 6
DMA6_CS_DISDEBUG_MSB 29
HDMI_RAM_PACKET_13_3_WIDTH 32
DMA3_TI_WIDTH 27
PM_IMAGE_MEMREP_BITS 3:3
SLIM_DMA_DC8_RESET 0000000000
DSI1_TST_MON_WIDTH 32
UART_MSR_DDCD_SET 0x00000008
FPGA_STATUS0_HW_ID_LSB 0
CM_PLLH_LOADRCAL_CLR 0xfffffffb
HD_VID_CTL_ERROR_BITS 26:25
IC1_FORCE1_SET 0x7e00284c:RW
SMI_CS_INTD_RESET 0x0
PIARBCTL_BASE 0x7e80a000
APERF1_GEN_CTRL_RESET_LSB 1
MPHI_C0INDS_DISCARD_RESET 0x0
DMA9_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
SPI_CS_CSPOL_MSB 6
A2W_PLLD_DSI1_CHENB_BITS 8:8
USB_GOTGINT_SES_REQ_SUC_STS_CHG_CLR 0xfffffeff
HDMI_AN_INFLUENCE_1 0x7e902020:RW
HDMI_AN_INFLUENCE_2 0x7e902024:RW
A2W_XOSC_CTRL_HDMIEN_LSB 1
PCM_MODE_A_FLEN_SET 0x000ffc00
DMA15_TI_SRC_WIDTH_LSB 9
PCM_CS_A_RXSEX_MSB 23
USB_HCCHAR0_MPS_MSB 10
A2W_SMPS_A_GAINR_RESET 0000000000
DPHY_CSR_BYTE3_SLAVE_DLL_OFFSET 0x7ee07028:RW
SLIM_DCC4_STAT_MASK 0xc0ff00c7
INTERRUPT_CRYPTO ((64) + 34 )
MPHI_INTSTAT_RX0MEND_MSB 0
GP_EDS1_EDSn32_CLR 0x00000000
CM_V3DCTL_FRAC_BITS 9:9
CM_LOCK_LOCKH_LSB 4
CM_EVENT_A2WDONE_MSB 20
SD_DQLCRC4_FALL_MSB 15
MS_MBOX_3_MBOX_CLR 0x00000000
DMA6_TI_INTEN_LSB 0
CAM1_CAMIDCD_RESET 0000000000
USB_GNPTXSTS_TX_Q_SPC_AVAIL_SET 0x00ff0000
SD_MR_RW_SET 0x10000000
CAM0_CAMIHSTA_WIDTH 32
CCP2TX_TS_TFP_LSB 6
SD_SECEND3_ADDR_LS_CLR 0xffffe000
PCM_GRAY_FLUSHED_CLR 0xffff03ff
SMI_CS_INTT_MSB 10
A2W_PLLC_PER_CHENB_BITS 8:8
AVE_OUT_Y_COEFF_GREEN_COEFF_MSB 19
SYSAC_USB_PRIORITY_PRIORITY_CLR 0xfffffff0
HDMI_RAM_PACKET_13_3_MASK 0xffffffff
PWM_CTL_SBIT2_MSB 11
A2W_PLLD_ANA_STAT_DATA_LSB 0
I2C_SPI_SLV_FR_TXBUSY_MSB 0
HDMI_RAM_PACKET_11_2_RESET 0000000000
PCM_DREQ_A_RX_PANIC_BITS 22:16
HDMI_FIFO_CTL_USE_EMPTY_BITS 13:13
PCM_RXC_A_CH2POS_MSB 13
DMA8_TI_BURST_LENGTH_CLR 0xffff0fff
I2C_SPI_SLV_IFLS_RXIFLSEL_SET 0x00000038
SYSAC_SRC_ARBITER_CONTROL_MASK 0x0000ffff
CM_PCMCTL_BUSYD_MSB 8
A2W_PLLD_CTRL_PRSTN_SET 0x00020000
HD_MAI_CTL_CHNUM_SET 0x000000f0
I2C_SPI_SLV_RSR_TXDMABREQ_CLR 0xfffffff7
CAM0_CAMIPIPE_MASK 0xffffffff
DMA0_TI_TDMODE_LSB 1
CM_PLLA_LOADCORE_SET 0x00000010
PCM_CS_A_RXCLR_LSB 4
SD_LAC_WIDTH 28
FPGA_MB_XPERI_BUILD_NUM_WIDTH 32
USB_DOEPCTL8_MASK 0xffffffff
V3D_DBSDR1_MASK 0xffffffff
IC0_MASK2_WIDTH 31
USB_HCCHAR1_WIDTH 32
A2W_SMPS_L_SCA_ANA_MSB 11
DMA9_DEBUG_FIFO_ERROR_BITS 1:1
USB_DCFG_NZ_STS_OUT_HSHK_BITS 2:2
DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
DMA11_TI_SRC_IGNORE_MSB 11
DMA1_TI_DEST_INC_LSB 4
DMA13_DEBUG_DMA_ID_BITS 15:8
CM_SMIDIV_RESET 0000000000
SD_DQLCRC5_RISE_CLR 0x0000ffff
A2W_SMPS_L_MULTI_RESET 0000000000
PM_AVS_EVENT_ALERT_ARM_P_LSB 4
SPI_DLEN_RESET 0000000000
DMA2_SOURCE_AD_S_ADDR_SET 0xffffffff
DMA2_CS_ERROR_CLR 0xfffffeff
GP_FSEL1_FSEL18_LSB 24
SD_DQRCRC0_WIDTH 32
HDMI_RAM_PACKET_8_0_MASK 0xffffffff
CM_PCMCTL_KILL_MSB 5
DMA4_CS_PAUSED_MSB 4
DMA3_CS_INT_LSB 2
DMA3_TI_DEST_IGNORE_MSB 7
TB_BOOT_STATUS_CPRMAN_PROGRAMMED_BITS 0:0
USB_DIEPTSIZ0_PKT_CNT_RESET 0x0
MPHI_OUTDS_WORDS_BITS 20:0
DMA11_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
A2W_PLLA_ANA_SSCL_LIMIT_LSB 0
USB_GRXSTSP_DEV_FN_RESET 0x0
ASB_H264_S_CTRL_RCOUNT_LSB 4
DSI1_PHY_AFEC0_RESET 0000000000
USB_GHWCFG2_EN_PERIO_HOST_MSB 18
SMI_DSR3_MODE68_LSB 23
EMMC_CONTROL2_ACNOX_ERR_SET 0x00000001
DPHY_CSR_DQ_PHY_READ_STATUS 0x7ee07068:RW
SYSAC_TRANS_PRIORITY_RESET 0000000000
CM_DSI1PCTL_ENAB_BITS 4:4
SD_DQRCRC6_FALL_MSB 15
I2C_SPI_SLV_SLV 0x7e214008:RW
PM_SPAREW_SPARE_BITS 23:0
HDMI_13_AUDIO_STATUS_1_WIDTH 1
DMA_INT_STATUS_INT6_SET 0x00000040
APERF0_BW2_AMAX 0x7e0098cc:RO
PM_CAM0_LDOHPEN_LSB 2
MS_VPUSEMA_0_VPUSEMA_0_BITS 0:0
USB_GOTGINT_HST_NEG_SUC_STS_CHG_RESET 0x0
SLIM_MC_IN_STAT 0x7e210104:RW
PM_PADS2_DRIVE_MSB 2
DMA15_TI_DEST_IGNORE_MSB 7
PM_DSI1_RESET 0000000000
USB_DOEPINT0_TIMEOUT_SET 0x00000008
GROPCTR_FBC_CZ_FETCH_STALLS 0x28
SMI_L_MASK 0xffffffff
CAM0_CAMDBCTL_MASK 0xffffffff
USB_GINTMSK_NP_TXF_EMP_CLR 0xffffffdf
A2W_PLLH_ANA_KAIP_KA_MSB 10
EMMC_CONTROL2_ACCRC_ERR_BITS 2:2
UART_RBRTHRDLL 0x7e201000:RW
GP_CLR1_CLRn32_SET 0xffffffff
MS_SEMA_29_RESET 0000000000
SPI_CLK_CDIV_LSB 0
A2W_PLLB_ANA_SCTL_RESET_CLR 0xffffffef
SD_DQRCRC15_FALL_LSB 0
SD_VIN_SPLIT_CLR 0xfffdffff
CM_OTPCTL_KILL_BITS 5:5
DMA3_DEBUG_READ_ERROR_CLR 0xfffffffb
A2W_PLLB_MULTI 0x7e102fe0:RW
SPI_LTOH 0x7e204010:RW
USB_HCDMA6_MASK 0xffffffff
EMMC_CONTROL0_WAKE_ONREM_EN_MSB 26
A2W_PLLD_ANA_STAT_RESET 0000000000
USB_GRSTCTL_C_SFT_RST_LSB 0
SLIM_DCC9_CON_RESET 0000000000
CM_ISPCTL_KILL_MSB 5
USB_DOEPCTL0_SET_ODD_FR_RESET 0x0
DMA10_NEXTCONBK_WIDTH 32
AUX_MU_BDMS_REG (0x7E215000 +0x044)
DMA13_NEXTCONBK_ADDR_MSB 31
PWMCTL_MSEN1 7
PWMCTL_MSEN2 15
DMA6_CS_PANIC_PRIORITY_CLR 0xff0fffff
PWMCTL_MSEN4 31
L2_IN_FLIGHT 0x7ee01114:RO
USB_DSTS_ERRTIC_ERR_SET 0x00000008
EMMC_IRPT_MASK_INT_C_SET 0x00000800
CM_DSI0HSCK_SELPLLD_CLR 0xfffffffe
DMA1_TI_DEST_INC_BITS 4:4
APERF0_BW2_CTRL_ID_EN_MSB 29
HD_MAI_CTL_WHOLSMP_CLR 0xffffefff
SH_HCFG_WIDE_EXT_BUS_MSB 2
PM_PROC_POWOK_LSB 1
DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
DMA11_DEST_AD_D_ADDR_MSB 31
MS_SEMA_26_MASK_LSB 0
SMI_DSR2_RESET 0x0101000c
A2W_PLLD_ANA_SSCS_RESET 0000000000
A2W_SMPS_CTLA0_MASK 0x00ffffff
CM_LOCK_LOCKA_CLR 0xfffffffe
SD_DQLCRC15_FALL_CLR 0xffff0000
HDCP_KEY_KY1_MASK 0x00ffffff
A2W_PLLC_ANA3R_WIDTH 24
SD_DQRCRC7_RISE_CLR 0x0000ffff
GROPCTR_FEINVALIDPIXELS 0x08
A2W_PLLB_ANA0_RESET 0000000000
UART_LCR_MASK 0x000000ff
AUX_SPI1_IO_REG (0x7E215000 +0x0E0)
SD_DQRCRC10_FALL_RESET 0x0
SMI_CS_DONE_RESET 0x0
CM_DFTDIV 0x7e10116c:RW
EMMC_IRPT_EN_DTO_ERR_MSB 20
USB_GAHBCFG_GLBL_INTR_MSK_SET 0x00000001
DMA4_CS_ACTIVE_SET 0x00000001
DMA6_TI_DEST_WIDTH_LSB 5
HDMI_FIFO_CTL_USE_EMPTY_CLR 0xffffdfff
SD_SF_PGEHLD_T_BITS 28:19
HD_VID_CTL_FULRGB_SET 0x00200000
HDMI_VERTA0_MANUAL_VSP0_LSB 20
PM_RSTS_HADDRH_MSB 2
PM_PADS0_POWOK_CLR 0xffffffdf
USB_DOEPCTL0_SNP_RESET 0x0
ST_C1_WIDTH 32
SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_SET 0x000000c0
SCALER_DISPSTAT_DMA_ERR_BIT2_MSB 31
SMI_CS_CLEAR_CLR 0xffffffef
SPI_DLEN_LEN_CLR 0xffff0000
SD_DQLCRC14_MASK 0xffffffff
SCALER_DISPECTRL_CR_BUSY_MSB 31
SMI_DSW3_WFORMAT_LSB 23
USB_HPRT_SPD_SET 0x00060000
CM_TDCLKEN_PLLCDIV2_CLR 0xffffffbf
CM_H264CTL_GATE_LSB 6
I2C_SPI_SLV_DR_RXFLEVEL_BITS 31:27
HDMI_DETECTED_VERTA1_MASK 0x01ffffff
A2W_PLLD_ANA_VCOR_WIDTH 1
MPHI_APB_ID 0x6d706869
MPHI_OUTDDB 0x7e00602c:RW
SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_LSB 6
USB_HCSPLT0_COMP_SPLT_SET 0x00010000
EMMC_CONTROL0_HCTL_CRDDET_BITS 6:6
PCM_GRAY_RXLEVEL_CLR 0xfffffc0f
A2W_PLLB_CTRL_PRSTN_MSB 17
EMMC_HWCAP0_V3_3_LSB 24
PIXELVALVE2_INTSTAT 0x7e807028:RW
DMA5_CS_PANIC_PRIORITY_BITS 23:20
GP_LEV0_LEVn0_LSB 0
DMA15_DEBUG_OUTSTANDING_WRITES_BITS 7:4
DMA0_STRIDE_S_STRIDE_LSB 0
SH_EDM_READ_THRESHOLD_SET 0x0007c000
EMMC_BOOT_TIMEOUT_TIMEOUT_CLR 0x00000000
A2W_HDMI_CTL2_WIDTH 24
HDMI_MISC_CONTROL_RESET 0000000000
GP_FSEL1_FSEL11_CLR 0xffffffc7
L1_IC1_CONTROL_START_FLUSH_BITS 1:1
A2W_HDMI_CTL_HFEN_WIDTH 1
DMA_ENABLE_EN4_BITS 4:4
EMMC_IRPT_MASK_READ_RDY_MSB 5
SD_WTC_MASK 0x0fffffff
MS_SEMA_18_MASK 0x00000001
V3D_L2CACTL_WIDTH 32
DMA13_DEBUG_FIFO_ERROR_MSB 1
SYSAC_V3D_LIMITER_INCREMENT_LSB 0
APERF0_BW1_CTRL_EN_LSB 30
AVE_IN_CURRENT_LINE_BUF1 0x7e910020:RW
DMA4_TI_PERMAP_MSB 20
DMA9_DEST_AD_D_ADDR_CLR 0x00000000
V3D_PCTRC_WIDTH 16
PM_CAM1_RESET 0000000000
DMA15_TI_SRC_DREQ_CLR 0xfffffbff
USB_DCFG_EP_MIS_CNT_BITS 22:18
DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
TB_BOOT_OPT_WIDTH 32
SD_IDL 0x7ee00018:RW
CM_ISPCTL_KILL_BITS 5:5
PM_IMAGE_ISFUNC_LSB 5
A2W_PLLH_RCAL_CHENB_CLR 0xfffffeff
INTERRUPT_HOSTPORT ((64) + 32 )
ARM_IE_ILLEGAL 0x00000040
DMA14_CS_RESET_SET 0x80000000
USB_DCTL_CGOUT_NAK_SET 0x00000400
HDMI_RAM_PACKET_4_3_MASK 0xffffffff
AVE_IN_STATUS_OVERRUN_DET_SET 0x00000001
DMA12_TI_DEST_DREQ_SET 0x00000040
CMI_CAM0_MASK 0x0000003f
I0CACHE_BASE 0x7ee02000
DMA6_TI_DEST_IGNORE_SET 0x00000080
USB_HPRT_PWR_RESET 0x0
USB_DCTL_IGN_FRM_NUM_LSB 15
TH1T3PC 0x1A008000 + 0x28:RW
A2W_PLLA_DIG2R_RESET 0x00100401
MS_VPU_STAT_MASK 0x00ff00ff
SMI_DSR2_RSTROBE_CLR 0xffffff80
DMA_DEBUG_VERSION (1<<25)
CAM1_CAMIVWIN_RESET 0000000000
CM_SMIDIV 0x7e1010b4:RW
DMA13_CS_PANIC_PRIORITY_LSB 20
CAM0_CAMIBEA1_MASK 0xffffffff
CM_UARTCTL_ENAB_SET 0x00000010
CM_GP0CTL_BUSYD_CLR 0xfffffeff
APERF0_BW0_CTRL_LATHALT_SET 0x10000000
MS_SEMA_23_MASK 0x00000001
USB_DTKNQR4_WIDTH 32
MPHI_OUTDFS 0x7e006034:RW
CCP2TX_TPC_TNP_BITS 3:0
PWM_RNG3_RESET 0x00000020
HDMI_CPU_STATUS_MASK 0xffffffff
DMA9_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
CM_SYSCTL_GATE_MSB 6
CPG_Debug2_WIDTH 32
SH_HBCT_BYTECOUNT_SET 0xffffffff
HDMI_DETECTED_VERTA0_MANUAL_VSP0_SET 0x01f00000
GP_FSEL0_FSEL00_SET 0x00000007
DMA4_NEXTCONBK_ADDR_SET 0xffffffe0
USB_HCINT0_NAK_RESET 0x0
A2W_PLLH_RCALR_MASK 0x000003ff
USB_DTHRCTL_TX_THR_LEN_BITS 10:2
USB_GUSBCFG_ULPI_IF_PROT_DIS_SET 0x02000000
PCM_DREQ_A_RX_LSB 0
GP_BASE 0x7e200000
DMA10_TI_WAIT_RESP_BITS 3:3
PWM_STA_STA1_LSB 9
PM_PADS3_POWOK_BITS 5:5
PM_RSTS_HADDRQ_CLR 0xfffffffe
PM_DSI0_LDOCTRL_SET 0x001ffff8
A2W_PLLA_PER_BYPEN_SET 0x00000200
HDMI_RAM_PACKET_11_0_WIDTH 32
MS_MBOX_0_MBOX_LSB 0
DMA0_CS_INT_LSB 2
A2W_SMPS_CTLA2_WIDTH 24
A2W_PLLA_ANA_SSCS_STEP_LSB 0
L2_CONT_OFF_l2_flush_mode_MSB 4
A2W_PLLC_ANA_SCTL_UPDATE_SET 0x00000008
I2C_SPI_SLV_RIS_BERIS_BITS 2:2
USB_DIEPCTL0_DIS_MSB 30
EMMC_CMDTM_TM_AUTO_CMD_EN_BITS 3:2
EMMC_IRPT_MASK_RETUNE_CLR 0xffffefff
DMA0_TI_BURST_LENGTH_SET 0x0000f000
SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_CLR 0xffffff3f
GP_FSEL5_FSEL57_MSB 23
USB_HCCHAR0_CH_DIS_MSB 30
USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_BITS 31:31
USB_DIEPCTL0_CNAK_RESET 0x0
PCM_CS_A_EN_SET 0x00000001
AVE_IN_MAX_TRANSFER 0x7e910010:RW
SMI_CS_PRDY_SET 0x01000000
CM_PWMCTL_RESET 0x00000200
STCS_1 0xffffffff:RW
DMA14_DEST_AD_D_ADDR_SET 0xffffffff
SD_MR_HI_Z_MSB 29
PCM_INTEN_A_RXERR_CLR 0xfffffff7
HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT_BITS 15:15
SD_SD_T_RC_BITS 24:20
CM_DSI0PCTL_MASK 0x0000039f
APERF1_BW0_WTWAIT_WIDTH 32
APERF1_BW1_ATWAIT_MASK 0xffffffff
DMA11_TI_DEST_INC_BITS 4:4
USB_DOEPINT0_IN_TKN_EP_MIS_CLR 0xffffffdf
CM_DSI1ECTL_SRC_LSB 0
SD_DQLCRC6_MASK 0xffffffff
SD_DQLCRC11_RISE_BITS 31:16
HD_CSC_CTL_USERGB2YCC_LSB 1
PCM_DREQ_A_RESET 0x10303020
CM_DSI0ECTL_BUSYD_MSB 8
TXP_CTRL_VSTART_AT_EOF_BITS 15:15
GP_SET0_MASK 0xffffffff
SD_STALL_CYCLES_LSB 0
CMI_CAM0 0x7e802000:RW
CM_ARMCTL_KILL_SET 0x00000020
HDMI_CPU_CLEAR_MASK 0xffffffff
DMA1_CS_PRIORITY_BITS 19:16
CM_DPICTL_BUSY_SET 0x00000080
DMA14_CS_ACTIVE_MSB 0
USB_DCTL_RMT_WKUP_SIG_CLR 0xfffffffe
MPHI_MOUTFS_LEVEL_RESET 0x0
CCP2RDSA0 CCP2_BASE_ADDRESS + 0x120:RW
I2C_SPI_SLV_MIS_BEMIS_SET 0x00000004
A2W_XOSC_CTRL_SMPSOK_LSB 15
AVE_IN_CTRL_WIDTH 32
CM_INTEN_A2WDONE_CLR 0xffefffff
CM_VPUCTL_BUSY_CLR 0xffffff7f
STCS_x(x) MACRO
SCALER_DISPECTRL_POSTED_CTRL_LSB 16
SPI_CS_INTD_SET 0x00000200
APERF1_BW0_AMAX_RESET 0000000000
DMA12_TI_MASK 0x03fffff9
A2W_PLLH_ANA_VCO_RESET 0000000000
L1_L1_SANDBOX_START1_START_ADDR_MSB 29
UNICAM_REG(x,d) MACRO
USB_DOEPTSIZ3_MASK 0xffffffff
CM_DPIDIV_DIV_LSB 4
SD_SC_T_WTR_CLR 0xffffff8f
EMMC_IRPT_MASK_DMA_SET 0x00000008
DMA6_CS_ERROR_BITS 8:8
SLIM_DCC9_PA1_RESET 0000000000
EMMC_FORCE_IRPT_CBAD_ERR_LSB 19
CMI_CAMTEST_SRC_LSB 0
CM_INTEN_WRFAIL_LSB 19
A2W_SMPS_CTLB1R_WIDTH 24
GRSPADR 0x1A005800 + 0x14:RW
AVE_OUT_CTRL_REFRESH_RATE_CLR 0xfffffff3
CM_UARTCTL_BUSYD_LSB 8
HD_HDM_CTL_CECRXD_BITS 9:9
TH1T1UD 0x1A008000 + 0x1C:RW
TB_BASE 0x7e20b000
GP_FSEL6_FSEL67_SET 0x00e00000
USB_GOTGCTL_A_SES_VLD_RESET 0x0
DMA9_DEBUG_VERSION_SET 0x0e000000
MS_SEMA_27_WIDTH 1
CM_DPICTL_FRAC_CLR 0xfffffdff
HDMI_READ_POINTERS_DRFT_UNDERFLOW_LSB 16
CM_PWMCTL_MASK 0x000007bf
DMA14_CONBLK_AD_SCB_ADDR_BITS 31:5
DSI0_CMD_PKTH_MASK 0xffffffff
SCALER_DISPLACT0 0x7e400030:RW
SCALER_DISPLACT1 0x7e400034:RW
SCALER_DISPLACT2 0x7e400038:RW
DMA5_DEBUG_VERSION_BITS 27:25
OTP_STATUS_REG_WIDTH 32
SD_VER_RESET 0x00000009
USB_DIEPTXF12_WIDTH 32
L1_D0_WBACKS_MASK 0000000000
GRMCIH0 0x1A005C80 + 0x40:RW
GRMCIH1 0x1A005C80 + 0x60:RW
SMI_DSR2_RSETUP_CLR 0xc0ffffff
FPGA_MB_XSLC1_BUILD_NUM 0x7e20b718:RO
PCM_CS_A_SYNC_CLR 0xfeffffff
A2W_PLLD_CTRL_PWRDN_SET 0x00010000
HDMI_RAM_PACKET_9_8_WIDTH 32
SPI_CS_CPOL_LSB 3
EMMC_IRPT_MASK_INT_A_BITS 9:9
DMA12_CONBLK_AD 0x7e007c04:RW
MPHI_INTSTAT_RX1TEND_SET 0x00001000
GRTLBIAS0 0x1A005200 + 0x1C:RW
GRTLBIAS1 0x1A005220 + 0x1C:RW
GRTLBIAS2 0x1A005240 + 0x1C:RW
GRTLBIAS3 0x1A005260 + 0x1C:RW
GRTLBIAS4 0x1A005280 + 0x1C:RW
GRTLBIAS5 0x1A0052A0 + 0x1C:RW
GRTLBIAS6 0x1A0052C0 + 0x1C:RW
USB_GHWCFG2_NUM_EPS_LSB 13
DSI0_PIX_FIFO_MASK 0xffffffff
USB_GOTGCTL_SES_REQ_BITS 1:1
L1_IC1_PRIORITY_IC1_APRIORITY2_LSB 8
CM_DFTCTL_BUSYD_SET 0x00000100
CM_GP2CTL_FRAC_BITS 9:9
SCALER_DISPECTRL_GT8_BURST_MSB 31
A2W_PLLH_ANA_STAT_RCALDONE_SET 0x00001000
FPGA_STATUS0_SW_SPI_SPI_IN_CLR 0xffffff7f
SYSAC_DUMMY_STATUS_IDLE_MSB 0
HDMI_RAM_PACKET_6_7_MASK 0xffffffff
DMA5_TI 0x7e007508:RO
OTP_CODE_SIGNING_KEY_ROW_REDUNDANT (((((((((8 +4)+4)+1)+1)+1)+4)+4)+1)+4)
CAM1_CAMCMP0_MASK 0xffffffff
IC1_SRC0 0x7e002808:RO
HDMI_HORZA_MANUAL_HPOL_BITS 13:13
PM_PROC_ARMRSTN_LSB 6
EMMC_STATUS_CARD_STABLE_SET 0x00020000
USB_GINTMSK_OEP_INT_SET 0x00080000
CM_VECDIV_WIDTH 16
DMA14_CS_INT_SET 0x00000004
HDMI_TX_PHY_TX_PHY_RESET_CTL_RESET 0x003f01ff
CM_GNRICDIV_DIV_CLR 0xff000000
A2W_PLLH_ANA_SCTLR 0x7e102d70:RW
I2C_SPI_SLV_FR_TXFF_LSB 2
DMA2_TI_SRC_IGNORE_BITS 11:11
SCALER_DISPCTRL0_MASK 0xffffffff
CM_INTEN_FGAINC_MSB 12
HDMI_DETECTED_HORZA_MANUAL_HPOL_CLR 0xffffdfff
DSI0_PHYC_txulpshs_1_sync_BITS 6:6
PM_AVS_INTEN_ALERT_ARM_P_LSB 4
USB_DIEPCTL0_WIDTH 32
USB_GHWCFG2 0x7e980048:RW
DMA8_TI_SRC_WIDTH_SET 0x00000200
EMMC_CONTROL2_ACBAD_ERR_CLR 0xffffffef
USB_DIEPCTL0_ENA_LSB 31
DMA6_TI_SRC_WIDTH_SET 0x00000200
USB_GUSBCFG_TERM_SEL_DL_PULSE_CLR 0xffbfffff
DMA4_CS_END_BITS 1:1
SD_DMRCRC0_HIGH_LSB 16
DMA11_CONBLK_AD_SCB_ADDR_LSB 5
DMA5_CS_DREQ_SET 0x00000008
SMI_DSW1_WSETUP_CLR 0xc0ffffff
DMA14_CS_DISDEBUG_SET 0x20000000
HDMI_READ_POINTERS_DRFT_UNDERFLOW_SET 0x00010000
PM_DFT_STOPALLCLOCKS_LSB 1
GP_FSEL5_FSEL53_LSB 9
DMA14_TI_SRC_IGNORE_BITS 11:11
USB_GUID 0x7e98003c:RW
AVE_IN_STATUS_OVERRUN_CNT_CLR 0xe0ffffff
CM_EVENT_GAINC_SET 0x00000004
DMA12_DEBUG_VERSION_SET 0x0e000000
A2W_SMPS_B_STATR_WIDTH 13
CM_TIMERCTL_BUSY_CLR 0xffffff7f
SMI_DSR0_FSETUP_CLR 0xffbfffff
HDMI_RAM_PACKET_7_7_RESET 0000000000
EMMC_HWCAP1_MULTIPLIER_SET 0x00ff0000
PM_GNRIC_POWOK_BITS 1:1
DMA14_TI_INTEN_SET 0x00000001
SMI_CS_RXR_SET 0x08000000
I2C_SPI_SLV_IMSC_BEIM_SET 0x00000004
CM_EMMCCTL_ENAB_MSB 4
PM_CAM1_LDOHPEN_SET 0x00000004
PCMDREQ_RXDREQTHR_LSB 0
SCALER_DISPSTAT_DMA_IRQ_SET 0xfffffff0
AJB_D1_FALL 0x000000
SH_HSTS_CMD_TIME_OUT_LSB 6
A2W_PLLD_CORE_MASK 0x000003ff
CM_V3DDIV_MASK 0x0000fff0
FPGA_STATUS0 0x7e20b60c:RO
CM_SMICTL_KILL_LSB 5
APERF1_BW2_ATWAIT 0x7ee080c8:RO
EMMC_STATUS_CARD_DETECT_BITS 18:18
USB_DIEPCTL8_MASK 0xffffffff
I2C_SPI_SLV_DEBUG2_DATA_CLR 0xff000000
APHY_CSR_ADDR_SPR_RO 0x7ee06090:RW
CAM0_CAMIVSTA_WIDTH 32
EMMC_CMDTM_CMD_TYPE_SET 0x00c00000
EMMC_HWCAP1_SDR104_BITS 1:1
TXP_APB_ID 0x20763374
HDMI_RAM_PACKET_2_6_MASK 0xffffffff
CM_PLLD_LOADPER_LSB 6
L1_IC0_PRIORITY_IC0_APRIORITY1_CLR 0xffffff0f
HD_HDM_CTL_SW_RST_RESET 0x0
HDMI_DETECTED_VERTA0_MANUAL_VAL0_MSB 12
DMA15_CS_ERROR_MSB 8
HD_MAI_THR_MASK 0xffffffff
SMI_CS_TXD_SET 0x10000000
L1_D1_WR_THRUS_WIDTH 0
GP_REN0_RENn0_SET 0xffffffff
EMMC_HWCAP0_TCLKUNIT_CLR 0xffffff7f
CM_HSMCTL_BUSYD_SET 0x00000100
DMA5_TI_DEST_WIDTH_MSB 5
SCALER_DISPGAMDAT_WIDTH 32
A2W_PLLA_ANA_MULTI_WIDTH 0
A2W_PLLH_ANA_KAIP_WIDTH 11
SMI_DSR3_RHOLD_MSB 21
DMA13_TI_SRC_INC_SET 0x00000100
APERF0_BW2_AMAX_RESET 0000000000
EMMC_INTERRUPT_WRITE_RDY_SET 0x00000010
SMI_CS_EDREQ_MSB 15
USB_GHWCFG2_EN_PERIO_HOST_CLR 0xfffbffff
DMA15_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
APHY_CSR_ADDR_PAD_MISC_CTRL 0x7ee0606c:RW
GRMCIL1 0x1A005C80 + 0x20:RW
A2W_PLLH_ANA_SCTLR_WIDTH 5
DMA1_CS_MASK 0xf0ff017f
A2W_PLLB_DIG3_MASK 0x00ffffff
USB_DOEPDMAB8_WIDTH 32
MPHI_C0INDCF_EMPTY_CLR 0x7fffffff
SD_DQRCRC13_RISE_SET 0xffff0000
VEC_INTERRUPT_STATUS_MASK 0xffffffff
SYSAC_TRANS_PRIORITY_P_PRIORITY_LSB 4
SPI_CS_DONE_MSB 16
TB_BOOT_OPT_ELPIDA_BITS 4:4
A2W_PLLD_ANA_STATR 0x7e102c50:RW
GP_FSEL2_MASK 0x3fffffff
PWM_RNG1_WIDTH 32
HD_MAI_CTL_BUSY_MSB 14
MS_MBOX_7_MBOX_LSB 0
SLIM_DCC3_CON_RESET 0000000000
MULTICORE_SYNC_IREQ_0 MULTICORE_SYNC_BASE_ADDRESS + 0x84:RW
DMA11_DEBUG_FIFO_ERROR_MSB 1
A2W_SMPS_L_SIV_VOLTS_SET 0x0000001f
PM_PROC_ISFUNC_SET 0x00000020
CM_V3DCTL_BUSY_SET 0x00000080
PM_RSTC_FRCFG_LSB 16
I2C_SPI_SLV_IMSC_TXIM_LSB 1
SD_CS_DPD_RESET 0x0
SMI_DSR2_RHOLD_LSB 16
DMA0_TI_WAITS_SET 0x03e00000
PM_PADS5_SLEW_LSB 4
PCMFIFO PCM_BASE_ADDRESS + 0x04:RW
USB_DIEPCTL0_SNP_SET 0x00100000
USB_DOEPINT0_XFER_COMPL_LSB 0
EMMC_IRPT_EN_CCRC_ERR_MSB 17
EMMC_FORCE_IRPT_CCRC_ERR_LSB 17
HD_VID_CTL_HPOL_RESET 0x0
USB_GVBUSDRV_WIDTH 16
DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
USB_GNPTXFSIZ_NP_TXF_DEP_RESET 0x0
SD_CARCRC_RISE_LSB 16
V3D_SCRATCH_WIDTH 32
HD_HDM_CTL 0x7e80800c:RW
TH1ITPC 0x1A008000 + 0x0C:RW
A2W_PLLC_FRACR_WIDTH 20
EMMC_HWMAXAMP0_AMP_33V_MSB 7
CM_GNRICCTL_ENAB_CLR 0xffffffef
CCP2TX_TPC_TPT_CLR 0xffff00ff
DMA0_TI_WAIT_RESP_SET 0x00000008
PM_AUDIO_MASK 0x003fffff
CM_DSI0ECTL_RESET 0000000000
GP_FEN1_WIDTH 32
SD_TMC_IPRD_CLR 0xffff00ff
EMMC_CONTROL2_EN_AINT_CLR 0xbfffffff
CM_INTEN_OCDONE_SET 0x00200000
TIMER_CTRL_ENABLE (1 << 7)
DMA15_CS_INT_CLR 0xfffffffb
DMA3_TI_SRC_IGNORE_CLR 0xfffff7ff
GPPUDCLK1 0x7e200000 + 0x9C:RW
SD_DQRCRC0_FALL_CLR 0xffff0000
DMA15_TXFR_LEN_XLENGTH_SET 0x0000ffff
EMMC_STATUS_WRT_PROTECT_LSB 19
CM_CAM0CTL_ENAB_CLR 0xffffffef
A2W_SMPS_L_SPVR_WIDTH 5
A2W_PLLD_MULTI_WIDTH 0
HD_CSC_24_23_MASK 0xffffffff
A2W_PLLC_CTRL_PRSTN_CLR 0xfffdffff
ASB_H264_S_CTRL_RESET 0x00000007
SMI_CS_AFERR_BITS 25:25
PM_SMPS_CTRLEN_MSB 0
DMA2_TI_WAIT_RESP_BITS 3:3
EMMC_CONTROL1_CLK_GENSEL_BITS 5:5
MS_SEMA_30_MASK_CLR 0xfffffffe
AUX_MU_LSR_REG (0x7E215000 +0x054)
DSI0_CMD_PKTH_RESET 0000000000
DMA_INT_STATUS_INT7_LSB 7
VPU_ARB_CTRL_L2_DELAY_RESET 0x0
GROPCTR_FBC_EZ_FE_REQS 0x39
SD_DQRCRC6_FALL_CLR 0xffff0000
CM_PLLD_LOADCORE_LSB 4
USB_HCINT0_XFER_COMPL_CLR 0xfffffffe
DMA2_TI_NO_WIDE_BURSTS_LSB 26
USB_GOTGCTL_HNP_REQ_MSB 9
CAM1_CAMICTL_WIDTH 32
SLIM_DCC0_PA0_WIDTH 24
DMA6_TI_SRC_INC_SET 0x00000100
HDMI_VERTB1_MANUAL_VBP1_LSB 8
SD_PHYC_VREF_ENB_LSB 4
L1_D1_WR_SNOOPS 0x7ee02194:RO
CM_EMMCCTL_KILL_CLR 0xffffffdf
DMA8_CS_RESET_SET 0x80000000
ACRECORDRATE 0x32
APERF1_BW1_CTRL_EN_LSB 30
DPI_C_WIDTH 16
HDMI_PERT_TEST_LENGTH_MASK 0xffffffff
SH_ARG_ARGUMENT_BITS 31:0
USB_GPVNDCTL_DIS_ULPI_DRVR_RESET 0x0
CAM1_CAMISTA 0x7e801104:RW
MS_SEMA_14_MASK_CLR 0xfffffffe
USB_GRXSTSP_HST_PKT_STS_LSB 17
CM_GP1DIV 0x7e10107c:RW
DMA14_CS_ACTIVE_BITS 0:0
SMI_DSW1_WHOLD_MSB 21
CM_PLLA_LOADCORE_BITS 4:4
EMMC_CONTROL0_HCTL_LED_MSB 0
DMA11_TI_INTEN_BITS 0:0
GP_FSEL0_FSEL05_MSB 17
GP_FSEL4_FSEL43_MSB 11
MPHI_AXIPRIV_RXPROT_BITS 6:4
PM_PROC_ENAB_LSB 12
GP_FSEL2_FSEL26_CLR 0xffe3ffff
DMA2_TI_INTEN_MSB 0
DMA11_TXFR_LEN_XLENGTH_LSB 0
CM_EMMCCTL_SRC_BITS 3:0
AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_CLR 0xfffff000
USB_DOEPINT0_TX_FIFO_UNDRN_SET 0x00000100
CM_UARTCTL 0x7e1010f0:RW
V3D_PCTR6_MASK 0xffffffff
CM_SLIMCTL_BUSY_SET 0x00000080
I2C_SPI_SLV_MIS 0x7e214020:RW
DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
DMA11_CS_ABORT_SET 0x40000000
DMA6_TI_SRC_INC_BITS 8:8
L1_IC0_FLUSH_S_WIDTH 32
USB_HFNUM_REM_LSB 16
HDMI_RAM_PACKET_CONFIG 0x7e9020a0:RW
I2CDIV_0 0x7e205000 + 0x14:RW
I2CDIV_1 0x7e804000 + 0x14:RW
HDMI_TX_PHY_HDMI_TX_PHY_CTL_2 (HDMI_BASE_ADDRESS + 0x2c0) + 12:RW
I2CDIV_3 I2C_BASE_3 + 0x14:RW
EMMC_FORCE_IRPT_CEND_ERR_MSB 18
CCP2TX_TS_TQI_CLR 0xfff7ffff
USB_DOEPDMAB9_MASK 0xffffffff
PM_SMPS_RSTDR_SET 0x00000002
I2C_SPI_SLV_DR_RXFF_SET 0x00080000
SLIM_DCC0_PA1_MASK 0x00ffff3f
DMA_ENABLE_EN3_MSB 3
USB_DOEPINT0_TX_FIFO_UNDRN_RESET 0x0
SD_DQRCRC10_RISE_BITS 31:16
SD_CS_STALLING_CLR 0xfeffffff
SH_EDM_FIFO_COUNT_LSB 4
SD_VIN_WRITE_MSB 16
DMA7_SOURCE_AD_S_ADDR_CLR 0x00000000
DMA1_CS_DISDEBUG_LSB 29
L1_IC1_RD_HITS_MASK 0000000000
SMI_CS_ENABLE_CLR 0xfffffffe
HDMI_PERT_INSERT_ERR_WIDTH 24
DSI1_TXPKT2_C_RESET 0000000000
DMA12_TI_DEST_WIDTH_BITS 5:5
A2W_PLLD_ANA_SSCS_MODE_LSB 16
DMA3_NEXTCONBK_ADDR_BITS 31:5
DMA10_CS_PRIORITY_SET 0x000f0000
DMA6_DEST_AD_D_ADDR_LSB 0
DMA2_CS_DREQ_LSB 3
DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
SH_RSP2_MASK 0xffffffff
USB_DCFG_PER_SCH_INTV_LSB 24
A2W_PLLA_ANA0R_MASK 0x00ffffff
DMA13_DEBUG_READ_ERROR_BITS 2:2
PWM_STA_GAPO2_SET 0x00000020
USB_GHWCFG4_HSPHY_DWIDTH_MSB 15
SMIDS_WIDTH 30
GP_FSEL1_FSEL15_SET 0x00038000
CM_GP1CTL_BUSYD_MSB 8
A2W_PLLA_ANA0R_WIDTH 24
MPHI_AXIPRIV_TXPROT_CLR 0xfffffff8
GP_FSEL1_FSEL17_MSB 23
CSI2_RLS0 CSI2_BASE_ADDRESS + 0x11C:RW
CSI2_RLS1 CSI2_BASE_ADDRESS + 0x21C:RW
CM_DFTCTL_FRAC_LSB 9
A2W_PLLB_ANA3R 0x7e1028fc:RW
VEC_CGMSAE_REVID 0x7e80605c:RW
PCM_DREQ_A_TX_SET 0x00007f00
I2C2_CLKT_RESET 0x00000040
CM_INTEN_GAINA_BITS 0:0
HDMI_FIFO_CTL_USE_FULL_LSB 1
CM_INTEN_LOSSA_CLR 0xffffffdf
EMMC_IRPT_EN_ACMD_ERR_CLR 0xfeffffff
DMA1_CONBLK_AD_SCB_ADDR_BITS 31:5
FPGA_CTRL0_SPI0_SEL_A_BITS 9:9
USB_GOTGCTL_SES_REQ_SCS_MSB 0
EMMC_FORCE_IRPT_MASK 0xffff00ff
HDMI_DETECTED_VERTB1_MANUAL_VBP1_SET 0x00000100
ARM_1_SEM1 (0x7E00B000 +0x900)+0x04:RW
ARM_1_SEM2 (0x7E00B000 +0x900)+0x08:RW
ARM_1_SEM3 (0x7E00B000 +0x900)+0x0C:RW
ARM_1_SEM4 (0x7E00B000 +0x900)+0x10:RW
HDMI_RAM_PACKET_7_5_WIDTH 32
ARM_1_SEM6 (0x7E00B000 +0x900)+0x18:RW
ARM_1_SEM7 (0x7E00B000 +0x900)+0x1C:RW
A2W_SMPS_C_CTL_UPEN_MSB 1
USB_HCTSIZ0_PKT_CNT_LSB 19
DMA5_TI_PERMAP_BITS 20:16
EMMC_HWCAP0_MAXLEN_LSB 16
SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_SET 0x00000030
A2W_PLLD_CTRL_NDIV_BITS 9:0
MS_MBOX_7_MBOX_BITS 31:0
CSI2_SRST CSI2_BASE_ADDRESS + 0x90:RW
I2C_SPI_SLV_IMSC_OEIM_MSB 3
DMA5_TI_NO_WIDE_BURSTS_SET 0x04000000
APHY_CSR_DDR_PLL_DESKEW_STATUS 0x7ee06064:RW
EMMC_CONTROL0_WAKE_ONINS_EN_CLR 0xfdffffff
DMA7_CS_ACTIVE_BITS 0:0
TXP_DIM_HEIGHT_LSB 16
MPHI_RXAXICFG_INTHRESH_SET 0x0001ff00
PWM_CTL_POLA1_MSB 4
A2W_SMPS_CTLC1_MASK 0x00ffffff
CM_BURSTCTL_BUSY_BITS 7:7
MS_SEMA_21_RESET 0000000000
CM_INTEN_GAINB_SET 0x00000002
USB_GRSTCTL_FRM_CNTR_RST_SET 0x00000004
I2C_SPI_SLV_FR_WIDTH 16
GP_FSEL5_FSEL50_BITS 2:0
DMA_INT_STATUS_INT0_CLR 0xfffffffe
A2W_PLLA_ANA_SCTL_UPDATE_LSB 3
TXP_CTRL_VERSION_LSB 22
FPGA_MB_SDC_V3D_FREQ 0x7e20b730:RO
DMA10_TI_WAIT_RESP_SET 0x00000008
DMA8_CS_DISDEBUG_MSB 29
VEC_ENC_RevID_WIDTH 32
ASB_H264_M_CTRL_FULL_SET 0x00000008
USB_GINTMSK_P_TXF_EMP_SET 0x04000000
CM_PWMCTL_BUSYD_LSB 8
HDMI_FIFO_CTL_CAPTURE_POINTER_CLR 0xfffffffb
I2C_SPI_SLV_DR_TXDMABREQ_SET 0x00000800
CM_EVENT_GAINH_MSB 4
GP_FSEL4_FSEL42_BITS 8:6
EMMC_STATUS_READ_TRANSFER_LSB 9
HDMI_RAM_PACKET_9_2_RESET 0000000000
MS_VPUSEMA_1_VPUSEMA_1_MSB 0
GP_FEN2_FENn64_SET 0x0000003f
A2W_SMPS_L_SIA_WIDTH 10
TB_PRINTER_DATA_MASK 0xffffffff
DMA8_TI_WAITS_CLR 0xfc1fffff
L1_IC0_CONTROL_RAS_DISABLE_MSB 4
GP_FSEL3_FSEL34_BITS 14:12
CM_DSI1EDIV 0x7e10115c:RW
USB_DTHRCTL_TX_THR_LEN_LSB 2
CM_EVENT_WRFAIL_MSB 19
A2W_PLLD_ANA_SCTL_SEL_MSB 2
GP_FSEL0_FSEL01_LSB 3
HDMI_13_AUDIO_STATUS_1 0x7e902154:RW
HD_MAI_THR_WIDTH 32
JICST_CDONE (1 << 16)
SPI_CS_RXR_MSB 19
DMA1_NEXTCONBK_ADDR_CLR 0x0000001f
CM_DSI0PDIV 0x7e101064:RO
HDMI_RAM_PACKET_5_4_RESET 0000000000
I2C_SPI_SLV_DR_RXFF_MSB 19
MS_SEMA_9_MASK_SET 0x00000001
PWM_STA_EMPT1_LSB 1
A2W_PLLA_CORE_CHENB_CLR 0xfffffeff
A2W_PLLA_PER_MASK 0x000003ff
PIARBCTL_CAM_THRESHOLD_BITS 5:4
DMA12_CS_INT_CLR 0xfffffffb
A2W_PLLC_PER_CHENB_MSB 8
A2W_PLLC_DIG2_WIDTH 24
DMA3_DEBUG_DMA_ID_LSB 8
TXP_CTRL_PILOT_BITS 31:24
GP_FSEL1_FSEL18_BITS 26:24
HDMI_HDMI_13_AUDIO_STATUS_1 HDMI_BASE_ADDRESS + 340:RW
USB_DAINT_IN_EP_INT_CLR 0xffff0000
CCP2TX_TIC_TQIT_BITS 7:4
CAM1_CAMIBWP_MASK 0xffffffff
USB_DIEPTSIZ13_WIDTH 32
HDMI_RAM_PACKET_1_6_RESET 0000000000
A2W_HDMI_CTL_RCAL_SELAVG_CLR 0xfffffffc
MS_SEMA_21_MASK_BITS 0:0
SD_SECEND3_ADDR_LS_SET 0x00001fff
AUX_SPI1_TXHOLD_REG (0x7E215000 +0x0F0)
CM_H264CTL_WIDTH 10
AUX_SPI_CNTL0_BITS 0x0000003F
CM_GP0CTL_ENAB_SET 0x00000010
EMMC_BUS_CTRL_CLK_PINS_CLR 0xfffffff8
SD_DQRCRC7_FALL_CLR 0xffff0000
DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
SMI_DCS_RESET 0000000000
CM_TDCLKEN_HDMIBYP_LSB 8
EMMC_CONTROL0_READWAIT_EN_BITS 18:18
A2W_PLLH_CTRL 0x7e102160:RW
APERF1_BW2_RPEND_MASK 0x000000ff
SMI_DSW2_WSWAP_BITS 22:22
USB_HPRT_CONN_DET_LSB 1
CM_PLLC_ANARST_CLR 0xfffffeff
PCMCS_RXTHR_FULL (3 << 7)
V3D_PCTR13_WIDTH 32
CM_TD0CTL_STEP_SET 0x00001000
EMMC_CONTROL2_DRVTYPE_SET 0x00300000
CCP2TX_TTC_ATX_BITS 31:31
APERF0_BW2_WTRANS_WIDTH 32
A2W_PLLH_ANA_STATR_WIDTH 21
L1_IC0_RAS_POPS_MASK 0000000000
FPGA_CTRL0_DIS_CTL0_SET 0x00000001
SD_MR 0x7ee00090:RW
DMA3_CS_PAUSED_CLR 0xffffffef
MS_IREQ_1_IREQ_1_MSB 31
SD_DQLCRC7_WIDTH 32
SD_CS_PUSKIP_BITS 4:4
TB_JTB_CONFIG_ENABLE_LSB 11
USB_DIEPINT0_STS_PHSE_RCVD_LSB 5
DMA2_STRIDE_D_STRIDE_SET 0xffff0000
USB_GUSBCFG_HNP_CAP_RESET 0x0
PM_HDMI_CTRLEN_BITS 0:0
A2W_PLLA_CORE_DIV_BITS 7:0
MPHI_C0INDDB_MENDINT_LSB 30
PM_DFT_ALLOWAUDIOCKSTOP_CLR 0xfffffffe
CM_DSI1PCTL_SRC_CLR 0xfffffff0
MPHI_CTRL_WIDTH 32
AVE_OUT_CTRL_BYTE_SWAP_LSB 19
SD_PHYC_CRC_EN_RESET 0x0
SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_RESET 0x0
A2W_PLLA_CCP2_RESET 0x00000100
USB_GINTMSK_RXF_LVL_LSB 4
USB_GOTGINT_DBNCE_DONE_LSB 19
USB_GOTGCTL_B_SES_VLD_CLR 0xfff7ffff
DMA9_CS_ERROR_MSB 8
EMMC_CONTROL0_WAKE_ONREM_EN_BITS 26:26
GP_FSEL6_FSEL68_LSB 24
HDMI_RAM_PACKET_7_4_MASK 0xffffffff
DMA5_DEBUG_DMA_STATE_CLR 0xfe00ffff
PCM_MODE_A_CLK_DIS_CLR 0xefffffff
I2C0_DIV_RESET 0x000005dc
PCM_TXC_A_CH1WID_LSB 16
SMICS_INTD 9
DMA2_DEBUG_FIFO_ERROR_CLR 0xfffffffd
PM_GNRIC_ENAB_MSB 12
MPHI_HSINDDA_START_CLR 0x00000000
CM_OSCFREQI_INT_BITS 7:0
A2W_PLLB_DIG0R_WIDTH 24
USB_DOEPINT0_BACK2BACK_SETUP_RESET 0x0
AUX_SPI0_TXHOLD_REG (0x7E215000 +0x0B0)
SMICS_INTR 11
SMICS_INTT 10
CM_PLLA_LOADCCP2_SET 0x00000004
HDMI_13_AUDIO_STATUS_1_MASK 0x00000001
L1_L1_SANDBOX_START4_CTRL_BITS 0:0
SYSAC_ISP_PRIORITY_WIDTH 4
PWM_CTL_PWEN2_LSB 8
PM_AVS_EVENT_ALERT_SYSTEM_A_CLR 0xfffffffd
SD_SA_CLKSTOP_SET 0x00000080
A2W_PLLB_ANA_MULTI_WIDTH 0
CM_INTEN_LOSSH_BITS 9:9
I2C_SPI_SLV_DR_OE_CLR 0xfffffeff
A2W_HDMI_CTL_RCAL_MANREN_SET 0x00001000
CSI2_RBC_x(x) MACRO
I2C_SPI_SLV_CR_INV_TXF_BITS 13:13
SMI_DSR1_RPACEALL_CLR 0xffff7fff
DMA4_TI_DEST_DREQ_BITS 6:6
MPHI_HSINDCF_LENERR_LSB 30
SLIM_DCC7_PA1_MASK 0x00ffff3f
L1_L1_SANDBOX_START0_START_ADDR_BITS 29:5
HD_HDM_CTL_ENDIAN_LSB 1
SD_DQLCRC14_FALL_MSB 15
V3D_DBSCS_WIDTH 32
VCE_DATA_MEM_SIZE 0x2000
DMA2_TXFR_LEN_MASK 0x3fffffff
DMA12_NEXTCONBK_WIDTH 32
PM_IMAGE_ISPOW_LSB 2
V3D_MEM1_BASE_ADDRESS 0x1A00B000
MS_SEMA_7_MASK 0x00000001
DMA13_DEBUG_FIFO_ERROR_CLR 0xfffffffd
MPHI_INTSTAT_HSDISC_LSB 30
PCM_RXC_A_CH1POS_LSB 20
EMMC_STATUS_CARD_STABLE_LSB 17
CM_VECCTL_KILL_LSB 5
CM_ARMCTL_BUSYD_BITS 8:8
L2_TAG_STALLS_WIDTH 32
SD_SC_WL_RESET 0x2
AVE_IN_CTRL_OVERRUN_IRQ_EN_CLR 0xfffffffe
SLIM_DMA_DC1_RESET 0000000000
MPHI_RXAXICFG_RXPPRIO_CLR 0xffffff0f
OTP_SUSPEND_SECURE_RAM_KEY_SIZE_IN_ROWS 2
A2W_SMPS_CTLA2R_WIDTH 24
USB_HCINTMSK4_MASK 0xffffffff
USB_DIEPCTL0_CNAK_SET 0x04000000
CAM1_CAMIDI0_WIDTH 32
USB_HCINT0_NYET_LSB 6
I2C_SPI_SLV_MIS_RXMIS_CLR 0xfffffffe
ASB_H264_M_CTRL_CLR_REQ_BITS 0:0
APERF1_BW2_CTRL_ID_RESET 0x0
CM_DSI1PCTL_FRAC_BITS 9:9
DMA8_CS_RESET_BITS 31:31
L1_L1_SANDBOX_START0_CTRL_MSB 0
MS_ICCLR_0_ICCLR_0_BITS 0:0
USB_GPVNDCTL_REG_WR_MSB 22
DMA6_CS_RESET_LSB 31
DMA10_CS_DREQ_STOPS_DMA_BITS 5:5
L2_FLUSH_END 0x7ee01008:RW
USB_GRSTCTL_H_SFT_RST_SET 0x00000002
A2W_SMPS_C_CLKR_WIDTH 4
CM_TD0CTL_KILL_BITS 5:5
V3D_SRQUA_WIDTH 32
A2W_PLLB_SP1_DIV_LSB 0
SD_DQLCRC8_RISE_RESET 0x0
DMA12_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
MPHI_C0INDDB_LENGTH_CLR 0xfff00000
A2W_SMPS_CTLB1R_MASK 0x00ffffff
CM_TDCLKEN_PLLDDIV2_SET 0x00000080
AUX_MU_CNTL_REC_ENBL 0x01
CM_CAM0CTL_SRC_CLR 0xfffffff0
DMA11_NEXTCONBK_MASK 0xffffffe0
PCM_TXC_A_CH1WEX_SET 0x80000000
SMI_DSW0_RESET 0x0101000c
HDMI_PACKET_FIFO_STATUS_WIDTH 26
USB_GHWCFG2_NUM_EPS_SET 0x0000000000
SD_DQLCRC15_RISE_CLR 0x0000ffff
HDMI_RAM_PACKET_1_3_MASK 0xffffffff
AM_HO_MEMPRI 0x1800d00c:RW
A2W_SMPS_L_SCV_VOLTS_SET 0x0000001f
A2W_PLLD_DSI0_CHENB_MSB 8
VPU_ARB_CTRL_L2_LIMIT_RESET 0x0
SH_CMD_LONG_RESPONSE_SET 0x00000200
SMI_DSW1_WFORMAT_CLR 0xff7fffff
USB_HPRT_CONN_STS_RESET 0x0
SPI_DLEN_LEN_BITS 15:0
AVE_OUT_CTRL_INVERT_HSYNC_SET 0x00004000
USB_HCINT0_AHB_ERR_SET 0x00000004
GP_CLR2_CLRn64_CLR 0xffffffc0
DMA13_DEBUG_DMA_ID_LSB 8
GRP_SDBG0 0x1A005740 + 0x10:RW
USB_DIEPDMA9_WIDTH 32
USB_GPVNDCTL_CTRL_ULPI_SET 0x00003f00
L1_D1_RD_HITS 0x7ee02180:RW
DMA2_CS_RESET 0000000000
UART_LCR_OUT1_CLR 0xfffffffb
APERF0_BW2_CTRL_RESET_LSB 31
PM_HDMI_CTRLEN_CLR 0xfffffffe
GP_LEN1_LENn32_BITS 31:0
A2W_PLLH_ANA_STAT_RESET 0000000000
SMI_CS_TXE_LSB 30
OTP_WRITE_DATA_READ_REG_WIDTH 32
SYSAC_HVSM_PRIORITY_N_PRIORITY_CLR 0xfffffff0
DMA6_STRIDE_S_STRIDE_SET 0x0000ffff
A2W_XOSC_CPR_DIV_MSB 1
SMI_DC_PANICR_LSB 18
SLIM_DCC6_PA0 0x7e2102c0:RW
SLIM_DCC6_PA1 0x7e2102c4:RW
USB_DOEPDMAB15_WIDTH 32
PM_PADS6_DRIVE_CLR 0xfffffffc
SH_HSTS_MASK 0x000007f9
GP_FSEL4_FSEL40_MSB 2
DMA10_TI_SRC_DREQ_SET 0x00000400
A2W_PLLC_ANA_SSCS_MODE_MSB 16
SD_SECSRT1_EN_CLR 0xfffffffe
SD_RWC_LASTCNT_RESET 0x0
PM_GRAFX_V3DRSTN_SET 0x00000040
GP_FSEL6_FSEL61_CLR 0xffffffc7
SD_CS_DPD_CLR 0xfffffffb
OTP_CTRL_LO_REG_WIDTH 32
HDMI_RAM_PACKET_9_0_WIDTH 32
CM_AVEOCTL_BUSYD_LSB 8
USB_GUSBCFG_ULPI_AUTO_RES_LSB 18
ASB_H264_M_CTRL_RESET 0x00000007
SPI_FIFO_DATA_BITS 7:0
USB_DIEPTSIZ0_WIDTH 32
APERF1_BW0_CTRL_LATHALT_MSB 28
CMI_CAM1_RX3SRC_CLR 0xfffffcff
DMA5_CS_ABORT_SET 0x40000000
A2W_PLLC_ANA_KAIP_KP_BITS 3:0
DMA0_TXFR_LEN_YLENGTH_CLR 0xc000ffff
SH_HSTS_CRC7_ERROR_BITS 4:4
CM_CAM0CTL_FRAC_SET 0x00000200
USB_GUSBCFG_PHY_SEL_LSB 6
AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_CLR 0x7fffffff
CCP2TX_TD_IES_LSB 5
HD_CSC_32_31 0x7e808054:RW
USB_DCTL_GOUT_NAK_STS_MSB 3
A2W_SMPS_A_GAIN_DIGGAIN_LSB 0
DMA14_TI_WAIT_RESP_MSB 3
VCE_REASON_RUNNING 0x11
ARM_3_MAIL0_WRT (0x7E00B000 +0xB00)+0x80:RW
HDMI_RAM_PACKET_5_2_WIDTH 32
I2CS_ERR (1 << 8)
DMA7_TI_SRC_INC_BITS 8:8
SMI_DSR1_RWIDTH_CLR 0x3fffffff
SYSAC_UC_ARBITER_CONTROL_THRESHOLD_RESET 0x0
PCM_INTEN_A_TXERR_CLR 0xfffffffb
DMA8_CS_INT_CLR 0xfffffffb
A2W_PLLA_ANA_SSCS_RESET 0000000000
ASB_ISP_S_CTRL_CLR_REQ_MSB 0
AUX_MU_STAT_REG (0x7E215000 +0x064)
EMMC_IRPT_EN_CBAD_ERR_BITS 19:19
TXP_CTRL_TFORMAT_CLR 0xffffffdf
CM_INTEN_LOSSD_CLR 0xfffffeff
A2W_PLLC_CTRL_RESET 0x00010000
DMA10_CS_RESET 0000000000
CAM0_CAMCMP0_RESET 0000000000
CM_OTPCTL_RESET 0x00000011
AUX_ENABLE_SPI0 0x02
AVE_IN_CURRENT_LINE_NUM_INTERLACED_BITS 30:30
TB_JTB_CONFIG_INV_CLK_MSB 7
APERF0_BW0_CTRL_ID_SET 0x00001f00
HDMI_RAM_PACKET_1_4_WIDTH 32
USB_HPRT_EN_CHNG_CLR 0xfffffff7
DMA3_TI_WAITS_BITS 25:21
SD_SB_ROWBITS_SET 0x0000000c
USB_GINTMSK_IEP_INT_MSB 18
HDMI_VERTA1_MANUAL_VFP1_CLR 0xfff01fff
DMA11_CS_PRIORITY_SET 0x000f0000
GP_FSEL5_FSEL50_SET 0x00000007
USB_GHWCFG2_SINGLE_POINT_BITS 5:5
MPHI_INTSTAT_RX1DISC_CLR 0xfeffffff
A2W_PLLA_ANA_VCO_RANGE_CLR 0xfffffffe
APERF0_BW1_RTWAIT_RESET 0000000000
AUX_ENABLE_SPI1 0x04
CM_ISPDIV_WIDTH 16
DMA11_NEXTCONBK_ADDR_BITS 31:5
SMI_DSW3_WHOLD_SET 0x003f0000
APHY_CSR_PHY_BIST_CNTRL_SPR 0x7ee06080:RW
DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
A2W_PLLB_SP2_DIV_MSB 7
DMA2_TXFR_LEN_XLENGTH_SET 0x0000ffff
SD_CYC 0x7ee00030:RO
SMI_DSR1_RSTROBE_MSB 6
A2W_PLLA_ANA_VCOR_WIDTH 1
DSI1_LP_DLT7_RESET 0000000000
DMA12_CS_DREQ_STOPS_DMA_MSB 5
DMA0_TI_DEST_WIDTH_CLR 0xffffffdf
CAM0_CAMIPIPE_WIDTH 32
CM_INTEN_GAINA_MSB 0
A2W_PLLH_RCAL_DIV_LSB 0
EMMC_TUNE_STEPS_STD_STEPS_CLR 0xffffffc0
PM_AVS_INTEN_ALERT_SYSTEM_A_LSB 1
USB_HCINT0_CH_HLTD_LSB 1
L1_IC0_PRIORITY_IC0_APRIORITY0_CLR 0xfffffff0
HDMI_RAM_PACKET_3_1_RESET 0000000000
USB_DTXFSTS8_WIDTH 32
EMMC_CONTROL0_WAKE_ONREM_EN_CLR 0xfbffffff
SLIM_DCC5_CON_WIDTH 32
JCBA 0x7e005000 + 0x10:RW
L1_L1_SANDBOX_START5_START_ADDR_SET 0x3fffffe0
SMI_CS_ACTIVE_MSB 2
A2W_PLLH_DIG1R_WIDTH 24
A2W_SMPS_L_MULTI 0x7e102fd0:RW
CM_PLLA_DIGRST_SET 0x00000200
SD_SECSRT0_MASK 0xffffffff
HD_VID_CTL_BLANKPIX_BITS 18:18
CM_PULSECTL_FRAC_MSB 9
MULTICORE_SYNC_NUM_SEMAPHORES (32)
USB_GINTMSK_USB_RST_BITS 12:12
EMMC_BLKSIZECNT_BLKSIZE_MS1_LSB 15
PWM_STA_RERR1_LSB 3
CAM1_CAMDBG3_RESET 0000000000
USB_DTXFSTS9_MASK 0xffffffff
DMA10_CS_DISDEBUG_CLR 0xdfffffff
JMCTRL_422_MODE (1 << 14)
A2W_PLLH_CTRLR_WIDTH 18
UART_LSR_OE_MSB 1
SDTOUT SDCARD_BASE + 0x08:RW
DMA9_CS_DISDEBUG_MSB 29
EMMC_INTERRUPT_BLOCK_GAP_CLR 0xfffffffb
SH_HCFG_DATA_IRPT_EN_LSB 4
PIXELVALVE0_C_WIDTH 24
SMI_DSR2_RDREQ_CLR 0xffffff7f
CM_PLLTCTL_KILL_LSB 5
USB_DOEPDMAB0_WIDTH 32
HDMI_ASYNC_RM_CONTROL (HDMI_BASE_ADDRESS + 0x300) + 0:RW
APERF1_BW0_ATWAIT_RESET 0000000000
HDMI_SCHEDULER_CONTROL_ALWS_VERT_KEEPOUT_MSB 3
MPHI_MINFS_OFLOW_CLR 0x7fffffff
SMI_CS_INTR_MSB 11
EMMC_CONTROL2_SIGTYPE_LSB 19
A2W_HDMI_CTL_RCAL_RESET 0x00010000
MPHI_HSINDCF_LENGTH_RESET 0x0
DMA_ENABLE_EN7_CLR 0xffffff7f
I2C_SPI_SLV_ICR_BEIC_LSB 2
MPHI_OUTDDB_CHANNEL_LSB 28
EMMC_IRPT_MASK_CARD_OUT_BITS 7:7
DMA0_TI_DEST_DREQ_MSB 6
SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_CLR 0xfffffffc
DMA3_CS_DREQ_STOPS_DMA_MSB 5
USB_DOEPDMAB4_WIDTH 32
EMMC_CONTROL0_PWCTL_ON_LSB 8
AUX_MU_CNTL_FLOW2 0x10
SD_VIN_INT_EN_RESET 0x0
DMA_ENABLE 0x7e007ff0:RW
A2W_PLLH_RCAL_WIDTH 10
I2C_SPI_SLV_IFLS_TXIFLSEL_LSB 0
APERF1_BW0_ATRANS_RESET 0000000000
SD_DQLCRC5_RISE_RESET 0x0
HDMI_DETECTED_VERTA1_MANUAL_VSP1_LSB 20
CM_TDCLKEN_PLLCDIV2_BITS 6:6
AVE_IN_CTRL_BUF_SER_IRQ_EN_CLR 0xfffffff7
VPU_ARB_CTRL_UC_CHANNEL_INIBIT_CLR 0xffff00ff
PM_AVS_RSTDR_PERI_A_BITS 0:0
DMA7_DEBUG_LITE_BITS 28:28
USB_DOEPINT0_OUT_TKN_EP_DIS_MSB 4
USB_GOTGINT_HST_NEG_DET_BITS 17:17
PWM_CTL_USEF4_CLR 0xdfffffff
GP_DESCRIPTION "GPIO control"
SD_DQRCRC13_FALL_SET 0x0000ffff
FPGA_CTRL0_CAM_CTL0_BITS 0:0
SD_SF_POWSAV_T_RESET 0x040
SH_HSTS_CRC16_ERROR_CLR 0xffffffdf
AUX_MU_BDLS_REG (0x7E215000 +0x040)
ASB_CPR_CTRL_CLR_REQ_MSB 0
APERF0_GEN_CTRL_ENABLE_MSB 0
CM_INTEN_FLOSSA_MSB 14
A2W_PLLB_SP0_RESET 0x00000100
MPHI_INTSTAT_MASK 0xf9111111
HDMI_TST_AN0_RESET 0000000000
EMMC_FORCE_IRPT_CARD_IN_LSB 6
PWM_STA_GAPO3_LSB 6
A2W_PLLD_ANA_VCO_MASK 0x00000001
GP_FSEL1_FSEL16_LSB 18
DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
USB_GNPTXSTS_TX_Q_TOP_CLR 0x80ffffff
CCP2TX_TAC_APD_BITS 1:1
SD_DQRCRC6_RISE_BITS 31:16
DMA6_TI_WAIT_RESP_CLR 0xfffffff7
HD_VID_CTL_RST_FRAMEC_BITS 29:29
CM_TSENSCTL_FRAC_MSB 9
USB_GUSBCFG_PHY_LPWR_CLK_SEL_LSB 15
DMA0_DEBUG_FIFO_ERROR_BITS 1:1
I2C_BASE_2 0x7e805000
SD_SECEND3_ADDR_MS_BITS 31:13
SD_TMC_IPSEL_CLR 0xffffff8f
GROPCTR_TU0_CACHE_ACCESSES 0x11
ARM_AIS1_OPPEMPTY 0x00000200
SD_DQRCRC12_MASK 0xffffffff
MS_SEMA_24_MASK_SET 0x00000001
IC1_MASK7_WIDTH 31
A2W_PLLD_ANA1_RESET 0x001d0000
EMMC_DMA_STATUS_ERR_AT_LSB 0
SMI_DA_MASK 0x0000033f
SD_CARCRC_FALL_LSB 0
I2C_SPI_SLV_IFLS_RXIFLSEL_BITS 5:3
V3D_CT01RA0_WIDTH 32
USB_DOEPCTL1 0x7e980b20:RW
USB_DOEPCTL2 0x7e980b40:RW
USB_DOEPCTL3 0x7e980b60:RW
USB_DOEPCTL4 0x7e980b80:RW
USB_DOEPCTL5 0x7e980ba0:RW
USB_DOEPCTL6 0x7e980bc0:RW
SLIM_DCC6_PA0_MASK 0x00ffff1f
USB_DOEPCTL8 0x7e980c00:RW
USB_DOEPCTL9 0x7e980c20:RW
CAM0_CAMDLT_MASK 0xffffffff
CM_PERIICTL_GATE_CLR 0xffffffbf
DMA11_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
DMA_INT_STATUS_INT4_SET 0x00000010
HDMI_DVO_TIMING_ADJUST_D_WIDTH 32
I2C_SPI_SLV_APB_ID 0x73506783
FPGA_CTRL0_SW_SPI_SCL_LSB 6
USB_DIEPDMAB6_MASK 0xffffffff
DMA9_CS_RESET 0000000000
DMA13_NEXTCONBK_ADDR_CLR 0x0000001f
L1_L1_SANDBOX_START5_MASK 0x3fffffff
JQWDATA 0x7e005000 + 0x44:RW
CM_OTPCTL_ENAB_CLR 0xffffffef
GP_FSEL6_FSEL69_BITS 29:27
CM_TSENSCTL_BUSYD_LSB 8
DMA4_TI_DEST_INC_LSB 4
SCALER_DISPECTRL_Y_BUSY_MSB 31
A2W_PLLB_FRAC_FRAC_CLR 0xfff00000
PCM_CS_A 0x7e203000:RW
A2W_PLLA_ANA_SSCL_LIMIT_BITS 21:0
V3D_DBSDR2_WIDTH 32
DMA6_STRIDE_D_STRIDE_CLR 0x0000ffff
I2C_SPI_SLV_DMACR_TXDMAE_SET 0x00000002
USB_DCFG_DESC_DMA_RESET 0x0
ST_CS_MASK 0xffffffff
SD_CS_SREF2RUN_LSB 8
I2C_SPI_SLV_MIS_TXMIS_BITS 1:1
HDMI_CEC_TX_DATA_4_WIDTH 32
VCE_DATA_MEM_OFFSET 0
HDMI_VERTB1_MASK 0x003fffff
HDMI_DVO_TIMING_ADJUST_C_MASK 0xffffffff
MPHI_INTSTAT_IMFOFLW_RESET 0x0
TB_BOOT_OPT_ELPIDA_MSB 4
SD_REORD_WIDTH 28
EMMC_IRPT_MASK_INT_A_SET 0x00000200
USB_GAHBCFG_GLBL_INTR_MSK_BITS 0:0
CM_TIMERCTL_KILL_SET 0x00000020
HDMI_RAM_GCP_4_MASK 0xffffffff
SCALER_DISPECTRL_GT8_BURST_SET 0xff000000
DMA5_CS_INT_CLR 0xfffffffb
PM_PADS4_HYST_LSB 3
A2W_PLLD_ANA_KAIP_RESET 0x0000033a
GRTDIM7 0x1A0052E0 + 0x08:RW
I2C_SPI_SLV_FR_RXFLEVEL_MSB 15
USB_GNPTXFSIZ_NP_TXF_ST_ADDR_BITS 15:0
CM_VPUCTL_SRC_SET 0x0000000f
L1_L1_SANDBOX_START6_RESET 0000000000
EMMC_TUNE_STEP_DELAY_BITS 2:0
PCM_RXC_A_CH2EN_MSB 14
DMA_TI_PER_MAP(n) MACRO
DMA14_DEBUG_VERSION_CLR 0xf1ffffff
EMMC_EXRDFIFO_CFG 0x7e300080:RW
DMA13_DEBUG_DMA_STATE_CLR 0xfe00ffff
USB_HFIR_WIDTH 16
DSI1_RXPKT2_H 0x7e700018:RO
TB_JTB_CONFIG_TMS_RISE_LSB 8
DMA11_TI_INTEN_SET 0x00000001
UART_MSR_DDSR_CLR 0xfffffffd
MPHI_OUTDDB_TENDINT_RESET 0x0
DMA0_TI_NO_WIDE_BURSTS_MSB 26
TXP_DST_PITCH_WIDTH 32
USB_GI2CCTL_ADDR_CLR 0xff80ffff
A2W_PLLC_ANA_MULTI_WIDTH 0
CM_TDCLKEN_PLLBBYP_SET 0x00000002
CM_ISPDIV_DIV_CLR 0xffff000f
ASB_CPR_CTRL_CLR_ACK_MSB 1
MPHI_C0INDS_WIDTH 32
DMA13_DEBUG_OUTSTANDING_WRITES_MSB 7
DMA15_CS_DREQ_LSB 3
A2W_PLLA_CTRL_PWRDN_SET 0x00010000
SLIM_DCC1_STAT_WIDTH 32
EMMC_INTERRUPT_CCRC_ERR_CLR 0xfffdffff
HDMI_HORZA_MANUAL_HPOL_SET 0x00002000
CM_PULSECTL_ENAB_LSB 4
PM_PROC_MEMREP_CLR 0xfffffff7
CAM1_CAMICC 0x7e801130:RW
CM_CAM0DIV_WIDTH 16
DMA0_STRIDE_D_STRIDE_LSB 16
APERF1_BW2_CTRL_RESET_SET 0x80000000
USB_GUSBCFG 0x7e98000c:RW
AVE_IN_STATUS_RESET 0000000000
DMA4_NEXTCONBK_ADDR_CLR 0x0000001f
SCALER_DISPSTAT_DMA_ERR_BIT0_MSB 31
CAM1_CAMICS 0x7e801134:RW
CAM1_CAMIDS_WIDTH 32
HDMI_FIFO_CTL_RESET 0000000000
CM_CAM1CTL_BUSY_SET 0x00000080
CM_BURSTCTL_KILL_MSB 5
CM_CKSM_CFG_LSB 16
DMA3_CS_INT_BITS 2:2
DMA6_CS_PAUSED_LSB 4
AVE_OUT_CTRL_NTSC_PAL_IDENT_CLR 0xffffdfff
CAM1_CAMIDC 0x7e801138:RW
L1_L1_SANDBOX_START3_START_ADDR_LSB 5
SD_SD_T_RAS_MSB 12
EMMC_ARG1_MASK 0xffffffff
HDMI_MAI_FORMAT 0x7e902098:RW
USB_HCTSIZ7_WIDTH 32
AVE_IN_FRAME_NUM_FRAME_NUM_LSB 0
DMA0_STRIDE_MASK 0xffffffff
DSI0_PHYC_txhsclk_cont_sync_CLR 0xfffffbff
EMMC_CONTROL2_UHSMODE_LSB 16
MPHI_C1INDDB_LENGTH_CLR 0xfff00000
CM_H264CTL_BUSY_LSB 7
DMA10_TI_DEST_DREQ_MSB 6
EMMC_BUS_CTRL_RESET 0000000000
HDMI_TX_PHY_HDMI_TX_PHY_STATUS (HDMI_BASE_ADDRESS + 0x2c0) + 24:RW
HD_CSC_22_21_WIDTH 32
DMA3_CS_ABORT_LSB 30
MPHI_HSINDDB_LENGTH_RESET 0x0
GP_SET1_WIDTH 32
EMMC_INTERRUPT_TUNE_ERR_CLR 0xfbffffff
PM_RSTC_FRCFG_BITS 17:16
OTP_CTRL_LO_REG 0x7e20f008:RW
HD_HDM_CTL_ENABLE_RESET 0x0
USB_GHWCFG4_EN_DESC_DMA_CLR 0xbfffffff
CM_DSI0ECTL_FRAC_CLR 0xfffffdff
A2W_PLLB_SP1R_MASK 0x000003ff
FPGA_CTRL0_DIS_RST_BITS 3:3
CAM1_CAMIBEA0_RESET 0000000000
PWM_DMAC_WIDTH 32
TB_JTB_CONFIG_OUT_MS_SET 0x00000040
USB_DOEPDMA13_MASK 0xffffffff
APERF1_BW2_CTRL_LATHALT_CLR 0xefffffff
SLIM_DMA_DC9_WIDTH 32
PWM_FIF1_RESET 0000000000
CM_TSENSCTL_ENAB_LSB 4
MPHI_INTCTRL_IMFOFLW_RESET 0x0
DMA5_TI_SRC_DREQ_CLR 0xfffffbff
INTERRUPT_SLIMBUS ((64) + 52 )
HDMI_RAM_PACKET_10_0 0x7e902568:RW
HDMI_RAM_PACKET_10_1 0x7e90256c:RW
SD_DQLCRC2_RISE_RESET 0x0
HDMI_RAM_PACKET_10_3 0x7e902574:RW
USB_DOEPINT0_IN_TKN_TXFEMP_CLR 0xffffffef
HDMI_RAM_PACKET_10_5 0x7e90257c:RW
HDMI_RAM_PACKET_10_6 0x7e902580:RW
HDMI_RAM_PACKET_10_7 0x7e902584:RW
HDMI_RAM_PACKET_10_8 0x7e902588:RW
SMI_DSW3_WSETUP_SET 0x3f000000
CM_ISPCTL_SRC_LSB 0
EMMC_IRPT_MASK_RETUNE_LSB 12
CAM1_CAMDBG1_WIDTH 32
APHY_CSR_ADDR_PVT_COMP_OVRD_CTRL 0x7ee06074:RW
DSI1_HS_CLT0 0x7e700050:RW
DSI1_HS_CLT1 0x7e700054:RW
L1_L1_SANDBOX_START2_MASK 0x3fffffff
USB_DOEPCTL0_SET_D1_PID_CLR 0xdfffffff
PIXELVALVE2_VERTB_EVEN_WIDTH 32
USB_GNPTXSTS_TXF_SPC_AVAIL_MSB 15
TB_BOOT_OPT_TB_PRESENT_LSB 31
EMMC_CONTROL2_ACTO_ERR_CLR 0xfffffffd
VPU_ARB_CTRL_UC_ALGORITHM_LSB 6
DMA11_TI_SRC_DREQ_SET 0x00000400
EMMC_CONTROL0_GAP_RESTART_SET 0x00020000
PCM_RXC_A_CH2WID_CLR 0xfffffff0
CM_AVEOCTL_BUSY_SET 0x00000080
SMIDC_PANICR 18
DMA9_DEBUG 0x7e007920:RW
DMA10_TI_SRC_INC_SET 0x00000100
SMIDC_PANICW 12
SD_TMC_TSTPAT_MSB 31
DSI1_HS_DLT5 0x7e700064:RW
MPHI_C1INDS_VALID_MSB 30
MPHI_C1INDFS_CFIFOLVL_BITS 31:16
GP_FEN0_WIDTH 32
MS_SEMA_28_MASK_BITS 0:0
SYSAC_DUMMY_STATUS_RESET 0000000000
DMA6_DEBUG_DMA_ID_SET 0x0000ff00
CM_ISPDIV_MASK 0x0000fff0
SMI_DSR1_RHOLD_BITS 21:16
A2W_SMPS_C_CLK_USEOSC_BITS 2:2
UEN 0x7e201000 + 0x20:RW
VEC_CGMSAE_BOT_DATA_WIDTH 32
GP_FSEL5_FSEL55_MSB 17
A2W_PLLA_ANA1_RESET 0x001d0000
FPGA_CTRL0_CAM_CTL1_MSB 1
HD_CSC_CTL_ENABLE_RESET 0x0
DMA8_TI_SRC_INC_BITS 8:8
HDMI_RAM_PACKET_12_3_MASK 0xffffffff
ASB_CPR_CTRL_FULL_CLR 0xfffffff7
CAM1_CAMDBEA0_WIDTH 32
A2W_HDMI_CTL0R_MASK 0x00ffffff
USB_GHWCFG4_EN_SESSIONEND_FILTER_CLR 0xfeffffff
PCM_INTEN_A_WIDTH 4
PWM_CTL_PWEN1_CLR 0xfffffffe
PCM_RXC_A_CH1POS_MSB 29
USB_DOEPCTL8_WIDTH 32
APERF1_GEN_CTRL_ENABLE_RESET 0x0
DMA7_CS_DREQ_STOPS_DMA_MSB 5
DMA4_STRIDE_S_STRIDE_LSB 0
L1_D0_RD_THRUS_MASK 0000000000
SD_SECSRT0_ADDR_MS_MSB 31
TS_TSENSCTL_CTRL_MSB 4
DMA_CS_WAITING_FOR_LAST_WRITE (1<<6)
AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_CLR 0xdfffffff
SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_MSB 5
TB_HOST_MASK 0xffffffff
APERF1_BW0_WMAX_MASK 0x00ffffff
MPHI_MINFS_LEVEL_SET 0x000003ff
USB_DIEPCTL0_SET_D1_PID_CLR 0xdfffffff
SD_MR_DONE_SET 0x80000000
EMMC_FORCE_IRPT_TUNE_ERR_MSB 26
DMA3_CS_ABORT_BITS 30:30
SMIDC_DMAEN 28
DMA12_CS_PRIORITY_SET 0x000f0000
CCP2TX_TD_TCS_SET 0x0000001f
ASB_V3D_M_CTRL_RCOUNT_CLR 0xffffc00f
APERF0_BW1_WMAX_RESET 0000000000
ASB_V3D_M_CTRL_CLR_REQ_SET 0x00000001
DMA0_CS_DREQ_CLR 0xfffffff7
CAM1_CAMMISC 0x7e801400:RW
SD_WDC_MASK 0x0fffffff
SD_DQLCRC2_RISE_LSB 16
CM_PERIICTL 0x7e101020:RW
HDMI_RAM_PACKET_7_0_MASK 0xffffffff
DMA2_CS_INT_CLR 0xfffffffb
HDMI_RAM_PACKET_5_8_RESET 0000000000
CM_GP2CTL_BUSY_CLR 0xffffff7f
SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_BITS 7:6
SMI_DSW2_WPACE_SET 0x00007f00
SYSAC_DUMMY_STATUS_MASK 0x00000001
A2W_PLLC_ANA0 0x7e102030:RW
A2W_PLLC_ANA1 0x7e102034:RW
A2W_PLLC_ANA2 0x7e102038:RW
UART_MSR_DCTS_LSB 0
DMA4_DEBUG_FIFO_ERROR_BITS 1:1
DMA13_CS_INT_MSB 2
HD_VID_CTL_VPOL_RESET 0x0
GP_FSEL6_FSEL65_SET 0x00038000
PCM_RXC_A_CH2EN_BITS 14:14
SD_DQLCRC0_RISE_LSB 16
CAM0_CAMDAT3_MASK 0xffffffff
USB_DOEPCTL0_TYPE_LSB 18
USB_DIEPDMAB2_MASK 0xffffffff
CM_OSCCOUNT_NUM_BITS 23:0
DMA4_DEBUG_READ_ERROR_LSB 2
CM_GNRICCTL_BUSYD_MSB 8
A2W_PLLD_ANA_SSCS_MODE_MSB 16
DMA2_TI_DEST_DREQ_CLR 0xffffffbf
MPHI_C1INDS_HANDLE_BITS 28:21
EMMC_INTERRUPT_ACMD_ERR_SET 0x01000000
PM_CCP2TX_CTRLEN_LSB 0
SD_MR_RDATA_SET 0x00ff0000
A2W_PLLA_CTRL_PDIV_CLR 0xffff8fff
HDMI_TEST_WIDTH 12
USB_HPRT_CONN_DET_RESET 0x0
SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_CLR 0xffffffcf
DMA3_TI_SRC_INC_SET 0x00000100
EMMC_CONTROL0_HCTL_CRDDET_SET 0x00000040
APERF0_BW0_CTRL_BUS_BITS 4:0
USB_GINTMSK_INCOMPL_ISO_OUT_BITS 21:21
HDMI_BKSV1_MASK 0xffffffff
VPU_ARB_CTRL_UC_THRESHOLD_BITS 5:4
MS_SEMA_19_RESET 0000000000
HDMI_READ_POINTERS_DRFT_WR_ADDR_SET 0x0000ff00
USB_DIEPTXF11_WIDTH 32
CM_DSI0PCTL_ENAB_CLR 0xffffffef
CM_H264CTL_KILL_MSB 5
USB_HCSPLT7_WIDTH 32
CM_TECCTL_BUSYD_LSB 8
PCM_CS_A_RXR_MSB 18
DMA11_CS_DISDEBUG_CLR 0xdfffffff
CM_EVENT_LOSSC_MSB 7
HDMI_RAM_PACKET_7_0 0x7e9024fc:RW
HDMI_RAM_PACKET_7_1 0x7e902500:RW
HDMI_RAM_PACKET_7_2 0x7e902504:RW
HDMI_RAM_PACKET_7_3 0x7e902508:RW
HDMI_RAM_PACKET_7_4 0x7e90250c:RW
HDMI_RAM_PACKET_7_5 0x7e902510:RW
HDMI_RAM_PACKET_7_6 0x7e902514:RW
HDMI_RAM_PACKET_7_7 0x7e902518:RW
DMA2_TI_SRC_IGNORE_SET 0x00000800
DMA0_CS 0x7e007000:RW
DMA5_TI_DEST_IGNORE_CLR 0xffffff7f
SMI_CS_RXF_SET 0x80000000
SYSAC_H264_PRIORITY_PRIORITY_BITS 3:0
DSI0_PHYC_txulpshs_1_sync_SET 0x00000040
CM_BURSTCTL_BUSY_SET 0x00000080
CM_INTEN_LOSSH_SET 0x00000200
DMA4_TI_BURST_LENGTH_SET 0x0000f000
CM_PLLD_ANARST_MSB 8
SD_CYC_WIDTH 28
EMMC_IRPT_EN_BLOCK_GAP_BITS 2:2
SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_BITS 2:0
FPGA_SCRATCH_MASK 0xffffffff
SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_MSB 7
SD_CS_DEL_KEEP_MSB 18
HDMI_DETECTED_HORZB_MASK 0x3ffffe00
A2W_PLLH_DIG1_MASK 0x00ffffff
MPHI_OUTDS_WORDS_CLR 0xffe00000
GP_SEN1_MASK 0x003fffff
APERF0_BW1_CTRL_RESET_LSB 31
DMA6_CS_ERROR_CLR 0xfffffeff
USB_GRSTCTL_INT_TKN_Q_FLSH_RESET 0x0
CM_V3DDIV_DIV_MSB 15
APERF0_BW1_CTRL_LATHALT_MSB 28
PWM_DMAC_ENAB_MSB 31
PCM_CS_A_TXD_MSB 19
AVE_OUT_CR_COEFF_RED_COEFF_LSB 20
USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_CLR 0x7fffffff
DMA15_DEBUG_LITE_LSB 28
APHY_CSR_GLBL_ADDR_DLL_RESET 0x7ee06004:RW
SD_DQRCRC15_RISE_MSB 31
USB_GHWCFG3_RM_OPT_FEATURES_BITS 10:10
CM_SDCCTL_BUSY_BITS 7:7
USB_GINTSTS_WIDTH 32
USB_DOEPCTL15_WIDTH 32
GP_HEN1_HENn32_MSB 31
UNICAM_DCS(x) MACRO
DMA11_CS_RESET_BITS 31:31
EMMC_ARG2 0x7e300000:RW
SD_DMRCRC1_WIDTH 32
DMA_INT_STATUS_INT11_BITS 11:11
USB_HCSPLT0_HUB_ADDR_MSB 13
PCMCS_TXTHR_LSB 5
A2W_PLLC_CORE1R_MASK 0x000003ff
V3D_DBSDR1_WIDTH 32
DMA4_TI_NO_WIDE_BURSTS_MSB 26
USB_DIEPCTL12_MASK 0xffffffff
DMA1_DEST_AD_D_ADDR_CLR 0x00000000
USB_GI2CCTL_BSY_DNE_CLR 0x7fffffff
PM_AVS_EVENT_RESET 0000000000
DMA11_CS 0x7e007b00:RW
CM_DSI0PDIV_RESET 0x00001000
GP_FSEL5_FSEL51_LSB 3
CMI_CAM1_HSSRC_CLR 0xfffffffc
SMI_DSR2_RHOLD_BITS 21:16
AUX_MU_MCR_RTS 0x02
PCM_TXC_A_CH2WID_MSB 3
A2W_PLLD_DIG0R_MASK 0x00ffffff
HDMI_HORZA_MANUAL_VPOL_SET 0x00004000
HDMI_TX_PHY_TX_PHY_PLL_CFG_RESET 0x07f80112
USB_DOEPINT0_XFER_COMPL_BITS 0:0
VEC_CONFIG0_MASK 0xffffffff
DMA15_NEXTCONBK_ADDR_CLR 0x0000001f
SD_DQRCRC2_RISE_LSB 16
DMA10_CS_ABORT_BITS 30:30
CAM0_CAMDBWP_RESET 0000000000
SPI_CS_DONE_CLR 0xfffeffff
GROPCTR_TU0_SAME_SET_STALL 0x0E
AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_CLR 0x7fffffff
EMMC_IRPT_MASK_DATA_DONE_CLR 0xfffffffd
CAM1_CAMISTA_RESET 0000000000
EMMC_CONTROL1_CLK_STABLE_BITS 1:1
MS_SEMA_4_MASK_MSB 0
DMA1_DEST_AD_D_ADDR_BITS 31:0
CSI2_RDEA0 CSI2_BASE_ADDRESS + 0x124:RW
APERF0_BW1_CTRL_BUS_CLR 0xffffffe0
DMA2_TXFR_LEN_XLENGTH_BITS 15:0
DMA13_DEST_AD_D_ADDR_CLR 0x00000000
GR_VPM_VRFCFG_ADDR_MASK 0x00000003
MS_MBOX_5_MBOX_SET 0xffffffff
CM_TECCTL_BUSY_MSB 7
FPGA_DCM_CTRL_PERI_RST_LSB 16
USB_DCTL_TST_CTL_SET 0x00000070
A2W_SMPS_A_GAINR 0x7e102ba0:RW
MPHI_C1INDDB_TENDINT_CLR 0xdfffffff
MPHI_INTSTAT_RX1TEND_CLR 0xffffefff
EMMC_IRPT_MASK_DMA_ERR_SET 0x10000000
PM_HDMI_LDOPD_LSB 1
EMMC_IRPT_EN_CARD_LSB 8
CM_TD0CTL_FRAC_LSB 9
EMMC_INTERRUPT_CMD_DONE_MSB 0
PM_PADS3_SLEW_SET 0x00000010
USB_GUSBCFG_PHY_LPWR_CLK_SEL_BITS 15:15
USB_GUSBCFG_HNP_CAP_LSB 9
A2W_SMPS_L_SIAR_WIDTH 10
USB_DIEPDMA1_WIDTH 32
PM_AVS_EVENT_ALERT_H264_I_CLR 0xfffffffb
DMA10_TI_DEST_IGNORE_SET 0x00000080
GP_HEN0_HENn0_SET 0xffffffff
HDMI_CEC_CNTRL_5_RESET 0x004cfff5
PM_DSI1_LDOLPEN_SET 0x00000002
CCP2TX_TAC_CLAC_BITS 23:16
USB_GI2CCTL_BSY_DNE_BITS 31:31
DMA1_TI_SRC_WIDTH_SET 0x00000200
MPHI_MOUTFS_UFLOW_CLR 0x7fffffff
A2W_PLLA_CTRL_NDIV_BITS 9:0
UART_IERDLM 0x7e201004:RW
A2W_PLLH_ANA2_MASK 0x00ffffff
SD_RWC_RSTMAX_SET 0x80000000
MPHI_MINFS_MASK 0xbfffffff
CM_CKSM_AUTO_SET 0x00100000
I2C_SPI_SLV_RSR_TXDMAPREQ_MSB 2
DMA4_CS_ACTIVE_BITS 0:0
I2C_SPI_SLV_RSR_RXDMAPREQ_MSB 4
HDMI_RAM_PACKET_10_8_WIDTH 32
HDMI_CTS_1_RESET 0000000000
APHY_CSR_ADDR_PVT_COMP_STATUS 0x7ee06078:RW
HDMI_DETECTED_HORZA_MANUAL_HAP_CLR 0xffffe000
A2W_PLLD_ANA0R 0x7e102850:RW
HDMI_TX_PHY_TX_PHY_PLL_CFG 0x7e9022d0:RW
CM_GP2CTL_ENAB_SET 0x00000010
SCALER_DISPSTAT_DSP2_STATUS_LSB 24
A2W_HDMI_CTL_RCAL_MANR_MSB 11
CCP2TX_TPC_RESET 0000000000
MPHI_C0INDDB_WIDTH 32
HDMI_RAM_PACKET_9_4_MASK 0xffffffff
SD_PHYC_IOB_TMODE_LSB 12
L1_IC0_FLUSH_E_RESET 0xffffffff
DMA13_SOURCE_AD_S_ADDR_CLR 0x00000000
USB_DIEPTXF15_MASK 0xffffffff
HDMI_RAM_PACKET_3_3_MASK 0xffffffff
HDMI_RAM_GCP_7_RESET 0000000000
EMMC_CONTROL2_NOTC12_ERR_BITS 7:7
USB_DCTL_IGN_FRM_NUM_SET 0x00008000
DMA_INT_STATUS_INT3_BITS 3:3
CM_CAM1CTL_SRC_MSB 3
L1_L1_SANDBOX_START1_CTRL_CLR 0xfffffffe
A2W_PLLA_DIG1R_RESET 0x00004000
CMI_CAMTEST_ENAB_SET 0x00000010
SMI_DSR3_RDREQ_LSB 7
A2W_PLLD_ANA1R 0x7e102854:RW
USB_GHWCFG2_DFIFO_DYNAMIC_BITS 19:19
CM_EVENT_LOSSA_BITS 5:5
MPHI_MINFS_WPTR_BITS 19:10
CM_TCNTCNT 0x7e1010c4:RW
PM_PROC_ENAB_SET 0x00001000
EMMC_FORCE_IRPT_CCRC_ERR_BITS 17:17
USB_GI2CCTL_RW_DATA_RESET 0x0
A2W_PLLD_ANA_MULTI_WIDTH 0
GP_AFEN1_AFENn32_LSB 0
A2W_XOSC_MULTI_MASK 0000000000
A2W_PLLH_CTRL_PDIV_LSB 12
DMA9_TI_INTEN_BITS 0:0
CM_OTPCTL_FRAC_SET 0x00000200
SH_HSTS 0x7e202020:RW
WOGLPTR 0x1820FFFC:RW
L1_L1_SANDBOX_START2_START_ADDR_BITS 29:5
A2W_PLLD_DIG0_MASK 0x00ffffff
SMIDS_MODE68 23
PCM_DREQ_A_TX_PANIC_SET 0x7f000000
CM_PCMCTL_SRC_CLR 0xfffffff0
VPU1_THREAD_CTRL_BASE_ADDRESS 0xffffffff:RW
DMA14_NEXTCONBK_WIDTH 32
SH_EDM_READ_THRESHOLD_CLR 0xfff83fff
PCMDREQ_TXPANICTHR_LSB 24
USB_DSTS_ENUM_SPD_RESET 0x0
ASB_H264_M_CTRL_RCOUNT_CLR 0xffffc00f
USB_DIEPTSIZ7_MASK 0xffffffff
USB_GUSBCFG_TOUT_CAL_RESET 0x0
A2W_PLLD_ANA2R 0x7e102858:RW
SLIM_DMA_DC0 0x7e210030:RW
SLIM_DMA_DC1 0x7e210034:RW
SLIM_DMA_DC2 0x7e210038:RW
SLIM_DMA_DC3 0x7e21003c:RW
SLIM_DMA_DC4 0x7e210040:RW
SLIM_DMA_DC5 0x7e210044:RW
SLIM_DMA_DC6 0x7e210048:RW
SLIM_DMA_DC7 0x7e21004c:RW
SLIM_DMA_DC8 0x7e210050:RW
SLIM_DMA_DC9 0x7e210054:RW
EMMC_HWCAP0_XMEDBUS_CLR 0xfffbffff
SD_SECSRT2_ADDR_LS_LSB 1
FPGA_CTRL0_SPI1_SEL_BITS 10:10
PM_CCP2TX_LDOEN_SET 0x00000002
SD_SC_T_WR_BITS 11:8
VEC_ENC_RevID 0x7e806060:RW
DMA10_CS_INT_MSB 2
PIARBCTL_CAM_CHANNEL_INIBIT_LSB 8
USB_DFIFO6_WIDTH 32
AVE_IN_FRAME_NUM_FRAME_NUM_SET 0x00000fff
I2C2_DEL 0x7e805018:RW
SMI_DSR2_MODE68_SET 0x00800000
DMA10_TI_BURST_LENGTH_BITS 15:12
USB_GHWCFG3_DFIFO_DEPTH_BITS 31:16
SMIDS_STROBE 0
CAM1_CAMIPIPE_MASK 0xffffffff
SMI_DSR0_RPACE_SET 0x00007f00
DMA_INT_STATUS_INT5_LSB 5
PM_PADS6_WIDTH 9
A2W_HDMI_CTL3R_RESET 0x00000040
DMA_INT_STATUS_INT6_MSB 6
USB_DIEPTXF5_WIDTH 32
USB_DIEPTSIZ0_XFERSIZE_LSB 0
SD_DQLCRC7_RISE_LSB 16
PM_PADS5_SLEW_BITS 4:4
HD_VID_CTL_EMPSYNC_SET 0x00100000
USB_DTXFSTS0_WIDTH 32
CM_VPUCTL_BUSYD_CLR 0xfffffeff
CM_PLLD_HOLDPER_SET 0x00000080
DMA12_TI_INTEN_MSB 0
SLIM_DMA_DC3_RESET 0000000000
USB_GUSBCFG_ULPI_FS_LS_SET 0x00020000
GP_AREN2_ARENn64_BITS 5:0
CAM1_CAMIBLS_WIDTH 32
PM_AVS_STAT_ALERT_ARM_P_LSB 4
SDHBCT SDCARD_BASE + 0x3C:RW
DMA3_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
SYSAC_V3D_PRIORITY_RESET 0000000000
FPGA_CTRL0_SPARE_OUT_LSB 20
DMA9_CS_INT_MSB 2
CCP2TX_TTC_LCN_CLR 0xfffffff0
CM_PLLA_ANARST_MSB 8
DMA9_TI_SRC_IGNORE_MSB 11
DMA5_CS_PAUSED_MSB 4
GP_FSEL0_FSEL03_MSB 11
DMA7_CS_DISDEBUG_BITS 29:29
MPHI_C1INDS_DISCARD_RESET 0x0
CM_EVENT_BURSTDONE_LSB 23
USB_GRXSTSP_HST_CH_NUM_SET 0x0000000f
USB_DFIFO11_WIDTH 32
GP_FSEL2_FSEL24_CLR 0xffff8fff
A2W_XOSC_CPR_MASK 0x00000013
DMA10_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
A2W_PLLD_ANA1_MASK 0x00ffffff
SLIM_DCC3_PA0_RESET 0000000000
SD_PHYC_CRC_EN_SET 0x00100000
DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
MPHI_OUTDDA_START_BITS 31:0
SD_SECSRT0_EN_SET 0x00000001
GRDAADR4 0x1A005A00 + 0x50:RW
A2W_SMPS_CTLB0R_WIDTH 24
UART_LCR_RTS_LSB 1
VEC_WSE_WSS_DATA_MASK 0xffffffff
HDMI_MAI_CHANNEL_MAP_WIDTH 24
SPI_CS_TXD_BITS 18:18
DMA0_TI_DEST_INC_MSB 4
SD_DQLCRC6_RISE_RESET 0x0
DMA8_DEBUG_FIFO_ERROR_BITS 1:1
L2_L2_ALIAS_EXCEPTION_ADDR_RESET 0000000000
V3D_RFC_WIDTH 8
TB_JTB_CONFIG_TRSTN_BITS 14:14
CM_PWMCTL_SRC_MSB 3
CAM1_CAMDBCTL_MASK 0xffffffff
SYSAC_JPEG_PRIORITY 0x7e009014:RW
A2W_PLLC_DIG3 0x7e10202c:RW
DMA12_TI_SRC_DREQ_SET 0x00000400
DMA_ENABLE_EN1_MSB 1
EMMC_SPI_INT_SPT_SELECT_SET 0x000000ff
IFORCE1_1 0xffffffff:RW
PM_PROC_POWUP_LSB 0
MPHI_CTRL_ENABLE_BITS 31:31
A2W_PLLA_DIG0R_MASK 0x00ffffff
SYSAC_PERI_ARBITER_CONTROL_DELAY_LSB 2
A2W_PLLH_ANA_STAT_RCALDONE_CLR 0xffffefff
L1_L1_SANDBOX_END0_MASK 0x3fffffe0
GP_REN1_RENn32_CLR 0x00000000
USB_GUSBCFG_FORCE_DEV_MODE_BITS 30:30
SYSAC_PERI_ARBITER_CONTROL_MASK 0x0000ffff
DMA_CB_TI(n) MACRO
HDMI_DETECTED_HORZB_MANUAL_HFP_BITS 9:9
CCP2TX_TD_MASK 0x000000ff
PIXELVALVE2_VERTA_WIDTH 32
DMA11_TI_SRC_WIDTH_SET 0x00000200
USB_DAINT_IN_EP_INT_MSB 15
USB_GINTMSK_CON_ID_STS_CHNG_CLR 0xefffffff
EMMC_HWCAP0_MAXLEN_MSB 17
SH_ARG_ARGUMENT_CLR 0x00000000
FPGA_CTRL0_DIS_SW_SPI_CLR 0xffffffdf
EMMC_HWCAP1_SPI_BLOCKMODE_LSB 25
HDMI_CP_STATUS_MASK 0x8000031f
HDMI_RAM_PACKET_5_7_MASK 0xffffffff
SD_DQRCRC9_RISE_LSB 16
SYSAC_V3D_LIMITER_SPARE_CLR 0xfffffff1
DMA_ENABLE_EN13_BITS 13:13
GP_FSEL1_FSEL13_SET 0x00000e00
APERF0_BW0_CTRL_ID_EN_SET 0x20000000
DMA9_TI_SRC_INC_BITS 8:8
CM_PLLA_LOADDSI0_SET 0x00000001
USB_DIEPCTL0_STALL_BITS 21:21
DMA_CB_TL(n) MACRO
A2W_PLLH_FRAC_FRAC_MSB 19
MPHI_OUTDFS_DFIFOLVL_SET 0x0000ffff
SD_SECSRT0_ADDR_LS_BITS 12:1
DMA8_CONBLK_AD 0x7e007804:RW
SCALER_DISPBKGND1 0x7e400054:RW
DMA12_TI_SRC_IGNORE_MSB 11
PM_HDMI_LDOPD_MSB 1
DMA13_CS_ERROR_MSB 8
MPHI_INTSTAT_HSDCFOFLW_MSB 27
SD_DQLCRC1_RISE_BITS 31:16
I2C2_DIV 0x7e805014:RW
CM_TD0CTL_FLIP_CLR 0xfffff7ff
DMA5_CS_ACTIVE_SET 0x00000001
DMA3_TXFR_LEN_XLENGTH_MSB 15
AVE_OUT_Y_COEFF_RED_COEFF_LSB 20
SYSAC_DBG_PRIORITY 0x7e009004:RW
MPHI_RXAXICFG_MASK 0x0001ffff
DMA13_CS_PRIORITY_SET 0x000f0000
GP_HEN2 0x7e20006c:RW
USB_DPTXFSIZ2_WIDTH 32
L2_CONT_OFF_l2_no_wr_allocate_BITS 1:1
ARM_MC_IHAVEDATAIRQEN 0x00000001
CM_TCNTCTL 0x7e1010c0:RW
MPHI_C1INDDB_MORUN_LSB 31
EMMC_INTERRUPT_CARD_IN_MSB 6
MPHI_C0INDDB_TENDINT_BITS 29:29
SYSAC_JPEG_PRIORITY_MASK 0x000000ff
SD_VIN_INT_EN_CLR 0xefffffff
TB_JTB_CONFIG_TDO_RISE_LSB 10
MPHI_CTRL_STBY_SET 0x08000000
USB_GINTSTS 0x7e980014:RW
SD_DQLCRC0_FALL_SET 0x0000ffff
CMI_CAM1_RX0SRC_BITS 3:2
EMMC_INTERRUPT_CARD_MSB 8
IS_ALIAS_DIRECT(x) MACRO
PWM_CTL_PWEN4_MSB 24
EMMC_HWCAP0_RESUME_BITS 23:23
HDMI_CEC_RX_DATA_1_RESET 0000000000
A2W_SMPS_L_SIA_MASK 0x000003ff
EMMC_DMA_STATUS_WIDTH 32
A2W_PLLB_ARMR 0x7e102be0:RW
EMMC_FORCE_IRPT_READ_RDY_MSB 5
PCMMODE_FSLEN 0
A2W_PLLB_ANA3R_WIDTH 24
DMA6_TXFR_LEN_XLENGTH_BITS 15:0
CM_HSMCTL_ENAB_MSB 4
EMMC_BUS_CTRL_IRQSEL_MSB 22
GP_SEN0_SEN_SET 0xffffffff
USB_GINTMSK_GOUT_NAK_EFF_SET 0x00000080
JC1BA 0x7e005000 + 0x50:RW
MS_SEMA_4_RESET 0000000000
VEC_INTERRUPT_STATUS 0x7e806194:RW
EMMC_IRPT_EN_ACMD_ERR_BITS 24:24
CM_TD1CTL_BUSY_LSB 7
DMA9_TI_PERMAP_BITS 20:16
DMA2_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
USB_DSTS_ENUM_SPD_MSB 2
A2W_SMPS_B_STAT_VOLTS_BITS 4:0
CM_DFTCTL_KILL_BITS 5:5
USB_DCFG_NZ_STS_OUT_HSHK_LSB 2
V3D_SRQPC_MASK 0xffffffff
CM_GP2DIV_DIV_CLR 0xff000000
HD_HDM_CTL_CECRXD_LSB 9
MPHI_INTCTRL_IMFOFLW_SET 0x00000100
AVE_IN_STATUS_VFORM_FIELD_BITS 12:12
I2C_SPI_SLV_DEBUG2_WIDTH 24
DMA5_TI_PERMAP_MSB 20
CCP2TX_TTC_ATX_LSB 31
GP_LEN1_LENn32_LSB 0
HDMI_RAM_GCP_5_WIDTH 32
MPHI_C1INDDB_MTERM_CLR 0xefffffff
MPHI_C0INDDA_START_SET 0xffffffff
DMA7_NEXTCONBK_ADDR_BITS 31:5
DMA12_CS_DISDEBUG_CLR 0xdfffffff
EMMC_IRPT_MASK_CEND_ERR_LSB 18
SD_DQRCRC3_MASK 0xffffffff
DMA5_TI_SRC_WIDTH_MSB 9
AUX_SPI_STAT_RXFULL 0x00000100
A2W_PLLB_SP2_DIV_BITS 7:0
CCP2TX_TIC_TEIE_MSB 1
CM_VPUCTL_GATE_SET 0x00000040
DMA5_CS_ERROR_MSB 8
DMA1_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
DMA14_TI_DEST_IGNORE_SET 0x00000080
JP_DCCTRL 0x7e00500c:RW
A2W_PLLH_ANA_VCO_RANGE_LSB 0
DMA5_SOURCE_AD 0x7e00750c:RO
INTERRUPT_I2C_SLV ((64) + 43 )
SH_HCFG_SDIO_IRPT_EN_BITS 5:5
USB_HCSPLT0_XACT_POS_CLR 0xffff3fff
HDMI_RAM_PACKET_12_3_WIDTH 32
EMMC_STATUS_NEW_WRITE_DATA_LSB 10
DMA12_TI_BURST_LENGTH_SET 0x0000f000
USB_DOEPCTL0_SET_ODD_FR_SET 0x20000000
L1_IC1_CONTROL_RAS_DISABLE_CLR 0xffffffef
CAM1_CAMIBEA1_MASK 0xffffffff
DMA6_DEBUG_DMA_STATE_MSB 24
linux 1
USB_HCINTMSK3_WIDTH 32
MPHI_AXIPRIV_HSPECEN_BITS 8:8
DMA7_TI_DEST_WIDTH_LSB 5
USB_DIEPINT5_MASK 0xffffffff
GROPCTR_TU1_SAME_BANK_STALL 0x17
DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
V3D_BXCF 0x7ec00000 +0x0310:RW
I2C_SPI_SLV_TDR 0x7e21402c:RW
HDMI_DETECTED_VERTB0_MANUAL_VBP0_LSB 8
MS_SEMA_13_MASK_BITS 0:0
GRSCFG 0x1A005800 + 0x04:RW
PWM_STA_STA4_BITS 12:12
CM_DSI0PDIV_DIV_MSB 12
AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_BITS 31:31
MPHI_HSINDDB_HANDLE_MSB 27
CM_OTPCTL_BUSY_BITS 7:7
EMMC_FORCE_IRPT_DATA_DONE_SET 0x00000002
USB_DOEPDMA4_MASK 0xffffffff
DMA6_CS_INT_MSB 2
EMMC_IRPT_MASK_CARD_MSB 8
HDMI_FIFO_CTL_RECENTER_BITS 6:6
SMI_DSR1_FSETUP_SET 0x00400000
CM_DSI0PCTL_FRAC_SET 0x00000200
USB_GRSTCTL_C_SFT_RST_CLR 0xfffffffe
SMI_DCS_EANBLE_BITS 0:0
CM_UARTCTL_FRAC_BITS 9:9
SMI_DSW2_WDREQ_MSB 7
APERF0_BW0_CTRL_MASK 0xf0001f1f
SD_CS_STALLING_BITS 24:24
PM_CAM1_LDOLPEN_MSB 1
DMA2_TI_BURST_LENGTH_LSB 12
CM_PLLA_HOLDPER_LSB 7
DMA2_TI_DEST_IGNORE_LSB 7
A2W_PLLB_SP2_BYPEN_MSB 9
A2W_PLLD_FRAC_RESET 0000000000
GP_FSEL2_WIDTH 30
MS_SEMA_17_WIDTH 1
APERF0_BW0_WMAX_MASK 0x00ffffff
CM_HSMCTL_KILL_BITS 5:5
GP_FSEL6_FSEL66_LSB 18
USB_DIEPMSK_MASK 0xffffffff
DMA0_TI_PERMAP_BITS 20:16
A2W_PLLC_DIG3R_RESET 0x00000004
HDMI_RAM_PACKET_10_2_RESET 0000000000
SLIM_DMA_DC1_WIDTH 32
DMA0_TI_NO_WIDE_BURSTS_BITS 26:26
CM_PCMCTL_BUSY_MSB 7
DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
SMI_DSR3_RPACE_CLR 0xffff80ff
EMMC_HWMAXAMP0_AMP_30V_BITS 15:8
I2C_SPI_SLV_RSR_OE_SET 0x00000001
DMA0_NEXTCONBK_ADDR_LSB 5
SMI_DSW1_WDREQ_LSB 7
TXP_CTRL_VSTART_AT_EOF_CLR 0xffff7fff
I2C0_FIFO_RESET 0000000000
CMUSB 0x7C:RW
CCP2TX_TIC_TQIT_CLR 0xffffff0f
HDMI_DETECTED_HORZA_MANUAL_VPOL_MSB 14
DMA14_DEBUG_DMA_STATE_LSB 16
DMA6_TI_DEST_INC_LSB 4
L1_D_PRIORITY_c1_l2_priority_MSB 19
DMA15_CS_ACTIVE_MSB 0
HDMI_READ_POINTERS_DOMAIN_WR_ADDR_BITS 29:27
SYSAC_USB_PRIORITY_PRIORITY_LSB 0
DMA4_TI_WAITS_SET 0x03e00000
MPHI_C0INDS_HANDLE_CLR 0xe01fffff
SDHBLC SDCARD_BASE + 0x50:RW
A2W_PLLB_SP1_BYPEN_LSB 9
SD_WTC 0x7ee00020:RO
PCM_RXC_A_CH1EN_SET 0x40000000
APERF1_BW2_WTWAIT 0x7ee080d4:RO
DMA10_TI_DEST_WIDTH_LSB 5
CM_TDCLKEN_MPHIRDFT_SET 0x00000400
EMMC_CONTROL1_CLK_STABLE_CLR 0xfffffffd
EMMC_CONTROL2_NOTC12_ERR_CLR 0xffffff7f
CM_HSMCTL_KILL_CLR 0xffffffdf
USB_GHWCFG2_WIDTH 31
DMA12_NEXTCONBK_ADDR_LSB 5
DMA1_DEBUG 0x7e007120:RW
SMI_DSR1_MASK 0xffffffff
PCM_MODE_A_FTXP_MSB 24
VEC_INTERRUPT_STATUS_WIDTH 32
DMA11_CS_PAUSED_CLR 0xffffffef
DMA7_CS_ERROR_BITS 8:8
CM_V3DCTL_RESET 0x00000040
EMMC_FORCE_IRPT_CARD_OUT_CLR 0xffffff7f
MS_BASE 0x7e000000
SH_RSP3_RESET 0000000000
DMA10_DEST_AD_D_ADDR_LSB 0
SD_RWC_MAXCNT_LSB 24
USB_GOTGCTL_B_SES_VLD_RESET 0x0
TS_TSENSCTL_THOLD_LSB 8
EMMC_STATUS_CARD_INSERT_LSB 16
AUX_SPI_CNTL0_HOLD4 0x00001000
MS_ICCLR_1_ICCLR_1_BITS 0:0
JMCTRL_AC_TAB(n) MACRO
CM_HSMCTL_SRC_BITS 3:0
EMMC_CONTROL0_WAKE_ONINT_EN_SET 0x01000000
PCM_MODE_A_PDMN_SET 0x08000000
DMA8_SOURCE_AD_S_ADDR_LSB 0
GP_PUDCLK1_PUDCLKn32_CLR 0x00000000
DMA0_TI 0x7e007008:RO
A2W_PLLC_DIG3R_WIDTH 24
DMA14_TI_DEST_DREQ_CLR 0xffffffbf
I2C_SPI_SLV_ICR_MASK 0x0000000f
HDMI_SW_RESET_CNTRL_RESET 0000000000
DMA15_DEBUG_MASK 0x1ffffff7
A2W_PLLB_DIG3_WIDTH 24
I2CS_TXD (1 << 4)
USB_DOEPCTL0_WIDTH 32
CM_TD1CTL_KILL_MSB 5
SMI_DSW2_MASK 0xffffffff
A2W_PLLB_ANA_SSCS_STEP_LSB 0
L1_L1_SANDBOX_START3_START_ADDR_BITS 29:5
CM_PULSECTL_RESET 0x00000011
DMA13_CS_DREQ_CLR 0xfffffff7
I2CS_TXW (1 << 2)
DMA15_NEXTCONBK_WIDTH 32
SD_DQLCRC13_RISE_RESET 0x0
FPGA_STATUS0_HW_ID_MSB 3
A2W_SMPS_LDO0R_MASK 0x00ffffff
DMA11_CS_DREQ_STOPS_DMA_SET 0x00000020
DMA6_STRIDE_D_STRIDE_SET 0xffff0000
CM_LOCK_LOCKC_LSB 2
ARM_2_SEMCLRDBG (0x7E00B000 +0xA00)+0xE0:RW
APERF1_GEN_CTRL_RESET_MSB 1
CMI_CAM1_HSSRC_BITS 1:0
PM_PADS0_RESET 0x0000001b
USB_DTHRCTL_RX_THR_LEN_RESET 0x0
PWM_CTL_MODE1_BITS 1:1
L2_CONT_OFF_l2_flush_SET 0x00000004
A2W_SMPS_L_SPV_VOLTS_BITS 4:0
MPHI_AXIPRIV_RXPROT_RESET 0x2
HD_CSC_12_11 0x7e808044:RW
L1_IC0_PRIORITY_IC0_APRIORITY3_SET 0x0000f000
CCP2TX_TAC_PTATADJ_CLR 0xf0ffffff
GP_HEN2_RESET 0000000000
DMA11_TI 0x7e007b08:RO
EMMC_IRPT_MASK_BLOCK_GAP_LSB 2
DMA15_TI_SRC_WIDTH_MSB 9
MPHI_MOUTFS_WPTR_LSB 10
DMA9_DEBUG_DMA_STATE_CLR 0xfe00ffff
SH_RSP3_CID_CSD_SET 0xffffffff
CM_PLLTCNT0 0x7e101134:RW
CM_PLLTCNT1 0x7e101138:RW
CM_PLLTCNT2 0x7e10113c:RW
CM_PLLTCNT3 0x7e101140:RW
ASB_V3D_S_CTRL_CLR_REQ_CLR 0xfffffffe
USB_GMDIOGEN_WIDTH 32
DMA_INT_STATUS_INT11_CLR 0xfffff7ff
CM_LOCK_LOCKH_MSB 4
DMA6_TI_INTEN_MSB 0
SD_PT1_T_INIT1_MSB 7
APERF0_BW2_RTWAIT_MASK 0xffffffff
SD_VIN_CLEAR_LSB 31
CCP2TX_TS_TFP_MSB 6
DMA14_TI_WIDTH 26
A2W_SMPS_A_VOLTSR_MASK 0x0000001f
USB_DIEPINT2_WIDTH 32
A2W_PLLA_ANA_STAT_DATA_CLR 0xfffff000
USB_GINTMSK_CUR_MOD_RESET 0x0
DMA9_DEBUG_FIFO_ERROR_SET 0x00000002
GP_AFEN1_AFENn32_BITS 31:0
SCALER_DISPCTRL_DSP3_MUX_CLR 0xfff3ffff
DMA15_CS_ABORT_SET 0x40000000
SLIM_DCC4_PA0 0x7e210280:RW
SLIM_DCC4_PA1 0x7e210284:RW
A2W_PLLH_RCAL_DIV_BITS 7:0
HDCP_KEY_CTL_WIDTH 3
SMI_DSW2_WPACEALL_LSB 15
USB_DCTL_CGNP_IN_NAK_SET 0x00000100
DSI0_CMD_DATAF_MASK 0x000000ff
DMA13_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
SCALER_DISPCTRL_DSP3_MUX_SET 0x000c0000
SYSAC_L2_ARBITER_CONTROL_DELAY_MSB 3
L2_CONT_OFF_WIDTH 24
USB_GOTGINT_A_DEV_TOUT_CHG_CLR 0xfffbffff
MPHI_INTCTRL_RX0DISC_RESET 0x0
SMI_DSW2_WSTROBE_SET 0x0000007f
HDMI_PERT_LFSR_PRELOAD_WIDTH 32
A2W_SMPS_L_SIAR 0x7e102ed0:RW
SH_CDIV 0x7e20200c:RW
SLIM_DCC3_STAT_MASK 0xc0ff00c7
DMA11_CS_END_BITS 1:1
MS_SEMA_11_RESET 0000000000
AVE_IN_CURRENT_LINE_NUM_INTERLACED_SET 0x40000000
MS_SEMA_2_WIDTH 1
I2C_SPI_SLV_DR_TXFLEVEL_SET 0x07c00000
MPHI_C0INDDB_HANDLE_RESET 0x0
PCM_CS_A_RXCLR_MSB 4
CM_TDCLKEN_PLLBDIV2_CLR 0xffffffdf
A2W_XOSC_PWR_MASK 0x00000007
L2_FLUSH_STA_WIDTH 28
DMA0_SOURCE_AD_S_ADDR_CLR 0x00000000
DMA1_CS_WIDTH 32
GR_UNIFORM_BASE 0x1a00c000
SD_DQLCRC0_FALL_LSB 0
I2C0_DEL 0x7e205018:RW
SD_SF_PGEHLD_T_RESET 0x100
CM_ISPCTL_KILL_CLR 0xffffffdf
SH_HCFG_REL_CMD_LINE_LSB 0
GROPCTR_NOFEPIXELPRIMS 0x04
USB_DOEPCTL0_MPS_BITS 10:0
UART_MSR_DCTS_CLR 0xfffffffe
DMA1_TI_DEST_INC_MSB 4
USB_HCTSIZ6_MASK 0xffffffff
CM_EVENT_BADPASS_CLR 0xfffbffff
PIXELVALVE1_INTSTAT 0x7e207028:RW
A2W_HDMI_CTL_HFEN_HFEN_BITS 0:0
GP_FSEL1_FSEL18_MSB 26
CM_INTEN_LOSSB_CLR 0xffffffbf
L2_STALLS_MASK 0xffffffff
DMA13_TI_SRC_DREQ_SET 0x00000400
SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_SET 0x00000030
SD_SC_T_RRD_BITS 23:20
USB_HCTSIZ0_PID_CLR 0x9fffffff
DMA3_CS_INT_MSB 2
GP_FSEL3_FSEL39_CLR 0xc7ffffff
DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
A2W_SMPS_A_MULTI_RESET 0000000000
MPHI_C0INDS_HANDLE_BITS 28:21
A2W_PLLA_ANA_SSCL_LIMIT_MSB 21
DMA7_CONBLK_AD_RESET 0000000000
USB_GPVNDCTL_STS_BSY_LSB 26
SCALER_DISPCTRL_DSP2_IRQ_CTRL_SET 0x00001800
USB_DIEPTXF1_FIFO_SIZE_CLR 0x0000ffff
I2C_SPI_SLV_DR_OE_MSB 8
SCALER_DISPCTRL_HVS_EN_SET 0x80000000
DSI0_LP_DLT7_MASK 0x000003fc
USB_DSTS_SUSP_STS_BITS 0:0
CM_ARMCTL_ENAB_SET 0x00000010
A2W_PLLA_ANA_KAIP_KP_LSB 0
CM_PLLC_RESET 0x00000300
AUX_MU_LSR_TEMT 0x40
A2W_PLLA_FRAC_RESET 0000000000
SDDELS0 SD_DELS0
SMICS_PAD 6
USB_DCTL_RMT_WKUP_SIG_MSB 0
PM_CAM1_MASK 0x001fffff
USB_GHWCFG4_EN_A_VALID_FILTER_RESET 0x0
A2W_PLLC_CORE2_CHENB_CLR 0xfffffeff
MPHI_CTRL_INVERT_RESET 0x0
DMA10_CS_PRIORITY_CLR 0xfff0ffff
DMA2_BASE 0x7e007200
PM_GRAFX_CFG_LSB 16
SCALER_OLEDOFFS 0x7e400080:RW
L2_RD_MISSES 0x7ee01104:RO
PM_AVS_RSTDR_V3D_G_CLR 0xfffffff7
SD_DQRCRC15_FALL_MSB 15
USB_DIEPDMAB7_WIDTH 32
CM_TD1CTL_GATE_MSB 6
DMA13_DEBUG_VERSION_SET 0x0e000000
HDMI_KSV_FIFO_0 0x7e902030:RW
HDMI_KSV_FIFO_1 0x7e902034:RW
PRM_CS_MASK 0xffffffff
EMMC_STATUS_DAT_LEVEL0_BITS 23:20
CAM0_CAMDBWP_MASK 0xffffffff
PM_GRAFX_POWOK_BITS 1:1
ARM_1_MAIL1_RD (0x7E00B000 +0x900)+0xA0:RW
SLIM_DMA_DC3_MASK 0xffffffff
SYSAC_V3D_PRIORITY_PRIORITY_SET 0x0000000f
SD_CARCRC_RISE_BITS 31:16
HDMI_VERTB0_MANUAL_VBP0_BITS 8:8
UART_MSR_TERI_CLR 0xfffffffb
USB_DOEPCTL0_TXF_NUM_LSB 22
HDMI_HORZB_MANUAL_HBP_MSB 29
EMMC_IRPT_MASK_ACMD_ERR_BITS 24:24
GP_FSEL2_FSEL28_SET 0x07000000
HDMI_RAM_PACKET_4_7_RESET 0000000000
DMA12_CS_DREQ_SET 0x00000008
PM_PROC_POWOK_MSB 1
SD_DQRCRC2_FALL_LSB 0
HD_MAI_CTL_ERRORE_BITS 2:2
HDMI_DETECTED_HORZB_MANUAL_HBP_SET 0x3ff00000
DSI0_DISP1_CTR_MASK 0xffffffff
MS_SEMA_26_MASK_MSB 0
HDMI_HORZA_MANUAL_HAP_LSB 0
CM_LOCK_LOCKD_LSB 3
CM_OSCFREQI_RESET 0000000000
APERF1_BW0_ATRANS_WIDTH 32
PWM_CTL_SBIT1_BITS 3:3
EMMC_CONTROL2_ACCRC_ERR_SET 0x00000004
HDMI_RAM_PACKET_10_0_WIDTH 32
CM_ARMCTL_BUSY_SET 0x00000080
UART_LCR_OUT2_BITS 3:3
ASB_V3D_M_CTRL_MASK 0x00ffffff
DMA3_DEBUG_FIFO_ERROR_LSB 1
SMI_DSR0_MODE68_BITS 23:23
SYSAC_HOST_PRIORITY_PRIORITY_SET 0x0000000f
HDCP_KEY_CTL_DONE_LSB 1
SLIM_DCC8_CON_RESET 0000000000
USB_DTHRCTL_ARB_PRK_EN_LSB 27
MAX_EXCEPTION_NUM 8
I2C_SPI_SLV_FR_RXFF_CLR 0xfffffff7
CM_CAM1CTL 0x7e101048:RW
FPGA_CTRL0_TERMEN_CLK_MSB 17
A2W_XOSC_CPR_RESET 0000000000
L1_IC0_CONTROL_BP_DISABLE_SET 0x00000008
HDMI_CEC_RX_DATA_1_WIDTH 32
DMA15_CS_PAUSED_BITS 4:4
L1_D1_RD_HITS_MASK 0000000000
DMA6_TI_DEST_WIDTH_MSB 5
HDMI_VERTA0_MANUAL_VSP0_MSB 24
HD_MAI_CTL_PAREN_SET 0x00000100
MPHI_INTCTRL_RX1DISC_CLR 0xffffffef
PM_PADS0_DRIVE_LSB 0
CM_TCNTCTL_KILL_CLR 0xffffffbf
USB_DOEPDMAB12_MASK 0xffffffff
DMA12_DEBUG_MASK 0x1ffffff7
L1_IC0_CONTROL_DISABLE_CLR 0xfffffffe
CAM0_CAMCAP1_MASK 0xffffffff
MS_SEMA_16_MASK_LSB 0
PM_AVS_INTEN_WIDTH 5
A2W_PLLA_FRAC_FRAC_SET 0x000fffff
PM_PADS3_MASK 0x0000003f
SMI_DSW3_WFORMAT_MSB 23
CM_EVENT_GAINA_CLR 0xfffffffe
CM_H264CTL_GATE_MSB 6
A2W_PLLC_PER_DIV_BITS 7:0
CM_SMICTL_SRC_CLR 0xfffffff0
USB_HPRT_RST_CLR 0xfffffeff
SD_DQLCRC10_RISE_RESET 0x0
UNICAM_DBSA1(x) MACRO
CM_VPUCTL_MASK 0x000003cf
DMA1_TI_WAITS_LSB 21
GROPCTR_FBC_EZ_FETCHES 0x3E
HDMI_MAI_FORMAT_RESET 0000000000
SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_MSB 7
PWM_CTL_USEF2_CLR 0xffffdfff
DMA13_CS_DISDEBUG_CLR 0xdfffffff
DSI0_HS_CLT1_WIDTH 10
SH_RSP1_WIDTH 32
HDMI_HBR_AUDIO_PACKET_HEADER_WIDTH 20
DMA12_TI_INTEN_BITS 0:0
A2W_PLLA_ANA_SSCS_MODE_SET 0x00010000
CM_PLLTCTL 0x7e101130:RW
USB_DOEPCTL0_TYPE_CLR 0xfff3ffff
DMA0_DEBUG_WIDTH 29
MS_SEMA_5_MASK_CLR 0xfffffffe
A2W_PLLA_CCP2_BYPEN_LSB 9
DMA15_NEXTCONBK_ADDR_BITS 31:5
PM_IMAGE_CFG_CLR 0xff80ffff
GP_LEV0_LEVn0_MSB 31
TH1T2PC 0x1A008000 + 0x20:RW
DMA0_STRIDE_S_STRIDE_MSB 15
CAM1_CAMDBSA1_RESET 0000000000
DMA11_TI_MASK 0x03fffff9
I2C0_FIFO 0x7e205010:RW
DMA5_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
EMMC_IRPT_MASK_CARD_OUT_LSB 7
GP_FSEL1_FSEL14_LSB 12
L2_WR_MISSES_WIDTH 32
V3D_L2CACTL_MASK 0xffffffff
GRPVORG 0x1A005600 + 0x10:RW
DMA8_CS_DREQ_LSB 3
HDMI_VERTA1_MANUAL_VAL1_CLR 0xffffe000
EMMC_IRPT_MASK_DTO_ERR_CLR 0xffefffff
A2W_PLLA_ANA_SCTL 0x7e102510:RW
EMMC_CONTROL1_SRST_HC_SET 0x01000000
CM_TD0DIV_RESET 0000000000
L1_IC1_FLUSH_S_WIDTH 32
A2W_SMPS_CTLA1R_WIDTH 24
APERF0_BW1_CTRL_EN_MSB 30
MS_SEMA_27_RESET 0000000000
USB_HPRT_RES_RESET 0x0
PM_AVS_STAT_RESET 0000000000
DMA0_CS_DREQ_STOPS_DMA_BITS 5:5
SYSAC_ISP_PRIORITY_MASK 0x0000000f
L1_D0_WR_MISSES_WIDTH 0
CM_VECCTL_BUSY_BITS 7:7
EMMC_CONTROL1_DATA_TOUNIT_SET 0x000f0000
GP_FSEL1_FSEL15_BITS 17:15
CM_VPUDIV_DIV_CLR 0xff00000f
DMA2_TI_WAITS_LSB 21
PM_IMAGE_ISFUNC_MSB 5
A2W_PLLA_ANA_KAIP_KI_CLR 0xffffff8f
DMA_INT_STATUS_INT2_SET 0x00000004
MS_ICSET_0_WIDTH 1
DMA4_TI_SRC_IGNORE_CLR 0xfffff7ff
TXP_CTRL_BUSY_MSB 1
HD_VID_CTL_ENABLE_LSB 31
DMA13_TI_DEST_IGNORE_BITS 7:7
A2W_SMPS_CTLA1R_MASK 0x00ffffff
A2W_XOSC_PWRR_MASK 0x00000007
GP_HEN0_WIDTH 32
HDMI_RAM_PACKET_8_8_WIDTH 32
SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_SET 0x0000ff00
APERF1_BW0_CTRL_RESET_RESET 0x0
MPHI_INTSTAT_RX0TEND_SET 0x00000010
A2W_PLLD_PER_DIV_SET 0x000000ff
SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_CLR 0xffffff3f
DMA3_TI_WAIT_RESP_BITS 3:3
DMA13_CS_PANIC_PRIORITY_MSB 23
SD_RWC_RXVAL_CLR 0xffffffe0
DMA1_DEBUG_DMA_STATE_SET 0x01ff0000
CAM0_CAMIHSTA 0x7e800124:RW
DMA15_CS_DREQ_STOPS_DMA_SET 0x00000020
HD_CSC_CTL_COLORD_SET 0x000000e0
ASB_H264_M_CTRL_CLR_REQ_LSB 0
AVE_IN_STATUS_VFORM_FIELD_LSB 12
HD_VID_CTL_BLANKPIX_LSB 18
SCALER_DISPCTRL_VSCL_DIS_SET 0xc0000000
MS_ICCLR_1 0x7e00009c:RW
CCP2TX_TIC_MASK 0x000000f7
SPI_CS_TXD_LSB 18
FPGA_CTRL0_SW_SPI_CS_LSB 8
SD_RWC_RSTMAX_RESET 0x0
EMMC_FORCE_IRPT_DMA_MSB 3
DMA8_CS_PAUSED_BITS 4:4
HDMI_CEC_CNTRL_1_MASK 0xffffffff
SYSAC_H264_PRIORITY_PRIORITY_LSB 0
USB_GHWCFG3_DFIFO_DEPTH_LSB 16
EMMC_STATUS_NEW_WRITE_DATA_BITS 10:10
JMCTRL_444_MODE (2 << 14)
I2CC_READ (1 << 0)
SH_HCFG_DATA_IRPT_EN_CLR 0xffffffef
USB_DOEPCTL0_USB_ACT_EP_CLR 0xffff7fff
PWM_STA_STA1_MSB 9
SD_DQLCRC10_RISE_LSB 16
ASB_H264_S_CTRL_WCOUNT_BITS 23:14
DMA8_CS_WIDTH 32
DSI0_RX2_PKTH 0x7e209010:RO
SD_DQLCRC7_FALL_LSB 0
A2W_PLLD_CORER_WIDTH 10
CM_CAM0CTL_BUSYD_LSB 8
EMMC_HWCAP0_TCLKUNIT_BITS 7:7
USB_DIEPDMA4_MASK 0xffffffff
USB_HCCHAR0_ODD_FRM_RESET 0x0
MS_MBOX_0 0x7e0000a0:RW
MS_MBOX_1 0x7e0000a4:RW
MS_MBOX_2 0x7e0000a8:RW
MS_MBOX_3 0x7e0000ac:RW
MS_MBOX_4 0x7e0000b0:RW
MS_MBOX_5 0x7e0000b4:RW
MS_MBOX_6 0x7e0000b8:RW
MS_MBOX_7 0x7e0000bc:RW
HDMI_DETECTED_VERTA0_MANUAL_VFP0_CLR 0xfff01fff
CM_EVENT_FGAINA_BITS 10:10
USB_HCSPLT2_MASK 0xffffffff
CM_SMICTL_BUSY_LSB 7
DMA7_TI_DEST_INC_LSB 4
DSI0_PHYC_dsi_esc_lpdt_BITS 17:12
DMA_INT_STATUS_INT15_BITS 15:15
CCP2TX_TS_TFE_CLR 0xffffffef
TS_TSENSSTAT 0x7e212004:RW
GP_PUDCLK0_MASK 0xffffffff
MPHI_TXAXICFG_INTHRESH_LSB 8
DMA0_TI_SRC_INC_SET 0x00000100
HDMI_READ_POINTERS_DRFT_ALMOST_MT_CLR 0xfffbffff
DMA1_TXFR_LEN_YLENGTH_LSB 16
APERF1_BW1_CTRL_RESET 0000000000
SD_CS_CLKOFF_SET 0x00004000
SD_VAD_RESET 0000000000
CM_VECCTL_BUSY_LSB 7
HDMI_RAM_PACKET_6_7_RESET 0000000000
SCALER_OLEDCOEF1_MASK 0xffffffff
APERF1_BW1_ATWAIT 0x7ee08088:RO
EMMC_CMDTM_CMD_CRCCHK_EN_CLR 0xfff7ffff
HDMI_RAM_PACKET_6_2 0x7e9024e0:RW
CM_DSI1ECTL_SRC_MSB 3
EMMC_CONTROL0_READWAIT_EN_LSB 18
CAM0_CAMDAT2_RESET 0x00000002
HD_CSC_CTL_USERGB2YCC_MSB 1
IC0_MASK0_MASK 0x77777777
HDMI_PERT_CONFIG_WIDTH 12
MPHI_HSINDS_MASK 0xdfffffff
HDMI_FIFO_CTL_FIFO_RESET_BITS 5:5
CM_CCP2CTL_BUSYD_LSB 8
SH_TOUT_TIME_OUT_CLR 0x00000000
SMI_FD_FLVL_LSB 8
V3D_DBQGHG_WIDTH 32
USB_DOEPINT0_TX_FIFO_UNDRN_BITS 8:8
SPI_CS_WIDTH 21
A2W_XOSC_CTRL_SMPSOK_MSB 15
SMI_CS_TXW_CLR 0xfbffffff
CM_VECCTL_FRAC_LSB 9
DMA13_CS_ABORT_LSB 30
VEC_CGMSAE_BOT_FORMAT_WIDTH 32
SCALER_DISPECTRL_POSTED_CTRL_MSB 21
CM_PERIACTL_RESET 0x00000040
DMA12_DEBUG_LITE_LSB 28
PM_GRAFX_ISFUNC_LSB 5
SLIM_EA0_WIDTH 32
PM_AVS_RSTDR_PERI_A_SET 0x00000001
HDMI_RAM_PACKET_2_5_MASK 0xffffffff
EMMC_BLKSIZECNT_BLKSIZE_SET 0x00000fff
CM_SDCCTL 0x7e1011a8:RW
CM_ARMDIV_MASK 0x00001000
CM_PLLA_WIDTH 10
DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
L1_L1_SANDBOX_START4_START_ADDR_BITS 29:5
ARM_MS_FULL 0x80000000
CM_DPIDIV_DIV_MSB 15
PIXELVALVE0_VERTB_WIDTH 32
A2W_PLLC_CORE2_BYPEN_BITS 9:9
A2W_PLLD_PER_CHENB_MSB 8
CAM1_CAMDBCTL_RESET 0000000000
CM_INTEN_WRFAIL_MSB 19
DMA7_CS_ACTIVE_CLR 0xfffffffe
SMI_CS_WRITE_RESET 0x0
TXP_CTRL_PILOT_CLR 0x00ffffff
CM_UARTCTL_BUSYD_MSB 8
TH1T2UD 0x1A008000 + 0x24:RW
L2_CONT_OFF_RESET 0000000000
CCP2TX_TS_TQI_BITS 19:19
HDMI_READ_POINTERS_DRFT_UNDERFLOW_MSB 16
DMA10_DEBUG_READ_ERROR_LSB 2
CAM1_CAMCMP1 0x7e801030:RW
EMMC_INTERRUPT_DEND_ERR_BITS 22:22
DMA0_CS_MASK 0xf0ff017f
DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
CAM1_CAMCLK_WIDTH 32
PCM_CS_A_STBY_LSB 25
A2W_PLLC_ANA2_RESET 0000000000
PWM_CTL_PWEN3_BITS 16:16
A2W_SMPS_B_STAT 0x7e1021b0:RW
DSI1_HSTX_TO_CNT 0x7e70003c:RW
V3D_BFC_WIDTH 8
HDMI_DETECTED_HORZB_MANUAL_HFP_CLR 0xfffffdff
USB_HCINTMSK7_WIDTH 32
EMMC_STATUS_NEW_READ_DATA_CLR 0xfffff7ff
PWM_RNG2_MASK 0xffffffff
L2_CONT_OFF_l2_enable_stats_BITS 5:5
DMA6_CS_PRIORITY_CLR 0xfff0ffff
DMA9_CS_ABORT_SET 0x40000000
ASB_CPR_CTRL_CLR_ACK_BITS 1:1
L2_RD_HITS_WIDTH 32
SLIM_DCC8_PA1_RESET 0000000000
SD_PHYC_BIST_MODE_LSB 8
USB_GHWCFG2_NUM_EPS_MSB 10
USB_HCINT0_ACK_BITS 5:5
L1_IC1_PRIORITY_IC1_APRIORITY2_MSB 11
EMMC_HWCAP1_DRV18_TYPEC_LSB 5
SMI_DSW0_WPACE_LSB 8
CM_PLLH_LOADPIX_CLR 0xfffffffe
A2W_SMPS_A_MODER_WIDTH 1
USB_DOEPTSIZ0_XFERSIZE_SET 0x0007ffff
A2W_XOSC_PWRR_WIDTH 3
A2W_PLLB_ARM_BYPEN_SET 0x00000200
PCM_TXC_A_CH2EN_LSB 14
L1_IC1_RAS_POPS_MASK 0000000000
TE_2VSWIDTH_MASK 0xffffffff
EMMC_BUS_CTRL_IRQ_PINS_MSB 5
L1_L1_SANDBOX_START5_WIDTH 30
HDMI_HDCP_KEY_1 0x7e90203c:RW
HDMI_HDCP_KEY_2 0x7e902040:RW
SD_SF_POWSAV_T_CLR 0xfff801ff
USB_GI2CCTL_REG_ADDR_SET 0x0000ff00
DMA4_STRIDE_D_STRIDE_LSB 16
DMA1_CS_ACTIVE_BITS 0:0
PM_DSI1_LDOHPEN_SET 0x00000004
EMMC_INTERRUPT_ADMA_ERR_CLR 0xfdffffff
DMA13_DEBUG_VERSION_LSB 25
USB_GNPTXFSIZ_MASK 0xffffffff
CPG_Param3_WIDTH 32
PM_AVS_INTEN_ALERT_ARM_P_MSB 4
USB_DOEPTSIZ0_RX_DPID_SET 0x60000000
DMA8_DEBUG_MASK 0x1ffffff7
USB_DIEPINT0_OUT_PKT_ERR_SET 0x00000100
CM_EMMCCTL_BUSY_CLR 0xffffff7f
SD_DMRCRC0_HIGH_MSB 31
CM_PLLC_LOADCORE2_MSB 4
A2W_SMPS_A_VOLTS_VOLTS_LSB 0
DMA11_CONBLK_AD_SCB_ADDR_MSB 31
USB_DIEPCTL0_SET_D0_PID_BITS 28:28
GP_FSEL2_FSEL21_LSB 3
SDACC SD_ACC
SMI_DSR0_RPACEALL_SET 0x00008000
PM_DFT_STOPALLCLOCKS_MSB 1
CAM1_CAMDBG2 0x7e8010f8:RW
DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
GP_FSEL5_FSEL53_MSB 11
SH_DATA_DATA_CLR 0x00000000
CAM1_CAMIDC_WIDTH 32
A2W_PLLH_ANA_SCTL 0x7e102570:RW
JP_HWDATA 0x7e00502c:RW
USB_DOEPTSIZ0_MASK 0xffffffff
FPGA_VERSION_MASK 0xffffffff
USB_DIEPTSIZ0_XFERSIZE_RESET 0x0
SD_PT1_T_INIT3_BITS 27:8
SMI_CS_ENABLE_RESET 0x0
DSI0_PHYC_txulpshs_0_sync_BITS 1:1
DMA3_SOURCE_AD_S_ADDR_BITS 31:0
DMA2_CS_PANIC_PRIORITY_SET 0x00f00000
SMI_A_WIDTH 10
SMI_FD_FLVL_MSB 13
A2W_PLLB_ANA_SSCL_RESET 0000000000
APERF0_BW2_CTRL_RESET_CLR 0x7fffffff
USB_DOEPINT13_WIDTH 32
SH_HSTS_CMD_TIME_OUT_MSB 6
CM_CCP2DIV_WIDTH 13
USB_GUSBCFG_ULPI_AUTO_RES_BITS 18:18
DMA3_TXFR_LEN_MASK 0x3fffffff
CM_SMICTL_KILL_MSB 5
USB_DCTL_RMT_WKUP_SIG_BITS 0:0
DMA12_DEBUG_VERSION_CLR 0xf1ffffff
USB_DPTXFSIZ14_WIDTH 32
GRS_DBGE 0x1A005900 + 0x00:RW
CM_PLLD_LOADPER_MSB 6
SCALER_DISPSTAT_DSP0_STATUS_BITS 13:8
A2W_PLLD_PER_BYPEN_CLR 0xfffffdff
USB_GRXFSIZ 0x7e980024:RW
DMA1_DEBUG_VERSION_LSB 25
VCE_PROGRAM_MEM_BASE 0x7f000000 + 0x110000:RW
CM_ARMCTL_AXIHALF_LSB 12
PM_HDMI_WIDTH 20
OTP_ADDR_REG 0x7e20f01c:RW
USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_CLR 0xffffffdf
HDMI_HDMI_HBR_AUDIO_PACKET_HEADER HDMI_BASE_ADDRESS + 344:RW
SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_BITS 5:4
SLIM_CON2 0x7e210004:RW
DMA_DEBUG_ID (1<<8)
SD_SC_T_RFC_CLR 0x80ffffff
A2W_PLLA_CORE_RESET 0x00000100
EMMC_IRPT_EN_RESET 0000000000
DMA9_CS_RESET_BITS 31:31
DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
GRODBGA 0x1A005100 + 0x000:RW
USB_HCCHAR0_EP_TYPE_CLR 0xfff3ffff
CM_PWMDIV_DIV_CLR 0xff000000
GP_FSEL6_FSEL63_SET 0x00000e00
DMA11_DEBUG_DMA_STATE_CLR 0xfe00ffff
SYSAC_H264_PRIORITY_MASK 0x0000000f
PM_CCP2TX_LDOCTRL_BITS 18:2
SYSAC_TRANS_PRIORITY_P_PRIORITY_MSB 7
USB_DOEPDMA9_WIDTH 32
CAM0_CAMCLT_MASK 0xffffffff
SD_SECEND2_MASK 0xffffffff
USB_GINTMSK_CUR_MOD_LSB 0
SMI_CS_TEEN_LSB 8
DMA6_TI_TDMODE_BITS 1:1
ASB_ISP_M_CTRL_CLR_ACK_LSB 1
L1_D_CONTROL_DC1_FLUSH_BITS 2:2
MS_MBOX_7_MBOX_MSB 31
CM_GP0DIV_MASK 0x00ffffff
USB_GINTMSK_ERLY_SUSP_BITS 10:10
PM_AVS_STAT_ALERT_PERI_A_LSB 0
DSI1_TXPKT1_C_RESET 0000000000
PM_RSTC_FRCFG_MSB 17
JP_SBO 0x7e005020:RW
DMA14_DEST_AD_D_ADDR_CLR 0x00000000
SMI_DSR2_RHOLD_MSB 21
SD_DQRCRC0_RISE_SET 0xffff0000
CM_EVENT_LOSSA_MSB 5
PM_PADS5_SLEW_MSB 4
CAM1_CAMPRI 0x7e80100c:RW
MPHI_MOUTFS_WPTR_RESET 0x0
USB_DOEPINT0_XFER_COMPL_MSB 0
SD_VIN_VIO_RESET 0x0
SMI_DSR2_RWIDTH_BITS 31:30
MPHI_HSINDFS_DFIFOLVL_BITS 0:0
DMA5_TI_SRC_WIDTH_CLR 0xfffffdff
SD_CARCRC_RISE_MSB 31
A2W_PLLA_DIG3_MASK 0x00ffffff
A2W_XOSC_CTRL_DDROK_LSB 16
CMI_CAM1_RX0SRC_SET 0x0000000c
ARM_AIS1_HAVEDATA 0x00000080
A2W_PLLC_ANA_STATR 0x7e102c30:RW
USB_GRXSTSP_DEV_EP_NUM_RESET 0x0
DMA10_CS_ERROR_BITS 8:8
DMA12_CS_RESET_MSB 31
A2W_PLLH_ANA_VCO_MASK 0x00000001
EMMC_CONTROL2_TUNED_LSB 23
USB_HCDMA3_WIDTH 32
USB_HCCHAR0_DEV_ADDR_MSB 28
GP_FSEL4_FSEL46_BITS 20:18
SD_SA_MASK 0xffffffff
A2W_PLLH_RCAL_BYPEN_CLR 0xfffffdff
UART_SCR_RESET 0000000000
HDMI_RAM_PACKET_6_5_WIDTH 32
A2W_PLLA_ANA_SSCS_MASK 0x0001ffff
SMI_DSR1_RHOLD_LSB 16
CAM1_CAMCTL_WIDTH 32
DMA13_TI_PERMAP_BITS 20:16
SD_DQLCRC7_FALL_BITS 15:0
EMMC_STATUS_WRT_PROTECT_MSB 19
CM_VPUDIV_RESET 0x00001000
CM_TDCLKEN_PLLABYP_SET 0x00000001
CAM0_CAMDAT0_WIDTH 32
DMA9_DEBUG_LITE_CLR 0xefffffff
AVE_IN_CTRL_HIGH_PRIORITY_BITS 23:20
SCALER_DISPSTAT_1 0x7e400000 + 0x58:RW
MS_SEMA_11_MASK 0x00000001
CCP2TX_TS_TUE_LSB 3
SD_SECSRT0_ADDR_MS_LSB 13
MPHI_INTCTRL_HSDCOFLW_LSB 20
CCP2TX_TTC_RESET 0x00000100
SD_CS_DEL_KEEP_LSB 18
CM_SYSDIV_DIV_BITS 12:12
JP_SDA 0x7e005018:RW
SD_DQLCRC8_RISE_CLR 0x0000ffff
USB_HFNUM_NUM_BITS 15:0
L2_CONT_OFF_l2_flush_core_limit_SET 0x00f00000
HDMI_RAM_PACKET_2_7_WIDTH 32
CM_PLLH_LOADRCAL_SET 0x00000004
JDCCTRL_SETDC(n) MACRO
CM_DPICTL_BUSYD_CLR 0xfffffeff
CM_PLLD_LOADCORE_MSB 4
CAM0_CAMICS 0x7e800134:RW
EMMC_EXRDFIFO_EN_WIDTH 1
PM_CAM0_LDOHPEN_BITS 2:2
CAM1_CAMICS_WIDTH 32
USB_DOEPCTL10 0x7e980c40:RW
USB_DOEPCTL11 0x7e980c60:RW
USB_DOEPCTL12 0x7e980c80:RW
USB_DOEPCTL13 0x7e980ca0:RW
USB_DOEPCTL14 0x7e980cc0:RW
USB_DOEPCTL15 0x7e980ce0:RW
AVE_OUT_CTRL_COEFF_IRQ_EN_SET 0x00000002
HDMI_VERTB1_MANUAL_VBP1_MSB 8
SD_DQRCRC4_RISE_RESET 0x0
USB_GOTGINT_SES_REQ_SUC_STS_CHG_SET 0x00000100
CM_EMMCDIV_RESET 0000000000
SH_HCFG_SDIO_IRPT_EN_SET 0x00000020
SYSAC_V3D_PRIORITY_PRIORITY_RESET 0x0
APERF1_BW1_CTRL_EN_MSB 30
PRMSCC 0x7e20d000 + 0x08:RW
HDMI_RAM_PACKET_8_2_RESET 0000000000
A2W_XOSC0 0x7e102090:RW
A2W_PLLC_DIG1R_MASK 0x00ffffff
USB_HPRT_OVR_CURR_CHNG_LSB 5
HDMI_ENCODER_CTL_WIDTH 1
USB_GRXSTSP_HST_PKT_STS_MSB 20
ARM_T_VALUE 0x7E00B000 +0x404:RW
SD_PT2_T_INIT5_RESET 0xfa0
A2W_PLLB_ANA_VCOR_RESET 0000000000
GP_EDS1_EDSn32_SET 0xffffffff
CAM0_CAMIDC 0x7e800138:RW
CAM1_CAMCMP0_RESET 0000000000
A2W_PLLD_ANA_SSCS_STEP_SET 0x0000ffff
A2W_PLLB_ANA_KAIP_KI_CLR 0xffffff8f
MS_SEMA_20_MASK_CLR 0xfffffffe
SMI_DSW1_WPACE_SET 0x00007f00
A2W_PLLB_FRACR_RESET 0000000000
CAM0_CAMIDS 0x7e800148:RW
GP_FSEL2_FSEL29_LSB 27
SMI_DSW2_WSETUP_MSB 29
USB_DCFG_PER_SCH_INTV_RESET 0x0
FPGA_CTRL0_SPI0_SEL_A_MSB 9
L1_D0_WR_MISSES_MASK 0000000000
A2W_PLLC_ANA0_WIDTH 24
HDMI_RAM_PACKET_4_4_RESET 0000000000
MPHI_OUTDS_HANDLE_RESET 0x0
SD_DQRCRC1_FALL_MSB 15
PCM_GRAY_FLUSHED_SET 0x0000fc00
A2W_PLLB_ANA_SSCL_WIDTH 22
CAM0_CAMIHWIN_WIDTH 32
SCALER_DISPLIST0_MASK 0xffffffff
FPGA_CTRL0_DIS_CTL2_BITS 2:2
DMA5_DEBUG_MASK 0x1ffffff7
USB_DCFG_DEV_SPD_MSB 1
L1_D0_WR_SNOOPS 0x7ee02154:RO
DMA14_DEBUG_LITE_BITS 28:28
MPHI_CTRL_INVERT_CLR 0xfffffeff
USB_HCINTMSK2_MASK 0xffffffff
USB_HFNUM_REM_MSB 31
L1_L1_SANDBOX_END6_WIDTH 30
SD_MRT_T_MRW_RESET 0x4
HDMI_DETECTED_HORZB_RESET 0x03018010
PM_DSI1_LDOCTRL_LSB 3
DMA8_TI_BURST_LENGTH_SET 0x0000f000
CCP2TX_TS_TQL_LSB 8
IC0_FORCE1_RESET 0000000000
A2W_PLLC_MULTI_RESET 0000000000
AVE_IN_STATUS_CSYNC_FIELD_LSB 13
PCM_INTSTC_A_RXR_CLR 0xfffffffd
I2C_SPI_SLV_RSR_TXDMABREQ_SET 0x00000008
PM_AVS_STAT_MASK 0x0000001f
DMA8_NEXTCONBK_ADDR_MSB 31
PWM_STA_RESET 0000000000
SH_EDM_FIFO_COUNT_MSB 8
CM_SDCDIV_WIDTH 18
MPHI_HSINDFS_DFIFOLVL_LSB 0
DMA9_SOURCE_AD 0x7e00790c:RO
DMA10_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
USB_DIEPTXF1 0x7e980104:RW
USB_DIEPTXF2 0x7e980108:RW
USB_DIEPTXF3 0x7e98010c:RW
USB_DIEPTXF4 0x7e980110:RW
USB_DIEPTXF5 0x7e980114:RW
USB_DIEPTXF6 0x7e980118:RW
USB_DIEPTXF7 0x7e98011c:RW
USB_DIEPTXF8 0x7e980120:RW
USB_DIEPTXF9 0x7e980124:RW
SD_SA_RFSH_T_RESET 0x30c
USB_GLPMCFG_WIDTH 32
DMA6_DEST_AD_D_ADDR_MSB 31
DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
USB_DOEPINT0_OUT_TKN_EP_DIS_RESET 0x0
DMA2_CS_DREQ_MSB 3
DMA6_TI_PERMAP_BITS 20:16
APERF0_BW0_CTRL_RESET 0000000000
ARM_C0_DBG0SYNC 0x00010000
DMA3_TI_INTEN_CLR 0xfffffffe
USB_DCFG_PER_SCH_INTV_MSB 25
A2W_PLLB_ANA_STAT_RESET 0000000000
SD_DQLCRC5_RISE_SET 0xffff0000
DMA8_TI_DEST_INC_LSB 4
I2C_SPI_SLV_MIS_OEMIS_CLR 0xfffffff7
HD_BASE 0x7e808000
SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_RESET 0x0
A2W_SMPS_L_SIVR 0x7e102dd0:RW
DMA2_CS_ERROR_SET 0x00000100
I2C_SPI_SLV_CR_CPOL_LSB 4
DMA0_DEST_AD_MASK 0xffffffff
CM_HSMCTL_GATE_CLR 0xffffffbf
PCM_RXC_A_CH1WID_CLR 0xfff0ffff
SCALER_DISPSTAT_RD_IRQ_CLR 0x0000003f
CM_DFTCTL_FRAC_MSB 9
SD_DAT_RESET 0000000000
L1_D0_RD_THRUS_WIDTH 0
CM_CAM0CTL_BUSYD_BITS 8:8
DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
EMMC_FORCE_IRPT_ACMD_ERR_CLR 0xfeffffff
PCM_INTEN_A_RXR_BITS 1:1
CAM0_CAMISTA_RESET 0000000000
CM_GP0DIV_DIV_MSB 23
SCALER_DISPECTRL_CR_BUSY_CLR 0x000007ff
DMA5_DEST_AD_D_ADDR_BITS 31:0
APERF1_BW2_ATRANS 0x7ee080c4:RO
ARM_S_READPEND 0x000003FF
I2C_SPI_SLV_DR_TXDMABREQ_BITS 11:11
DMA7_CS_ABORT_LSB 30
GROPCTR_FBC_EZ_UM_STALLS 0x3D
USB_HCTSIZ0_PKT_CNT_MSB 28
CM_AVEOCTL_BUSYD_BITS 8:8
EMMC_INTERRUPT 0x7e300030:RW
EMMC_CONTROL0_ALT_BOOT_EN_MSB 22
A2W_SMPS_L_SIVR_WIDTH 5
DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
EMMC_INTERRUPT_ENDBOOT_CLR 0xffffbfff
IC_MASK0 0x7e002010:RW
CM_EMMCDIV_DIV_CLR 0xffff000f
USB_DIEPINT0_BNA_MSB 9
TXP_DIM_HEIGHT_MSB 27
DMA0_CS_PAUSED_CLR 0xffffffef
USB_GINTMSK_NP_TXF_EMP_SET 0x00000020
CMGEN 0x7C:RW
DMA10_CONBLK_AD_SCB_ADDR_BITS 31:5
HDMI_RAM_PACKET_11_3_MASK 0xffffffff
V3D_IDENT3_MASK 0xffffffff
USB_GHWCFG3_RM_OPT_FEATURES_LSB 10
DSI0_DISP1_CTR_RESET 0000000000
A2W_PLLB_ANA_SCTL_RESET_SET 0x00000010
SD_VIN_SPLIT_SET 0x00020000
DMA3_DEBUG_READ_ERROR_SET 0x00000004
DMA_INT_STATUS_INT3_LSB 3
TB_JTB_CONFIG_TDO_RISE_BITS 10:10
A2W_PLLA_ANA_SCTL_UPDATE_MSB 3
USB_HCSPLT0_PRT_ADDR_CLR 0xffffff80
TXP_CTRL_VERSION_MSB 23
A2W_PLLB_ANA_VCO_RANGE_CLR 0xfffffffe
L1_IC1_RAS_PUSHES_WIDTH 0
APERF0_BW0_WMAX_RESET 0000000000
L1_L1_SANDBOX_START5_START_ADDR_BITS 29:5
USB_HPRT_SPD_BITS 18:17
CM_PWMCTL_BUSYD_MSB 8
SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_RESET 0x0
A2W_PLLB_ARM_WIDTH 10
DMA7_SOURCE_AD_S_ADDR_BITS 31:0
SLIM_DCC7_PROT 0x7e2102f0:RW
A2W_SMPS_L_SIV_RESET 0000000000
DMA6_CS_PANIC_PRIORITY_SET 0x00f00000
EMMC_STATUS_READ_TRANSFER_MSB 9
SD_VIN_WIDTH 32
CM_DSI0HSCK_SELPLLD_SET 0x00000001
HDMI_POSTING_MASTER 0x7e90215c:RW
SMI_DCS_START_BITS 1:1
EMMC_CONTROL2_EN_PSV_CLR 0x7fffffff
SMI_A_ADDR_MSB 5
HD_MAI_CTL_WHOLSMP_SET 0x00001000
A2W_PLLB_FRACR 0x7e102ae0:RW
DMA1_TI_DEST_WIDTH_CLR 0xffffffdf
DMA2_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
CM_TECDIV_DIV_BITS 17:12
USB_DTXFSTS12_MASK 0xffffffff
L1_IC1_CONTROL_DISABLE_VLINE_LSB 5
AVE_IN_LINE_NUM_INT 0x7e91002c:RW
HDMI_MAI_CONFIG_MASK 0x0fffffff
DMA5_CS_DREQ_STOPS_DMA_MSB 5
CM_LOCK_LOCKA_SET 0x00000001
PCM_GRAY_RXFIFOLEVEL_LSB 16
GP_FSEL0_FSEL01_MSB 5
EMMC_ARG1_RESET 0000000000
DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
HDMI_RAM_PACKET_6_0_MASK 0xffffffff
GP_FSEL2_FSEL22_CLR 0xfffffe3f
USB_HCCHAR0_EP_NUM_RESET 0x0
CAM0_CAMIBSA0_MASK 0xffffffff
PWM_STA_EMPT1_MSB 1
A2W_SMPS_C_CLK_OSCDIV_MSB 1
USB_GI2CCTL_MASK 0xdfffffff
APERF0_BW0_CTRL_EN_CLR 0xbfffffff
CAM1_CAMIBSA0_MASK 0xffffffff
GROPCTR_TU0_CACHE_STALLS 0x12
PCM_RXC_A_CH1EN_BITS 30:30
HDMI_FIFO_CTL_USE_EMPTY_SET 0x00002000
PM_PADS0_POWOK_SET 0x00000020
SLIM_DTX_DMA ( 8*(1<<16))
DMA9_TI_MASK 0x03fffff9
SPI_DLEN_LEN_SET 0x0000ffff
FPGA_DCM_CTRL_REMOTE_EN_LSB 8
A2W_PLLB_SP0_DIV_LSB 0
MPHI_INTSTAT_IMFOFLW_BITS 29:29
CM_TDCLKEN_PLLCDIV2_SET 0x00000040
SD_SECEND2_WIDTH 32
CM_V3DCTL_FRAC_CLR 0xfffffdff
SD_CS_SDTST_LSB 5
USB_HCTSIZ0_PID_RESET 0x0
DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
PCM_INTEN_A 0x7e203018:RW
USB_DOEPTSIZ4_WIDTH 32
SMI_DSR3_RPACE_LSB 8
CM_TDCLKEN_HDMIBYP_MSB 8
DMA0_DEBUG_VERSION_MSB 27
UNICAM_STA(x) MACRO
ASB_ISP_M_CTRL_RCOUNT_BITS 13:4
SCALER_DISPID_RESET 0x64647276
A2W_PLLA_FRAC_FRAC_BITS 19:0
AVE_IN_CTRL_LENGTH_IN_PXLS_BITS 8:8
USB_HPRT_CONN_DET_MSB 1
SH_EDM_STATE_MACHINE_SET 0x0000000f
CM_TECDIV_MASK 0x0003f000
DSI1_CTRL_RESET 0000000000
I2C_SPI_SLV_SLV_ADDR_BITS 6:0
HD_VID_CTL_RST_FRAMEC_CLR 0xdfffffff
A2W_PLLA_PER_DIV_SET 0x000000ff
CM_PWMCTL_MASH_LSB 9
APERF1_BW1_AMAX_WIDTH 24
USB_GNPTXFSIZ_NP_TXF_ST_ADDR_CLR 0xffff0000
USB_GHWCFG2_MODE_MSB 2
GP_FSEL1_FSEL11_SET 0x00000038
MPHI_C0INDS 0x7e006010:RW
DMA0_CS_DISDEBUG_BITS 29:29
DMA3_TI_DEST_INC_MSB 4
A2W_XOSC_CTRL_PLLCOK_BITS 12:12
HDMI_BKSV1_RESET 0000000000
EMMC_IRPT_EN_CARD_IN_LSB 6
CM_SDCCTL_UPDATE_BITS 17:17
EMMC_BOOT_TIMEOUT_TIMEOUT_BITS 31:0
USB_DIEPCTL1_MASK 0xffffffff
USB_DIEPINT0_STS_PHSE_RCVD_MSB 5
L2_L2_ALIAS_EXCEPTION_ID 0x7ee01084:RO
MPHI_INTSTAT_RX0MEND_RESET 0x0
A2W_PLLC_CORE0_DIV_CLR 0xffffff00
DMA9_DEST_AD_D_ADDR_SET 0xffffffff
DMA15_TI_SRC_DREQ_SET 0x00000400
SLIM_DCC_PA0(n) MACRO
SLIM_DCC_PA1(n) MACRO
SD_RWC_LASTCNT_BITS 20:16
A2W_PLLD_CORE_CHENB_BITS 8:8
MPHI_TXAXICFG_TXPPRIO_MSB 7
CM_DPICTL_MASK 0x000003bf
I2C0_DIV 0x7e205014:RW
CM_VECCTL_RESET 0000000000
USB_GINTMSK_RXF_LVL_MSB 4
A2W_PLLH_ANA_STAT_DATA_LSB 0
DMA2_DEBUG_MASK 0x1ffffff7
DMA6_STRIDE_MASK 0xffffffff
I2C_SPI_SLV_IMSC_RESET 0000000000
GP_FSEL6_FSEL68_MSB 26
DMA11_CS_ACTIVE_BITS 0:0
SD_STALL_CYCLES_BITS 9:0
PCM_TXC_A_CH1WID_MSB 19
A2W_PLLC_ANA_KAIP_KP_LSB 0
AVE_IN_STATUS_AXI_STATE_CLR 0xff8fffff
HDMI_RAM_PACKET_8_0_WIDTH 32
MPHI_C0INDDB_MTERM_MSB 28
USB_GRSTCTL_WIDTH 32
DMA0_TI_PERMAP_CLR 0xffe0ffff
MS_SEMA_0_MASK_LSB 0
SD_SECEND0_ADDR_LS_LSB 0
A2W_PLLH_AUX_DIV_BITS 7:0
A2W_PLLD_CORE_CHENB_SET 0x00000100
CCP2TX_TC_CLKM_CLR 0xfffffffb
V3D_PCTRS3_MASK 0x0000001f
SD_VER 0x7ee0009c:RO
USB_PCGCR_RST_PDWN_MODULE_RESET 0x0
EMMC_CONTROL0_HCTL_DMA_CLR 0xffffffe7
EMMC_STATUS_CARD_DETECT_LSB 18
IFORCE0_1 0xffffffff:RW
CCP2TX_TAC_MASK 0xffffff0f
MPHI_HSINDCF_LENERR_MSB 30
DMA7_CS_PAUSED_LSB 4
SMI_DSW3_WPACE_CLR 0xffff80ff
HDMI_RAM_PACKET_13_7_MASK 0xffffffff
HDMI_RAM_PACKET_4_2_WIDTH 32
HD_HDM_CTL_ENDIAN_MSB 1
MPHI_INTSTAT_TXEND_CLR 0xfffeffff
MS_MBOX_4_MBOX_LSB 0
GRFCSTAT 0x1A005500 + 0x00:RW
MS_SEMA_31_MASK_MSB 0
GP_EDS1 0x7e200044:RW
AUX_MU_CNTL_FLOW4 0x30
CAM1_CAMDBG2_MASK 0xffffffff
PM_RSTS_HADDRQ_SET 0x00000001
GP_EDS2 0x7e200048:RW
SDARG SDCARD_BASE + 0x04:RW
MPHI_INTSTAT_HSDISC_MSB 30
DMA9_CONBLK_AD_SCB_ADDR_MSB 31
EMMC_STATUS_CARD_STABLE_MSB 17
CM_VECCTL_KILL_MSB 5
L1_L1_SANDBOX_START3_CTRL_BITS 0:0
DMA14_SOURCE_AD_S_ADDR_LSB 0
SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_SET 0x000000c0
USB_HCINT0_NYET_MSB 6
SH_RSP0_CARD_STATUS_CLR 0x00000000
I2C_SPI_SLV_RSR_RXDMAPREQ_SET 0x00000010
MPHI_INTSTAT_RX0DISC_CLR 0xffefffff
PCM_MODE_A_FSLEN_CLR 0xfffffc00
USB_GUSBCFG_ULPI_UTMI_SEL_LSB 4
SCALER_DISPSTAT_DSP1_STATUS_CLR 0xffc0ffff
CAM0_CAMIDCA_MASK 0xffffffff
DMA6_CS_RESET_MSB 31
VEC_SOFT_RESET 0x7e80610c:RW
DMA15_DEBUG_VERSION_CLR 0xf1ffffff
SD_SECEND2_ADDR_MS_CLR 0x00001fff
USB_HCTSIZ0_DO_PNG_RESET 0x0
HDMI_RAM_PACKET_8_4_MASK 0xffffffff
A2W_PLLB_SP1_DIV_MSB 7
USB_DVBUSDIS_MASK 0x0000ffff
GP_HEN2_HENn64_LSB 0
SD_DQLCRC10_FALL_LSB 0
SD_DQLCRC3_WIDTH 32
PM_USB_MASK 0x00000001
HDMI_RAM_PACKET_2_3_MASK 0xffffffff
TXP_CTRL_TRANSPOSE_BITS 6:6
CM_H264DIV_MASK 0x0000fff0
PCM_MODE_A_FSM_LSB 21
CM_PLLA_ANARST_BITS 8:8
A2W_PLLA_PERR_MASK 0x000003ff
A2W_PLLA_DIG0R_RESET 0000000000
V3D_PCTRS2_WIDTH 5
CM_PLLTCTL_BUSY_LSB 7
HDMI_RAM_PACKET_2_1_RESET 0000000000
CM_SLIMCTL_BUSY_BITS 7:7
USB_DOEPINT0_BACK2BACK_SETUP_CLR 0xffffffbf
DMA0_SOURCE_AD_WIDTH 32
DMA8_TXFR_LEN_XLENGTH_LSB 0
CM_INTEN_A2WDONE_SET 0x00100000
CM_VPUCTL_BUSY_SET 0x00000080
PCM_INTSTC_A_RXERR_CLR 0xfffffff7
HDMI_DETECTED_VERTB0_MANUAL_VBP0_BITS 8:8
V3D_CT0PC_MASK 0xffffffff
A2W_PLLB_SP1R_RESET 0x00000100
HDMI_DETECTED_HORZB_MANUAL_HFP_LSB 9
USB_GPVNDCTL_CTRL_UTMI_CLR 0xfffff0ff
DMA13_DEBUG_DMA_ID_MSB 15
DMA4_CS_PANIC_PRIORITY_BITS 23:20
CAM1_CAMDBG0_MASK 0xffffffff
GR_PPL_ADDR_MASK 0x0000007F
L1_IC1_BP_MISSES 0x7ee020cc:RO
SD_SC_T_WTR_SET 0x00000070
CM_OSCCOUNT_WIDTH 24
CM_H264DIV_DIV_MSB 15
GP_LEV1_LEVn32_LSB 0
DMA14_TI_DEST_DREQ_LSB 6
AVE_OUT_CTRL_REFRESH_RATE_SET 0x0000000c
SCALER_DISPSTAT_WIDTH 32
I2C2_DEL_WIDTH 32
CAM1_CAMDBCTL 0x7e801300:RW
SLIM_FS_MASK 0x00003fff
DMA15_DEBUG_FIFO_ERROR_SET 0x00000002
USB_GOTGCTL_SES_REQ_SCS_RESET 0x0
IC1_MASK1_WIDTH 31
CCP2TX_TS_TII_BITS 17:17
USB_GRSTCTL_DMA_REQ_BITS 30:30
DMA11_TI_SRC_WIDTH_LSB 9
DMA6_CS_DREQ_CLR 0xfffffff7
SMI_DC_PANICR_MSB 23
PCM_CS_A_SYNC_MSB 24
A2W_PLLC_ANA_SSCS_WIDTH 17
HDMI_HORZB_MANUAL_HFP_LSB 9
DMA1_CS_DREQ_STOPS_DMA_BITS 5:5
EMMC_HWCAP1_RETUNE_TMR_BITS 11:8
I2C0_DLEN 0x7e205008:RW
APERF0_BW1_RPEND_MASK 0x000000ff
GP_FSEL6_FSEL64_LSB 12
PCM_CS_A_SYNC_SET 0x01000000
MS_MBOX_1_MBOX_CLR 0x00000000
DMA14_TI_WAITS_SET 0x03e00000
L1_D1_RD_THRUS_MASK 0000000000
MPHI_C1INDCF_MTERM_RESET 0x0
CM_AVEOCTL_BUSYD_MSB 8
USB_GOTGCTL_B_SES_VLD_LSB 19
A2W_PLLC_ANA_KAIP_KI_CLR 0xffffff8f
AVE_IN_CTRL_FRAME_RATE_IRQ_EN_LSB 6
HDMI_CEC_RX_DATA_1_MASK 0xffffffff
USB_DIEPCTL0_SET_EVEN_FR_CLR 0xefffffff
L1_L1_SANDBOX_END0_RESET 0x3fffffe0
USB_DOEPCTL0_SET_D0_PID_LSB 28
A2W_HDMI_CTL2R_RESET 0x0018048e
DMA13_TI_DEST_WIDTH_SET 0x00000020
DMA10_CS_DISDEBUG_BITS 29:29
A2W_HDMI_CTL_HFENR_RESET 0000000000
ASB_V3D_M_CTRL_EMPTY_SET 0x00000004
UIER 0x7e201000 + 0x04:RW
HDMI_FIFO_CTL_USE_FULL_MSB 1
CCP2TX_TD_IES_MSB 6
EMMC_CONTROL0_GAP_IEN_MSB 19
DMA13_CS_PAUSED_BITS 4:4
A2W_SMPS_A_GAIN_DIGGAIN_MSB 2
SMI_CS_PVMODE_LSB 12
PM_PADS5_DRIVE_CLR 0xfffffff8
V3D_PCTR8_WIDTH 32
CM_GNRICDIV_DIV_SET 0x00ffffff
USB_GRSTCTL_AHB_IDLE_RESET 0x0
ASB_V3D_S_CTRL_RCOUNT_MSB 13
DMA7_TI_PERMAP_LSB 16
SYSAC_HVSM_PRIORITY_WIDTH 8
HDMI_DETECTED_HORZA_MANUAL_HPOL_SET 0x00002000
I2C_SPI_SLV_FR_TXFF_CLR 0xfffffffb
TXP_XTRA_NOSTBY_CLR 0xfffffffe
DMA6_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
ARM_EH_VPU1HALT 0x00000010
DMA8_TI_DEST_DREQ_BITS 6:6
UART_LCR_WLS_CLR 0xfffffffc
USB_GUSBCFG_ULPI_CLK_SUS_M_BITS 19:19
ASB_V3D_S_CTRL_RESET 0x00000007
USB_GUSBCFG_OTG_I2C_SEL_LSB 16
UART_LCR_DTR_BITS 0:0
EMMC_CONTROL2_ACBAD_ERR_SET 0x00000010
USB_DIEPCTL0_TXF_NUM_CLR 0xfc3fffff
USB_GUSBCFG_TERM_SEL_DL_PULSE_SET 0x00400000
A2W_PLLC_MULTI_MASK 0000000000
SYSAC_PERI_ARBITER_CONTROL_RESET 0000000000
SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_RESET 0x0
A2W_SMPS_CTLC3R_RESET 0000000000
SMI_DSW1_WSETUP_SET 0x3f000000
DMA0_TXFR_LEN_XLENGTH_CLR 0xffff0000
A2W_PLLB_SP2R_RESET 0x00000100
AVE_OUT_STATUS_COEFF_ERROR_BITS 2:2
DMA14_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
DMA12_CS_PAUSED_BITS 4:4
MS_MBOX_6_MBOX_BITS 31:0
DMA2_TXFR_LEN 0x7e007214:RO
FPGA_CTRL0_SPI1_SEL_SET 0x00000400
USB_HCINT4_WIDTH 32
H264_RC_WIDTH 32
ARM_2_MAIL0_WRT (0x7E00B000 +0xA00)+0x80:RW
DMA3_DEBUG_OUTSTANDING_WRITES_LSB 4
CM_TDCLKEN_MPHIRDFT_BITS 10:10
A2W_XOSC_PWR_PWRDN_CLR 0xfffffffd
TXP_DIM 0x7e004008:RW
DMA9_TI_DEST_INC_LSB 4
SD_CS_IDLE_RESET 0x0
SD_DQRCRC9_FALL_MSB 15
USB_GOTGCTL_HST_SET_HNP_EN_BITS 10:10
DC0CS 0x7ee02100:RW
DMA_ENABLE_EN8_BITS 8:8
SD_MR_WDATA_RESET 0x0
DMA0_CS_PANIC_PRIORITY_SET 0x00f00000
DMA5_TI_SRC_DREQ_MSB 10
CM_EMMCCTL_SRC_MSB 3
HD_CSC_34_33_WIDTH 32
CM_SDCCTL_KILL_LSB 5
A2W_PLLH_RCAL_DIV_MSB 7
PM_SMPS_UPEN_CLR 0xfffffffb
TS_TSENSCTL_RSTDELAY_CLR 0xfc03ffff
USB_DOEPCTL12_MASK 0xffffffff
DMA7_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
USB_HCINT0_CH_HLTD_MSB 1
HDMI_DETECTED_VERTB0_MASK 0x003fff00
MPHI_RXAXICFG_INTHRESH_RESET 0x0
PCMCS_RXR (1 << 18)
CMI_CAM1_RESET 0000000000
DMA_INT_STATUS_INT14_LSB 14
EMMC_BLKSIZECNT_BLKSIZE_BITS 11:0
USB_GHWCFG3_PACKET_COUNT_WIDTH_BITS 6:4
SCALER_DISPCTRL_TILE_WID_CLR 0xfffcffff
CM_TCNTCTL_SRC0_CLR 0xfffffff0
USB_DOEPTSIZ0_MC_CLR 0x9fffffff
L1_IC0_PRIORITY_IC0_APRIORITY1_SET 0x000000f0
CAM0_CAMIVWIN_WIDTH 32
MPHI_C1INDS_MASK 0xdfffffff
USB_GHWCFG3_I2C_INTERFACE_LSB 8
DMA13_DEST_AD_D_ADDR_BITS 31:0
EMMC_CONTROL2_ACEND_ERR_CLR 0xfffffff7
CM_OSCFREQF_FRAC_LSB 0
VEC_CONFIG1_WIDTH 32
APERF1_BASE 0x7ee08000
A2W_PLLC_ANA_SCTL_SEL_LSB 0
CM_TD0CTL_BUSYD_CLR 0xfffffeff
USB_HPTXSTS_MASK 0xffffffff
CM_TSENSDIV_DIV_CLR 0xfffe0fff
A2W_PLLH_ANA_MULTI_WIDTH 0
USB_GHWCFG3_MODE_LSB 7
A2W_PLLC_ANA_KAIP_KA_LSB 8
VIDEO_ENC_RevID 0x7e806060:RW
DMA12_CS_RESET_BITS 31:31
DMA10_DEST_AD_WIDTH 32
DMA10_TXFR_LEN 0x7e007a14:RO
CM_PLLB_DIGRST_BITS 9:9
USB_HCCHAR0_DEV_ADDR_BITS 28:22
USB_DOEPCTL0_NEXT_EP_SET 0x00007800
L1_L1_SANDBOX_START6_START_ADDR_BITS 29:5
SMI_CS_AFERR_LSB 25
PM_AVS_INTEN_MASK 0x0000001f
CM_PLLTCTL_KILL_MSB 5
SLIM_DCC4_CON_WIDTH 32
USB_DOEPDMA1_WIDTH 32
SLIM_DCC2_PA0 0x7e210240:RW
SLIM_DCC2_PA1 0x7e210244:RW
A2W_PLLD_ANA_KAIP_KA_BITS 10:8
CM_TSENSDIV_DIV_MSB 16
L1_D_CONTROL_DC_EN_STATS_CLR 0xfffffff7
SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_BITS 1:0
HDMI_SCHEDULER_CONTROL_ALWS_REKEY_KEEPOUT_CLR 0xffffffef
MPHI_OUTDDB_CHANNEL_MSB 28
DMA11_CS_ABORT_BITS 30:30
CAM1_CAMDBWP_RESET 0000000000
EMMC_IRPT_EN_CARD_IN_MSB 6
UIIR 0x7e201000 + 0x08:RO
EMMC_CONTROL0_PWCTL_ON_MSB 8
SD_DMRCRC1_HIGH_CLR 0x0000ffff
EMMC_CONTROL2_TUNEON_CLR 0xffbfffff
USB_DIEPCTL14_WIDTH 32
I2C_SPI_SLV_IFLS_TXIFLSEL_MSB 2
TS_TSENSCTL_EN_INT_LSB 5
EMMC_INTERRUPT_INT_B_BITS 10:10
SD_VIN_INT_EN_SET 0x10000000
EMMC_CMDTM_CMD_CRCCHK_EN_LSB 19
TRANSPOSER_DST_PITCH 0x7e004004:RW
PM_PADS2_SLEW_LSB 4
SMI_DSR1 0x7e600018:RW
SMI_DSR2 0x7e600020:RW
SMI_DSR3 0x7e600028:RW
SMI_DSW3_WWIDTH_CLR 0x3fffffff
CM_PCMDIV_DIV_BITS 23:0
DSI0_PHYC_dlane_hsen_1_sync_LSB 5
DMA14_TI_SRC_IGNORE_LSB 11
DMA5_CS_PAUSED_BITS 4:4
GP_FSEL0_FSEL03_BITS 11:9
DMA3_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
HDMI_FIFO_CTL_VB_CNT_CLR 0xfffff0ff
PM_AUDIO_APSM_CLR 0xfff00000
A2W_PLLB_ANA2R_WIDTH 24
HD_CSC_34_33_MASK 0xffffffff
ASB_V3D_S_CTRL_CLR_REQ_MSB 0
SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_BITS 3:2
DMA13_CS_DREQ_STOPS_DMA_LSB 5
ASB_CPR_CTRL_RESET 0x00000007
APERF1_BW0_CTRL_BUS_BITS 4:0
HDMI_PERT_LFSR_PRELOAD 0x7e902078:RW
GP_FSEL1_FSEL13_LSB 9
A2W_PLLD_FRAC_FRAC_CLR 0xfff00000
EMMC_CONTROL2_NOTC12_ERR_LSB 7
USB_GINTMSK_OTG_INT_BITS 2:2
CAM0_CAMDAT3_WIDTH 32
PM_IMAGE_ENAB_BITS 12:12
VEC_INTERRUPT_CONTROL 0x7e806190:RW
SD_TMC_IPRD_SET 0x0000ff00
EMMC_CONTROL2_EN_AINT_SET 0x40000000
PWM_STA_GAPO3_MSB 6
MPHI_OUTDDA_START_LSB 0
A2W_PLLA_CTRL 0x7e102100:RW
GP_FSEL1_FSEL16_MSB 20
DMA15_CS_INT_SET 0x00000004
DMA3_TI_SRC_IGNORE_SET 0x00000800
DMA3_TI_WAIT_RESP_LSB 3
GP_FSEL3_FSEL37_CLR 0xff1fffff
USB_GUSBCFG_PHY_LPWR_CLK_SEL_MSB 15
SD_DQRCRC0_FALL_SET 0x0000ffff
PM_AVS_EVENT_ALERT_V3D_G_MSB 3
CM_CAM0CTL_ENAB_SET 0x00000010
A2W_SMPS_L_SCA 0x7e1024d0:RW
APERF0_BW1_CTRL_ID_BITS 12:8
APERF0_BW0_AMAX_WIDTH 24
HDMI_RAM_PACKET_13_8_RESET 0000000000
PCMCS_TXTHR_3_QUARTER (2 << 5)
CSI2LPRX0 CSI2_BASE_ADDRESS + 0x20:RW
CSI2LPRX1 CSI2_BASE_ADDRESS + 0x24:RW
SD_CARCRC_FALL_MSB 15
CSI2LPRX3 CSI2_BASE_ADDRESS + 0x2C:RW
L1_L1_SANDBOX_START3_CTRL_LSB 0
GP_AREN0_RESET 0000000000
DMA7_TI_DEST_WIDTH_BITS 5:5
CMI_USBCTL_WIDTH 7
SCALER_DISPSTAT_DMA_ERR_BIT0_BITS 31:14
PM_AVS_STAT_ALERT_SYSTEM_A_CLR 0xfffffffd
MS_SEMA_30_MASK_SET 0x00000001
CAM0_CAMDBEA1_RESET 0000000000
DMA9_TI_WAIT_RESP_CLR 0xfffffff7
A2W_PLLH_ANA3_RESET 0000000000
CSI2LPRXC CSI2_BASE_ADDRESS + 0x30:RW
FPGA_CTRL0_SW_SPI_SCL_MSB 6
MPHI_HSINDCF_EMPTY_CLR 0x7fffffff
PCM_CS_A_TXTHR_LSB 5
AVE_IN_STATUS_BUF1_COMPL_CLR 0xfffffffb
USB_DOEPTSIZ7_MASK 0xffffffff
USB_HCINT0_XFER_COMPL_SET 0x00000001
EMMC_HWCAP0_V3_0_SET 0x02000000
CM_PLLA_HOLDCCP2_LSB 3
CM_TD1CTL_ENAB_BITS 4:4
SPI_CS_CPHA_BITS 2:2
SD_DQRCRC5_RISE_BITS 31:16
PIXELVALVE1_VC 0x7e207004:RW
CM_EMMCCTL_KILL_SET 0x00000020
PIXELVALVE_INTSTAT_1 0x7e207028:RW
AVE_IN_CURRENT_LINE_NUM_WIDTH 32
SYSAC_APB_ID 0x4152424d
EMMC_FORCE_IRPT_WIDTH 32
L1_IC0_RAS_PUSHES_MASK 0000000000
MS_SEMA_14_MASK_SET 0x00000001
UART_LSR_THRE_BITS 5:5
DSI0_HS_CLT0 0x7e209044:RW
SD_CS_SREF2RUN_MSB 8
DSI0_HS_CLT2 0x7e20904c:RW
SMI_DCS_EANBLE_SET 0x00000001
SMI_DSW0_WSWAP_CLR 0xffbfffff
I2C_SPI_SLV_DEBUG1_WIDTH 26
GP_FSEL2_FSEL26_SET 0x001c0000
CM_PWMCTL_KILL_BITS 5:5
SD_CS_SREF2RUN_BITS 8:8
PM_PADS4_HYST_MSB 3
CCP2TX_TAC_DLAC_CLR 0xffff00ff
EMMC_CMDTM_TM_BLKCNT_EN_LSB 1
A2W_PLLD_ANA_KAIP_KP_LSB 0
DMA3_DEST_AD_MASK 0xffffffff
FPGA_CTRL0_CAM_CTL2_CLR 0xfffffffb
CM_LOCK_LOCKB_LSB 1
SD_DQLCRC14_RISE_MSB 31
DPHY_CSR_GLBL_MSTR_DLL_LOCK_STAT 0x7ee07018:RW
PM_RSTS_HADWRH_CLR 0xffffffbf
HDMI_RAM_PACKET_10_7_RESET 0000000000
MS_SEMA_0_MASK 0x00000001
SD_SE_T_XSR_LSB 0
SMI_CS_CLEAR_MSB 4
USB_DIEPCTL0_USB_ACT_EP_RESET 0x0
CPG_Debug0 0x7e211040:RW
CPG_Debug1 0x7e211044:RW
CPG_Debug2 0x7e211048:RW
CPG_Debug3 0x7e21104c:RW
SMI_CS_TXD_CLR 0xefffffff
FPGA_MB_XV3D_BUILD_NUM_WIDTH 32
CCP2TX_TS_TQI_SET 0x00080000
PIARBCTL_CAM_THRESHOLD_CLR 0xffffffcf
INTERRUPT_CCP2 ((64) + 38 )
DMA15_CS_DREQ_MSB 3
IC0_MASK7_RESET 0000000000
CM_PULSECTL_ENAB_MSB 4
DMA7_SOURCE_AD_S_ADDR_SET 0xffffffff
DMA0_STRIDE_D_STRIDE_MSB 31
A2W_XOSC_CTRL_PLLAEN_LSB 6
PIXELVALVE1_HORZB_WIDTH 32
SMI_CS_ENABLE_SET 0x00000001
CAM0_CAMDBG1 0x7e8000f4:RW
SMI_SCALER_0_DMA (24*(1<<16))
L1_L1_SANDBOX_START0_CTRL_SET 0x00000001
TS_TSENSCTL_EN_INT_CLR 0xffffffdf
DMA9_TXFR_LEN 0x7e007914:RO
USB_DIEPCTL0_SET_D0_PID_CLR 0xefffffff
DMA3_TI_DEST_IGNORE_CLR 0xffffff7f
DSI0_DISP1_CTR 0x7e20901c:RW
PM_PROC_CFG_CLR 0xff80ffff
CCP2TX_TAC_BPD_LSB 2
EMMC_CONTROL0_GAP_STOP_CLR 0xfffeffff
DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
I2C_SPI_SLV_CR_SPI_SET 0x00000002
PM_DSI0_LDOCTRL_MSB 20
CM_CKSM_CFG_MSB 17
SMI_DSW0 0x7e600014:RW
SMI_DSW1 0x7e60001c:RW
SMI_DSW2 0x7e600024:RW
SMI_DSW3 0x7e60002c:RW
APERF0_BW0_CTRL_ID_LSB 8
APERF1_BW1_WTWAIT 0x7ee08094:RO
AVE_OUT_CR_COEFF_RED_COEFF_SET 0x3ff00000
DMA6_CS_PAUSED_MSB 4
DMA15_DEBUG_DMA_ID_CLR 0xffff00ff
CAM0_CAMMISC 0x7e800400:RW
VPU_ARB_CTRL_L2_THRESHOLD_RESET 0x0
A2W_XOSC_BIAS_WIDTH 5
EMMC_IRPT_EN_ACMD_ERR_SET 0x01000000
A2W_PLLH_CTRL_MASK 0x000370ff
SMI_DSW1_WWIDTH_LSB 30
GP_FSEL1_FSEL12_LSB 6
DMA12_TI_WAITS_LSB 21
CM_H264CTL_BUSY_MSB 7
DMA8_DEBUG_READ_ERROR_CLR 0xfffffffb
CM_DSI1EDIV_RESET 0000000000
VEC_ENC_PrimaryControl_MASK 0xffffffff
UNICAM_CAP0(x) MACRO
PM_DUMMY_ONE_CLR 0xfffffffe
DMA3_CS_ABORT_MSB 30
EMMC_BUS_CTRL_MASK 0xffffffff
HDMI_13_AUDIO_STATUS_1_RESET 0000000000
TB_JTB_CONFIG_SPEED_LSB 16
EMMC_IRPT_EN_OEM_ERR_MSB 31
HDMI_FIFO_CTL_USE_FULL_BITS 1:1
SD_DQLCRC5_FALL_SET 0x0000ffff
GROPCTR_FBC_EZ_FETCH_STALLS 0x38
DMA2_DEBUG_LITE_LSB 28
CCP2TX_TS_IS_LSB 16
USB_DPTXFSIZ10_MASK 0xffffffff
DMA1_SOURCE_AD_WIDTH 32
A2W_PLLC_DIG2R_WIDTH 24
V3D_SQRSV1_WIDTH 32
PCM_CS_A_RXERR_BITS 16:16
EMMC_CONTROL0_GAP_STOP_BITS 16:16
CAM0_CAMDBG1_MASK 0xffffffff
AVE_OUT_CTRL_ENABLE_BITS 31:31
DMA_INT_STATUS_INT0_SET 0x00000001
USB_PCGCR_GATE_HCLK_LSB 1
PCM_WID1(x) MACRO
OTP_JTAG_PARITY_MASK 0xFF
USB_GPVNDCTL_REG_WR_SET 0x00400000
CM_DSI0ECTL_BUSYD_CLR 0xfffffeff
CM_GP1CTL_ENAB_CLR 0xffffffef
DMA14_CS_PANIC_PRIORITY_LSB 20
HDMI_FIFO_CTL_CAPTURE_POINTER_SET 0x00000004
CM_TSENSCTL_ENAB_MSB 4
PWMDMAC_PANIC 8
HDMI_RAM_PACKET_11_0 0x7e90258c:RW
HDMI_RAM_PACKET_11_1 0x7e902590:RW
HDMI_RAM_PACKET_11_2 0x7e902594:RW
HDMI_RAM_PACKET_11_3 0x7e902598:RW
HDMI_RAM_PACKET_11_4 0x7e90259c:RW
HD_MAI_DAT_WIDTH 32
HDMI_RAM_PACKET_11_6 0x7e9025a4:RW
HDMI_RAM_PACKET_11_7 0x7e9025a8:RW
HDMI_RAM_PACKET_11_8 0x7e9025ac:RW
MPHI_CTRL_HATVAL_CLR 0xfffffffe
ASB_ISP_M_CTRL_EMPTY_LSB 2
SLIM_DCC4_PA1_WIDTH 24
DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
DMA0_CS_PANIC_PRIORITY_LSB 20
DMA13_TI_WAIT_RESP_LSB 3
DMA8_TI_WAITS_SET 0x03e00000
USB_DTHRCTL_MASK 0x0fff0fff
MPHI_MINFS_RPTR_RESET 0x0
GP_AJBTDI_RESET 0000000000
CM_TD1CTL_STEP_CLR 0xffffefff
PM_RSTS_HADSRH_BITS 10:10
VPU_ARB_CTRL_UC_ALGORITHM_MSB 7
HDMI_DETECTED_VERTB1_MANUAL_VSPO1_BITS 21:9
CM_SMICTL_BUSY_BITS 7:7
ACIS_BASE_ADDRESS 0x1C004800
DMA7_TI_DEST_INC_BITS 4:4
A2W_PLLA_ANA_KAIP_KI_MSB 6
APERF1_BW1_CTRL_LATHALT_LSB 28
HDMI_PACKET_FIFO_CFG_MASK 0x00000001
GP_REN1_MASK 0xffffffff
USB_GI2CCTL_DEV_ADR_LSB 26
A2W_SMPS_L_SIV 0x7e1025d0:RW
I2C0_CLKT_WIDTH 16
SH_CMD_NO_RESPONSE_LSB 10
A2W_PLLH_ANA3R_WIDTH 24
A2W_PLLD_ANA_KAIP_KI_CLR 0xffffff8f
USB_HCCHAR0_LSPD_DEV_RESET 0x0
USB_HCSPLT0_COMP_SPLT_BITS 16:16
DMA12_CS_INT_SET 0x00000004
DMA6_CS_ACTIVE_SET 0x00000001
SCALER_DISPCTRL_DSP0_PANIC_LSB 24
DMA11_NEXTCONBK_ADDR_MSB 31
PM_PADS5_SLEW_SET 0x00000010
CM_PLLH_LOADPIX_BITS 0:0
SD_SB_REORDER_CLR 0xffffff7f
PM_WDOG 0x7e100024:RW
INTERRUPT_JPEG ((64) + 7 )
L2_CONT_OFF_l2_flush_core_limit_CLR 0xff0fffff
A2W_HDMI_CTL_RCAL_SELAVG_SET 0x00000003
USB_DFIFO0 0x7e981000:RW
USB_DFIFO1 0x7e982000:RW
USB_DFIFO2 0x7e983000:RW
MS_MBOX_7_WIDTH 32
JP_QADDR 0x7e005040:RW
USB_DFIFO5 0x7e986000:RW
USB_DFIFO6 0x7e987000:RW
USB_DFIFO7 0x7e988000:RW
USB_DFIFO8 0x7e989000:RW
HD_CSC_CTL_PADMSB_CLR 0xffffffef
EMMC_CONTROL1_CLK_GENSEL_MSB 5
MPHI_RXAXICFG_RXNPRIO_RESET 0x0
EMMC_BUS_CTRL_CLK_PINS_SET 0x00000007
SD_DQRCRC7_FALL_SET 0x0000ffff
USB_DPTXFSIZ12_WIDTH 32
DMA4_STRIDE_S_STRIDE_MSB 15
CCP2TX_TAC_APD_CLR 0xfffffffd
CM_PULSECTL_KILL_CLR 0xffffffdf
L1_D_PRIORITY_c1_per_priority_LSB 24
CM_TDCLKEN_SLIMDFT_SET 0x00001000
DMA3_DEBUG_DMA_ID_MSB 15
MS_SEMA_27_MASK_BITS 0:0
HD_MAI_SMP_WIDTH 32
EMMC_CONTROL2_UHSMODE_BITS 18:16
CM_SYSCTL_GATE_BITS 6:6
SD_DQRCRC3_FALL_BITS 15:0
I2CS_CLKT (1 << 9)
CM_PLLC_ANARST_SET 0x00000100
CM_BURSTCTL_RESET 0000000000
GP_CLR0_RESET 0000000000
DSI0_PHY_AFEC1_WIDTH 32
EMMC_STATUS_WRITE_TRANSFER_LSB 8
USB_DFIFOn(n) MACRO
I2C0_DLEN_RESET 0000000000
DC_OSETTABLE_OFFSET(t) MACRO
IC1_PROFILE_MASK 0x0000ffff
CCP2TX_TS_RESET 0000000000
USB_GOTGCTL_HST_NEG_SCS_LSB 8
CM_PULSECTL_SRC_BITS 1:0
USB_DIEPINT0_IN_EP_NAK_EFF_SET 0x00000040
ARM_I0_BANK2 0x00000200
SH_HSTS_SDIO_IRPT_BITS 8:8
CM_TCNTCTL_WIDTH 14
DMA7_DEBUG_OUTSTANDING_WRITES_LSB 4
DMA6_TI_PERMAP_MSB 20
L1_IC0_PRIORITY_IC0_APRIORITY3_CLR 0xffff0fff
DMA0_CONBLK_AD_SCB_ADDR_LSB 5
DMA10_TI_PERMAP_BITS 20:16
USB_DCTL_PWRON_PRG_DONE_BITS 11:11
A2W_PLLH_ANA1_WIDTH 24
PM_DFT_ALLOWAUDIOCKSTOP_SET 0x00000001
CM_DSI1PCTL_SRC_SET 0x0000000f
USB_GINTMSK_HCH_INT_LSB 25
MPHI_C1INDCF 0x7e00601c:RW
DMA6_DEBUG_LITE_CLR 0xefffffff
SD_DMRCRC1_HIGH_RESET 0x0
APERF1_BW1_AMAX_MASK 0x00ffffff
DMA_DEBUG_READ_ERR (1<<2)
UART_MSR_DCTS_MSB 0
ASB_V3D_M_CTRL_RESET 0x00000007
TS_TSENSCTL_RSTB_SET 0x00000002
USB_GHWCFG2_TOKEN_QUEUE_DEPTH_BITS 30:26
GP_EDS2_EDSn64_CLR 0xffffffc0
SD_DQLCRC0_RISE_MSB 31
DMA5_DEBUG_DMA_STATE_SET 0x01ff0000
DMA13_DEBUG_READ_ERROR_CLR 0xfffffffb
USB_DOEPCTL0_TYPE_MSB 19
PCM_MODE_A_CLK_DIS_SET 0x10000000
USB_DTXFSTS2_MASK 0xffffffff
DMA4_DEBUG_READ_ERROR_MSB 2
DMA2_DEBUG_FIFO_ERROR_SET 0x00000002
EMMC_IRPT_MASK_WRITE_RDY_BITS 4:4
DMA13_TI_SRC_IGNORE_MSB 11
MPHI_HSINDDA_START_SET 0xffffffff
PM_CCP2TX_CTRLEN_MSB 0
DMA15_DEBUG_DMA_ID_BITS 15:8
DMA14_TI_BURST_LENGTH_LSB 12
EMMC_IRPT_EN_CEND_ERR_CLR 0xfffbffff
MPHI_HSINDS_VALID_LSB 30
USB_GHWCFG3_SYNC_RESET_TYPE_LSB 11
V3D_PCTRS11_MASK 0x0000001f
PWM_CTL_RPTL3_CLR 0xfffbffff
MPHI_C1INDDA 0x7e006008:RW
DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
HD_MAI_CTL_ENABLE_MSB 3
SH_HSTS_SDIO_IRPT_CLR 0xfffffeff
CM_TECCTL_BUSYD_MSB 8
CM_OSCFREQI_INT_LSB 0
USB_GUSBCFG_FORCE_HST_MODE_CLR 0xdfffffff
GP_PUDCLK1_PUDCLKn32_BITS 31:0
HDMI_RAM_PACKET_8_0 0x7e902520:RW
HDMI_RAM_PACKET_8_1 0x7e902524:RW
HDMI_RAM_PACKET_8_2 0x7e902528:RW
HDMI_RAM_PACKET_8_3 0x7e90252c:RW
HDMI_RAM_PACKET_8_4 0x7e902530:RW
A2W_PLLD_ANA_SSCS_STEP_BITS 15:0
CM_TSENSCTL_KILL_CLR 0xffffffdf
L1_IC1_PRIORITY_IC1_APRIORITY0_MSB 3
CM_ISPCTL_RESET 0x00000040
EMMC_HWCAP1_DRV18_TYPEA_LSB 4
L1_L1_SANDBOX_START7_START_ADDR_BITS 29:5
USB_DIEPDMAB0 0x7e980918:RW
SMI_DA_WIDTH 10
CM_DSI0ECTL_ENAB_CLR 0xffffffef
SMIDCS 0x7e600000 + 0x34:RW
HDMI_RAM_PACKET_11_5_RESET 0000000000
DMA10_TI_SRC_WIDTH_CLR 0xfffffdff
VEC_CONFIG1 0x7e806188:RW
VEC_CONFIG2 0x7e80618c:RW
VEC_CONFIG3 0x7e8061a0:RW
VEC_CONFIG4 0x7e8061a4:RW
CM_DSI0PCTL_BUSYD_LSB 8
MPHI_CTRL_REQ_SOFT_RST_RESET 0x0
A2W_PLLD_CTRL_WIDTH 18
SD_RWC_RXOVR_CLR 0xffffff7f
A2W_PLLC_PER_BYPEN_SET 0x00000200
AVE_IN_SYNC_CTRL_MASK 0x0000008f
IC1_C_MASK 0x0000000f
FPGA_CTRL0_SPI1_SEL_CLR 0xfffffbff
APERF0_BW1_CTRL_RESET_MSB 31
GP_FSEL5_FSEL51_CLR 0xffffffc7
USB_DIEPDMAB2 0x7e980958:RW
SD_DQRCRC15_FALL_BITS 15:0
MPHI_RXAXICFG_RXPPRIO_SET 0x000000f0
UART_LCR_EPS_LSB 4
IC0_MASK5_WIDTH 31
USB_HCCHAR4_WIDTH 32
HDMI_DETECTED_VERTA0_MANUAL_VAL0_CLR 0xffffe000
DMA15_DEBUG_LITE_MSB 28
AVE_IN_BUF0_ADDRESS_MASK 0xffffffff
CM_EVENT_FGAINC_CLR 0xffffefff
DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
APERF1_BW1_CTRL 0x7ee08080:RW
CM_TCNTCNT_CNT_BITS 23:0
GP_FSEL5_FSEL51_MSB 5
USB_DOEPCTL0_CNAK_RESET 0x0
SD_DQRCRC3_WIDTH 32
USB_HCINT0_CH_HLTD_RESET 0x0
CM_CAM0CTL_SRC_SET 0x0000000f
UART_LCR_LOOP_LSB 4
USB_GINTMSK_SESS_REQ_INT_RESET 0x0
A2W_PLLD_DSI0_CHENB_CLR 0xfffffeff
GPLEN0 0x7e200000 + 0x70:RW
GPLEN1 0x7e200000 + 0x74:RW
GPLEN2 0x7e200000 + 0x78:RW
SD_CS_STOP_CLR 0xffffff7f
USB_DIEPINT0_TXF_EMPTY_CLR 0xffffff7f
DMA3_TI_PERMAP_BITS 20:16
SD_CS_IDLE_LSB 9
SD_DQLCRC15_RISE_SET 0xffff0000
A2W_PLLH_DIG2R_MASK 0x00ffffff
EMMC_INTERRUPT_DCRC_ERR_MSB 21
CM_CAM1CTL_FRAC_CLR 0xfffffdff
ASB_CPR_CTRL_CLR_REQ_CLR 0xfffffffe
APERF1_BW1_CTRL_ID_EN_LSB 29
SLIM_DCC8_CON 0x7e210308:RW
UART_MSR_DCTS_BITS 0:0
FPGA_DCM_CTRL_PERI_RST_MSB 19
DMA7_CS_PRIORITY_BITS 19:16
FPGA_CTRL0_TV_ACTIVITY_CLR 0xffffdfff
USB_DCFG_PER_FR_INT_BITS 12:11
GP_CLR2_CLRn64_SET 0x0000003f
EMMC_IRPT_EN_CARD_MSB 8
A2W_SMPS_L_SCV_WIDTH 5
CM_TD0CTL_FRAC_MSB 9
CM_TECCTL_BUSY_LSB 7
PIXELVALVE1_VERTA 0x7e207014:RW
PCMMODE_PDMRX (1 << 26)
CMI_CAM0_HSSRC_CLR 0xfffffffc
MPHI_C0INDDA_START_MSB 31
USB_GUSBCFG_HNP_CAP_MSB 9
CM_GP2DIV_WIDTH 24
DMA8_CS_ERROR_BITS 8:8
USB_HCINT0_NAK_CLR 0xffffffef
MPHI_HSINDS_HANDLE_CLR 0xe01fffff
GP_FSEL5_FSEL54_BITS 14:12
DMA11_CS_END_LSB 1
PM_GNRIC_CFG_MSB 22
DMA8_TI_DEST_WIDTH_LSB 5
UART_LCR_OUT1_SET 0x00000004
L1_IC0_PRIORITY_IC0_APRIORITY2_LSB 8
DMA5_DEBUG_READ_ERROR_MSB 2
A2W_SMPS_L_SPA 0x7e1022d0:RW
FPGA_CTRL0_LV_SPARE_OUT_BITS 19:18
USB_GUSBCFG_TOUT_CAL_MSB 2
DMA3_CS_RESET_CLR 0x7fffffff
MPHI_C0INDS_HANDLE_RESET 0x0
EMMC_IRPT_EN_CEND_ERR_BITS 18:18
USB_GPVNDCTL_STS_DONE_RESET 0x0
PM_IMAGE_MEMREP_LSB 3
DMA5_TI_DEST_INC_MSB 4
PM_SPAREW_SPARE_LSB 0
PM_CAM0 0x7e100044:RW
PM_CAM1 0x7e100048:RW
SYSAC_UC_ARBITER_CONTROL_RESET 0000000000
PCM_GRAY_RXLEVEL_SET 0x000003f0
PM_PADS6_DRIVE_SET 0x00000003
A2W_PLLH_ANA_STAT_RCALCODE_SET 0x000f0000
USB_GLPMCFG_MASK 0xffffffff
I2C2_DEL_MASK 0xffffffff
L1_IC1_RAS_PUSHES_MASK 0000000000
SD_CS_PUSKIP_LSB 4
A2W_PLLB_DIG1 0x7e1020e4:RW
DMA0_TI_SRC_DREQ_LSB 10
GP_FSEL6_FSEL61_SET 0x00000038
AVE_IN_BASE 0x7e910000
SD_CS_DPD_SET 0x00000004
SCALER_DISPSTAT_DSP2_STATUS_MSB 29
MS_MBOX_7_MASK 0xffffffff
CM_CKSM_STATE_BITS 7:0
SH_CMD_WIDTH 16
EMMC_INTERRUPT_ADMA_ERR_LSB 25
SD_PHYC_IOB_TMODE_MSB 12
USB_DIEPINT0_OUT_TKN_EP_DIS_BITS 4:4
USB_GHWCFG2_NUM_HOST_CHAN_MSB 14
CMI_CAM1_RX3SRC_SET 0x00000300
APERF0_BW2_CTRL_EN_BITS 30:30
CAM0_CAMMISC_MASK 0xffffffff
USB_DOEPINT2_WIDTH 32
GP_SET0 0x7e20001c:RW
DMA0_TXFR_LEN_YLENGTH_SET 0x3fff0000
A2W_PLLB_ANA3_RESET 0x00000180
AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_SET 0x80000000
DMA8_DEBUG_LITE_MSB 28
HDMI_DETECTED_HORZA_MANUAL_HPOL_MSB 13
HDMI_SW_RESET_CNTRL_WIDTH 2
SD_SECSRT2_WIDTH 32
SMI_DSR1_RWIDTH_SET 0xc0000000
CM_PLLC_LOADCORE2_CLR 0xffffffef
DMA8_CS_INT_SET 0x00000004
DMA15_TI_WAIT_RESP_LSB 3
DMA4_CS_PANIC_PRIORITY_LSB 20
SMI_CS_PRDY_LSB 24
TXP_CTRL_TFORMAT_SET 0x00000020
CM_INTEN_LOSSD_SET 0x00000100
PM_GNRIC_ISFUNC_BITS 5:5
USB_GUSBCFG_PHY_SEL_RESET 0x0
CM_AVEOCTL_FRAC_CLR 0xfffffdff
CM_BURSTCNT_WIDTH 24
TB_HOST_WIDTH 32
CAM0_CAMSTA_MASK 0xffffffff
USB_DSTS_SOF_FN_BITS 21:8
DMA14_TI_DEST_IGNORE_LSB 7
I2C_SPI_SLV_RSR_RXDMABREQ_CLR 0xffffffdf
HDMI_CP_INTEGRITY_CFG_WIDTH 17
USB_HPRT_EN_CHNG_SET 0x00000008
CM_SYSCTL_GATE_CLR 0xffffffbf
DMA8_CONBLK_AD_SCB_ADDR_LSB 5
DMA9_SOURCE_AD_MASK 0xffffffff
ASB_ISP_S_CTRL_EMPTY_MSB 2
PWM_DAT3_WIDTH 0
A2W_XOSC_BIAS_BIAS_MSB 3
HDMI_MAI_CHANNEL_MAP 0x7e902090:RW
HDMI_VERTA1_MANUAL_VFP1_SET 0x000fe000
USB_GRXSTSR_MASK 0xffffffff
HDMI_CEC_CNTRL_3_RESET 0x96826f5c
UART_LCR_OUT2_MSB 3
DMA11_TI_DEST_WIDTH_LSB 5
MPHI_INTSTAT_RX1DISC_SET 0x01000000
DMA15_CONBLK_AD_MASK 0xffffffe0
CM_VPUDIV_WIDTH 24
A2W_PLLA_ANA_VCO_RANGE_SET 0x00000001
PIXELVALVE2_HORZB_MASK 0xffffffff
ASB_V3D_S_CTRL_RCOUNT_CLR 0xffffc00f
SD_SECSRT2_ADDR_LS_MSB 12
DMA13_TI_SRC_INC_LSB 8
AUX_SPI_STAT_BUSY 0x00000040
CM_GP0CTL_KILL_MSB 5
PWM_DMAC_PANIC_LSB 8
PIARBCTL_CAM_CHANNEL_INIBIT_MSB 15
APERF1_BW1_WTRANS_MASK 0xffffffff
DMA6_TI_WAITS_LSB 21
L1_IC1_CONTROL_DISABLE_VLINE_BITS 6:5
GP_FSEL3_FSEL32_LSB 6
SH_ARG_ARGUMENT_SET 0xffffffff
SYSAC_L2_ARBITER_CONTROL_THRESHOLD_CLR 0xffffffcf
IC0_WAKEUP_WIDTH 32
A2W_PLLC_DIG0_MASK 0x00ffffff
DMA0_TI_DEST_WIDTH_SET 0x00000020
EMMC_EXRDFIFO_CFG_RD_THRSH_CLR 0xfffffff8
DMA8_DEBUG_OUTSTANDING_WRITES_BITS 7:4
USB_DFIFO7_WIDTH 32
DMA12_CS_DREQ_STOPS_DMA_BITS 5:5
APERF1_BW0_ATWAIT 0x7ee08048:RO
A2W_PLLB_ANA_STAT_DATA_BITS 11:0
A2W_PLLC_FRAC_FRAC_CLR 0xfff00000
USB_GOTGCTL_DEV_HNP_EN_BITS 11:11
USB_DIEPTSIZ0_XFERSIZE_MSB 18
CMI_CAM1_RX1SRC_CLR 0xffffffcf
SD_DQLCRC7_RISE_MSB 31
A2W_SMPS_A_GAIN_DIGGAIN_BITS 2:0
SCALER_DISPECTRL_POSTED_STATUS_CLR 0xffff8fff
PCMCS_RXON (1 << 1)
DC1END 0xffffffff:RW
DMA_INT_STATUS_INT11_SET 0x00000800
DMA7_CS_END_SET 0x00000002
APERF0_BW0_RPEND 0x7e009868:RO
USB_GHWCFG2_FSPHY_INTERFACE_LSB 8
A2W_PLLC_ANA_SSCS_STEP_LSB 0
USB_DOEPTSIZ10_MASK 0xffffffff
PM_AVS_STAT_ALERT_ARM_P_MSB 4
GP_EDS2_EDSn64_SET 0x0000003f
SCALER_INPUT_CONTROL 0x7e400000 + 0x00:RW
AUX_SPI_CNTL0_CS0_N 0x000C0000
GP_FSEL0 0x7e200000:RW
DMA2_SOURCE_AD_WIDTH 32
USB_GRSTCTL_TXF_FLSH_LSB 5
SD_DQRCRC9_MASK 0xffffffff
HDMI_RAM_PACKET_9_8_MASK 0xffffffff
EMMC_HWCAP1_SDR50_TUNE_CLR 0xffffdfff
A2W_PLLA_DSI0R_RESET 0x00000100
INTERRUPT_PWA0 ((64) + 45 )
A2W_PLLA_CTRL_WIDTH 18
CCP2TX_TD_IES_BITS 6:5
CM_EVENT_BURSTDONE_MSB 23
CM_TIMERCTL_MASK 0x000003b3
GP_FSEL2_FSEL27_LSB 21
GR_TU_UNIT_MASK 0xFFFFFF1F
PM_GNRIC_MRDONE_MSB 4
EMMC_INTERRUPT_BLOCK_GAP_SET 0x00000004
SMI_DSR2_RDREQ_SET 0x00000080
SMI_DCS_DONE_CLR 0xfffffffb
MPHI_MINFS_OFLOW_SET 0x80000000
UART_LCR_RTS_MSB 1
EMMC_SLOTISR_VER_SDVERSION_LSB 16
MPHI_CTRL_REQ_SOFT_RST_LSB 16
A2W_XOSC_BIASR_RESET 0x00000018
SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_SET 0x00000003
CM_TD0CTL_ENAB_LSB 4
JP_BASE 0x7e005000
CM_PLLC_ANARST_LSB 8
PCMCS_RXTHR_1_QUARTER (1 << 7)
DMA13_TI_INTEN_CLR 0xfffffffe
SDRSP0 SDCARD_BASE + 0x10:RW
SDRSP1 SDCARD_BASE + 0x14:RW
A2W_PLLB_ANA_STAT_DATA_CLR 0xfffff000
SDRSP3 SDCARD_BASE + 0x1C:RW
DMA3_CS_DREQ_CLR 0xfffffff7
VPU_ARB_CTRL_UC_CHANNEL_INIBIT_SET 0x0000ff00
CCP2TX_TIC_WIDTH 8
SYSAC_PERI_ARBITER_CONTROL_DELAY_MSB 3
GRPCDSM 0x1A005600 + 0x58:RW
EMMC_HWMAXAMP0_AMP_30V_LSB 8
DMA12_CS_ERROR_SET 0x00000100
GP_FSEL3_FSEL33_MSB 11
GRMSSI0 0x1A005C00 + 0x20:RW
GRMSSI1 0x1A005C00 + 0x24:RW
SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_RESET 0x0
MS_MBOX_1_RESET 0000000000
A2W_PLLC_ANA1_MASK 0x00ffffff
SLIM_DCC2_PA0_RESET 0000000000
PWM_CTL_USEF4_SET 0x20000000
EMMC_CONTROL0_SPI_MODE_CLR 0xffefffff
DMA0_CS_PRIORITY_CLR 0xfff0ffff
IC0_FORCE0_MASK 0xffffffff
DMA8_CONBLK_AD_MASK 0xffffffe0
SH_HSTS_CRC16_ERROR_SET 0x00000020
SMI_DSR2_RDREQ_BITS 7:7
USB_DPTXFSIZ5_MASK 0xffffffff
A2W_PLLD_DSI0_RESET 0x00000100
HDMI_RAM_BASE (HDMI_BASE_ADDRESS + 0x400)
DMA0_DEBUG_READ_ERROR_BITS 2:2
SD_DQRCRC9_RISE_MSB 31
EMMC_IRPT_MASK_SDOFF_ERR_CLR 0xff7fffff
MPHI_C1INDDB_HANDLE_RESET 0x0
PWM_STA_STA3_BITS 11:11
V3D_SRQUL_WIDTH 12
HDMI_CPU_MASK_STATUS_WIDTH 32
USB_GNPTXSTS_TX_Q_TOP_SET 0x7f000000
GP_EDS2_MASK 0x0000003f
DMA6_TI_WAIT_RESP_SET 0x00000008
CCP2RLS0 CCP2_BASE_ADDRESS + 0x11C:RW
CCP2RLS1 CCP2_BASE_ADDRESS + 0x21C:RW
EMMC_INTERRUPT_CMD_DONE_LSB 0
L1_IC0_BP_HITS_MASK 0000000000
TB_PRINTER_CTRL_OFFSET_CLR 0xfffffffc
USB_GRXSTSP_HST_DPID_RESET 0x0
A2W_SMPS_LDO0_RESET 0000000000
HDMI_RAM_PACKET_STATUS 0x7e9020a4:RW
VEC_CFG_MASK 0xffffffff
GPLEV1 0x7e200000 + 0x38:RW
GPLEV2 0x7e200000 + 0x3C:RW
SYSAC_V3D_PRIORITY_PRIORITY_CLR 0xfffffff0
HDMI_RAM_PACKET_13_0_RESET 0000000000
EMMC_HWCAP0_V1_8_CLR 0xfbffffff
DMA6_DEBUG_WIDTH 29
USB_GAHBCFG_H_BST_LEN_BITS 4:1
USB_DFIFO4_MASK 0xffffffff
USB_DIEPEMPMSK_EP_TXF_EMP_MSK_RESET 0x0
EMMC_HWCAP0_MASK 0xffffffff
DSI1_PHY_AFEC1_WIDTH 32
AVE_OUT_Y_COEFF_RED_COEFF_MSB 29
OTP_BOOT_ROM_SIZE_IN_ROWS 1
CM_HSMCTL_BUSY_CLR 0xffffff7f
CM_PLLTCNT0_CNT_BITS 23:0
CM_OTPCTL_ENAB_SET 0x00000010
DMA4_TI_SRC_INC_SET 0x00000100
MPHI_C1INDDB_MORUN_MSB 31
CAM1_CAMICC_WIDTH 32
A2W_PLLB_FRAC_FRAC_SET 0x000fffff
DMA6_TI_TDMODE_MSB 1
I2C_SPI_SLV_RIS_BERIS_SET 0x00000004
DMA_INT_STATUS_INT1_LSB 1
A2W_PLLD_DSI0_DIV_CLR 0xffffff00
CSI2_RSA1 CSI2_BASE_ADDRESS + 0x20C:RW
I2C_SPI_SLV_DR_TXFF_LSB 18
DMA7_CONBLK_AD 0x7e007704:RW
DMA7_CS_END_LSB 1
HD_VID_CTL_BLANKPIX_RESET 0x1
USB_GI2CCTL_SUSP_CTL_LSB 25
SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_CLR 0xfffffffc
PM_AVS_RSTDR_ROSC_LSB 5
DSI1_HS_CLT1_WIDTH 32
DPHY_CSR_CRC_CTRL_MASK 0x00000111
MPHI_HSINDFS_MASK 0xffff0001
DMA13_TI_INTEN_BITS 0:0
SD_DQLCRC0_RISE_BITS 31:16
A2W_SMPS_A_VOLTS_MASK 0x0000001f
AVE_IN_LINE_NUM_INT_LINE_NUM_INT_BITS 11:0
GP_LEV2_WIDTH 6
FPGA_DCM_CTRL_REMOTE_EN_MSB 12
HDMI_CPU_MASK_SET_RESET 0x0001ffff
JC2BA 0x7e005000 + 0x54:RW
APERF1_BW1_CTRL_RESET_RESET 0x0
APERF0_GEN_CTRL_RESET_LSB 1
DMA5_CS_INT_SET 0x00000004
CM_TD1CTL_BUSY_MSB 7
PM_IMAGE_MRDONE_CLR 0xffffffef
V3D_DBQITE_MASK 0xffffffff
CM_SDCCTL_ENAB_SET 0x00000010
A2W_PLLH_CTRL_NDIV_CLR 0xffffff00
AVE_IN_STATUS_CAPTURING_BITS 31:31
DMA14_DEBUG_VERSION_SET 0x0e000000
TB_TASK_PARAM2 0x7e20b008:RW
DMA13_DEBUG_DMA_STATE_SET 0x01ff0000
A2W_SMPS_L_MULTI_MASK 0000000000
DSI0_HS_CLT2_RESET 0000000000
USB_DCFG_NZ_STS_OUT_HSHK_MSB 2
AVE_IN_LINE_LENGTH_LINE_LENGTH_CLR 0xfffff000
HD_HDM_CTL_CECRXD_MSB 9
A2W_PLLA_CCP2_DIV_LSB 0
DMA12_DEBUG_DMA_STATE_BITS 24:16
UART_MSR_DDSR_SET 0x00000002
DMA1_TXFR_LEN_YLENGTH_BITS 29:16
GP_FSEL2_FSEL20_CLR 0xfffffff8
USB_DIEPCTL0_CNAK_BITS 26:26
CCP2TX_TTC_ATX_MSB 31
SMI_CS_PAD_CLR 0xffffff3f
SMI_DSR3_WIDTH 32
USB_GI2CCTL_ADDR_SET 0x007f0000
GP_LEN1_LENn32_MSB 31
I2C_SPI_SLV_CR_CPHA_LSB 3
USB_PCGCR_STOP_PCLK_MSB 0
CM_ISPDIV_DIV_SET 0x0000fff0
AVE_OUT_CTRL_SOFT_RESET_CLR 0xbfffffff
A2W_PLLD_ANA1 0x7e102054:RW
HD_MAI_CTL 0x7e808014:RW
A2W_PLLB_ANA1_WIDTH 24
GP_FSEL5_FSEL54_CLR 0xffff8fff
PM_PROC_MEMREP_SET 0x00000008
USB_DOEPCTL0 0x7e980b00:RW
UART_LCR 0x7e20100c:RW
CM_TD0CTL_WIDTH 13
APERF1_BW2_RTRANS_WIDTH 32
DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
A2W_PLLB_DIG1R_MASK 0x00ffffff
USB_DIEPCTL0_NAK_STS_RESET 0x0
USB_DOEPINT0_OUT_PKT_ERR_LSB 8
A2W_PLLH_ANA_VCO_RANGE_MSB 0
CM_CAM1DIV 0x7e10104c:RW
ASB_H264_S_CTRL_RCOUNT_CLR 0xffffc00f
SPI_CLK_CDIV_CLR 0xffff0000
AUX_MU_LSR_THRE 0x20
DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
EMMC_STATUS_NEW_WRITE_DATA_MSB 10
SMI_DSW1_MASK 0xffffffff
HDMI_HORZB_MANUAL_HSP_SET 0x000ffc00
A2W_PLLA_DSI0_DIV_BITS 7:0
SD_DQRCRC3_RISE_LSB 16
I2C_SPI_SLV_DR_RXBUSY_LSB 21
DMA3_DEBUG_DMA_STATE_LSB 16
SLIM_CON2_WIDTH 32
DMA7_TI_DEST_WIDTH_MSB 5
DMA14_TXFR_LEN_XLENGTH_LSB 0
DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
HDMI_DETECTED_VERTB0_MANUAL_VBP0_MSB 8
GROPCTR_FBC_EZ_PBE_REQS 0x34
DMA9_DEST_AD_D_ADDR_BITS 31:0
TB_JTB_CONFIG_WIDTH 32
HD_HDM_CTL_RFSTBY_BITS 7:6
GP_FSEL6_FSEL60_CLR 0xfffffff8
AVE_OUT_CTRL_NTSC_PAL_IDENT_SET 0x00002000
HDMI_CEC_CNTRL_1_WIDTH 32
AVE_IN_STATUS_AXI_STATE_BITS 22:20
EMMC_STATUS_WRT_PROTECT_BITS 19:19
VCE_SEMA_SET_OFFSET 0x40028
SCALER_DISPCTRL_DSP1_IRQ_CTRL_LSB 9
USB_DFIFO13_MASK 0xffffffff
A2W_PLLA_ANA3R_RESET 0x00000180
EMMC_IRPT_MASK_DEND_ERR_CLR 0xffbfffff
DSI0_PHYC_txhsclk_cont_sync_SET 0x00000400
DMA8_CS_PANIC_PRIORITY_LSB 20
MPHI_C1INDDB_LENGTH_SET 0x000fffff
EMMC_BOOT_TIMEOUT_WIDTH 32
DMA9_TI_BURST_LENGTH_BITS 15:12
HD_VID_CTL_CLRRGB_BITS 23:23
AVE_OUT_STATUS_HFRONT_PORCH_CLR 0xffffffef
AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_LSB 31
EMMC_STATUS_DAT_INHIBIT_LSB 1
UART_LSR_PE_BITS 2:2
DMA12_CS_PANIC_PRIORITY_CLR 0xff0fffff
VEC_CONFIG2_WIDTH 32
USB_DOEPCTL7 0x7e980be0:RW
DMA2_TI_BURST_LENGTH_MSB 15
SD_DQRCRC7_RISE_SET 0xffff0000
USB_GHWCFG4_EN_DESC_DMA_SET 0x40000000
HDMI_HORZA_WIDTH 15
CM_DSI0ECTL_FRAC_SET 0x00000200
USB_GNPTXSTS_TXF_SPC_AVAIL_LSB 0
DMA2_TI_DEST_IGNORE_MSB 7
EMMC_HWCAP1_SDR50_TUNE_MSB 13
MS_SEMA_12_MASK_BITS 0:0
PM_PADS5_HYST_CLR 0xfffffff7
PCM_CS_A_TXTHR_BITS 6:5
DMA14_CS_PRIORITY_CLR 0xfff0ffff
SCALER_DISPECTRL_PROF_TYPE_CLR 0xf3ffffff
CM_SDCCTL_CTRL_BITS 15:12
TB_PRINTER_CTRL_TASKNO_LSB 4
GP_FSEL6_FSEL66_MSB 20
VCINTMASK0 0x7f000000 + 0x4408b8:RW
VCINTMASK1 0x7f000000 + 0x4408c0:RW
APERF1_BW2_CTRL_LATHALT_SET 0x10000000
HDMI_RAM_PACKET_6_6_RESET 0000000000
EMMC_ARG2_MASK 0xffffffff
PM_PXLDO_RSTPLLDR_LSB 17
MPHI_MINFS_OFLOW_BITS 31:31
SMI_DSW1_WSTROBE_LSB 0
CAM1_CAMDAT2_RESET 0x00000002
SMI_DSW1_WSWAP_CLR 0xffbfffff
SDSECSRT0 0x7ee0003c:RW
SDSECSRT1 0x7ee00044:RW
SDSECSRT2 0x7ee0004c:RW
SDSECSRT3 0x7ee00054:RW
USB_GHWCFG4_EN_DED_TX_FIFO_RESET 0x0
SMI_DSW1_WDREQ_MSB 7
A2W_PLLH_ANA2R_MASK 0x00ffffff
CM_TDCLKEN_PLLADIV2_CLR 0xffffffef
SCALER_DISPCTRL_IRQ_EN_SET 0x0000007f
APERF1_BW1_CTRL_BUS_MSB 4
DMA6_TI_DEST_INC_MSB 4
SMI_DA_WRITE_BITS 9:8
PWM_CTL_MSEN3_CLR 0xff7fffff
A2W_PLLA_ANA_SCTL_RESET_CLR 0xffffffef
DMA5_TI_SRC_IGNORE_CLR 0xfffff7ff
SH_CDIV_CLOCKDIV_BITS 10:0
EMMC_CONTROL2_ACTO_ERR_SET 0x00000002
A2W_PLLB_SP1_BYPEN_MSB 9
A2W_PLLB_DIG2R_MASK 0x00ffffff
V3D_PCTRE_MASK 0x8000ffff
APERF1_BW0_WMAX 0x7ee08058:RO
AVE_IN_FRAME_NUM 0x7e910044:RW
PWM_STA_BERR_CLR 0xfffffeff
DMA10_TI_DEST_WIDTH_MSB 5
PCM_CS_A_TXW_LSB 17
APERF0_BW1_AMAX_MASK 0x00ffffff
DMA0_CS_ABORT_CLR 0xbfffffff
L2_RD_MISSES_WIDTH 32
L1_L1_SANDBOX_END1 0x7ee0280c:RW
L1_L1_SANDBOX_END2 0x7ee02814:RW
L1_L1_SANDBOX_END3 0x7ee0281c:RW
L1_L1_SANDBOX_END4 0x7ee02824:RW
L1_L1_SANDBOX_END5 0x7ee0282c:RW
A2W_PLLA_DSI0_RESET 0x00000100
L1_L1_SANDBOX_END7 0x7ee0283c:RW
DMA12_NEXTCONBK_ADDR_MSB 31
V3D_SQCSTAT_WIDTH 32
PM_SMPS_RSTDR_BITS 1:1
DMA4_TI_WAIT_RESP_BITS 3:3
AVE_IN_MAX_TRANSFER_MAX_TRANSFER_CLR 0x00000000
PIXELVALVE2_STAT_WIDTH 10
I2C_SPI_SLV_IFLS_TXIFPSEL_BITS 8:6
DMA8_CS_ACTIVE_CLR 0xfffffffe
FPGA_CTRL0_TERMEN_DO_CLR 0xfffeffff
I2C_SPI_SLV_CR_ENCTRL_MSB 6
DMA10_DEST_AD_D_ADDR_MSB 31
SYSAC_V3D_LIMITER_MAX_PRIORITY_CLR 0xffffff07
TS_TSENSCTL_THOLD_MSB 17
V3D_PCTR0_WIDTH 32
USB_GAHBCFG_GLBL_INTR_MSK_MSB 0
USB_DIEPTXF6_WIDTH 32
DMA8_SOURCE_AD_S_ADDR_MSB 31
DMA9_DEBUG_DMA_ID_LSB 8
SD_SE_T_RTP_SET 0x00000700
PM_DSI0_WIDTH 21
DMA0_DEST_AD_WIDTH 32
USB_GHWCFG4_EN_SESSIONEND_FILTER_SET 0x01000000
USB_DIEPTSIZ0_MASK 0xffffffff
DPHY_CSR_GLBL_DQ_DLL_CNTRL 0x7ee0700c:RW
FPGA_CTRL0_DIS_SW_SPI_SET 0x00000020
SMI_DC_DMAP_LSB 24
CM_TD0CTL_BUSY_SET 0x00000080
USB_GINTMSK_CUR_MOD_CLR 0xfffffffe
A2W_PLLB_ANA_SSCS_STEP_MSB 15
A2W_PLLH_PIX_CHENB_LSB 8
PCM_TXC_A_WIDTH 32
CM_AVEOCTL_SRC_CLR 0xfffffff0
CM_TD1CTL_FRAC_BITS 9:9
AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_SET 0x20000000
USB_DIEPCTL0_SET_ODD_FR_MSB 29
A2W_HDMI_CTL0_WIDTH 24
I2C_SPI_SLV_ICR_OEIC_MSB 3
USB_HPRT_SUSP_LSB 7
USB_DIEPCTL0_SET_D1_PID_SET 0x20000000
PIXELVALVE1_VC_WIDTH 23
L2_FLUSH_STA_MASK 0x0fffffe0
HD_MAI_CTL_RST_MAI_CLR 0xfffffffe
MPHI_C1INDDB_MTERM_SET 0x10000000
SLIM_DMA_DC_STAT_1_MASK 0x000f000f
USB_HCINT0_XACT_ERR_CLR 0xffffff7f
DMA7_CS_DISDEBUG_SET 0x20000000
A2W_PLLC_ANA_SCTL_RESET_BITS 4:4
USB_DCFG_DEV_SPD_LSB 0
DMA2_STRIDE_S_STRIDE_MSB 15
DMA0_CS_DREQ_SET 0x00000008
V3D_PCTRS14_WIDTH 5
WSE_RESET 0x7e8060c0:RW
CAM0_CAMMISC_WIDTH 32
A2W_SMPS_L_SCV 0x7e1023d0:RW
CM_PLLA_DIGRST_LSB 9
DMA9_DEBUG_DMA_STATE_MSB 24
CM_TCNTCTL_BUSY_CLR 0xffffff7f
DMA4_DEBUG_READ_ERROR_BITS 2:2
MPHI_MOUTFS_WPTR_MSB 19
VEC_FREQ3_2 0x7e806180:RW
L1_D_FLUSH_S_RESET 0000000000
DMA2_CS_INT_SET 0x00000004
SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_BITS 1:0
CM_CKSM_STEP_CLR 0xffdfffff
USB_DSTS_MASK 0x003fff0f
L1_L1_SANDBOX_PERI_BR_sandbox_bootrom_CLR 0xffffffe0
USB_DTXFSTS14_WIDTH 32
PM_DSI0_LDOCTRL_BITS 20:3
USB_GHWCFG2_DFIFO_DYNAMIC_LSB 19
UART_LCR_OUT2_LSB 3
EMMC_CONTROL0_PWCTL_SDVOLTS_BITS 11:9
UART_LCR_OUT2_CLR 0xfffffff7
SD_VIN_CLEAR_MSB 31
PM_GNRIC_MRDONE_LSB 4
HDMI_READ_POINTERS_DOMAIN_WR_ADDR_LSB 27
L1_D_PRIORITY_c0_l2_priority_LSB 0
DMA10_CS_ERROR_LSB 8
A2W_PLLC_ANA_KAIP_WIDTH 11
DMA13_TXFR_LEN_WIDTH 16
APERF1_BW1_ATRANS 0x7ee08084:RO
EMMC_CMDTM_TM_DMA_EN_CLR 0xfffffffe
DSI0_CMD_DATAF 0x7e209014:RW
SH_CDIV_RESET 0x000001fb
CM_SDCCTL_SRC_CLR 0xfffffff0
DMA2_TI_DEST_DREQ_SET 0x00000040
SLIM_DCC3_CON_MASK 0xffff0070
MS_SEMA_20_RESET 0000000000
SMI_DSW2_WPACEALL_MSB 15
EMMC_IRPT_EN_ENDBOOT_CLR 0xffffbfff
HDMI_RAM_GCP_8_MASK 0xffffffff
PM_RSTS_HADPOR_CLR 0xffffefff
DMA8_DEST_AD_D_ADDR_CLR 0x00000000
PWM_STA_WERR1_BITS 2:2
A2W_PLLA_CTRL_PDIV_SET 0x00007000
DMA5_CS_DISDEBUG_CLR 0xdfffffff
SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_SET 0x00000030
GP_FSEL6_FSEL62_LSB 6
SD_CS 0x7ee00000:RW
PIARBCTL_CAM_ALGORITHM_CLR 0xffffff3f
HDMI_RAM_PACKET_10_3_MASK 0xffffffff
USB_DOEPDMA1 0x7e980b34:RW
USB_DOEPDMA2 0x7e980b54:RW
USB_DOEPDMA3 0x7e980b74:RW
VEC_CPS2425_CPS2627 0x7e806138:RW
USB_DOEPDMA5 0x7e980bb4:RW
SD_SA_PGEHLDE_SET 0x00000100
USB_GAHBCFG_WIDTH 9
USB_DOEPDMA8 0x7e980c14:RW
CM_DSI0PCTL_ENAB_SET 0x00000010
I2C_SPI_SLV_IFLS_MASK 0x00000fff
GP_EDS1_WIDTH 32
DMA11_CS_DISDEBUG_SET 0x20000000
PWM_CTL_USEF3_LSB 21
EMMC_BLKSIZECNT_SDMA_BLKSIZE_SET 0x00007000
MPHI_HSINDFS_CFIFOLVL_CLR 0x0000ffff
DSI0_PIX_FIFO_WIDTH 32
SH_ARG_WIDTH 32
DMA5_TI_DEST_IGNORE_SET 0x00000080
PWM_DAT1_MASK 0xffffffff
SD_DQLCRC0_FALL_MSB 15
I2C_SPI_SLV_CR_SPI_MSB 1
USB_DCFG_DEV_ADDR_SET 0x000007f0
SH_HCFG_REL_CMD_LINE_MSB 0
USB_DTXFSTS1_WIDTH 32
USB_GHWCFG3_SYNC_RESET_TYPE_CLR 0xfffff7ff
DMA7_TI_INTEN_CLR 0xfffffffe
ARM_2_BELL0 (0x7E00B000 +0xA00)+0x40:RW
A2W_XOSC1R_MASK 0x00ffffff
ARM_2_BELL2 (0x7E00B000 +0xA00)+0x48:RW
ARM_2_BELL3 (0x7E00B000 +0xA00)+0x4C:RW
DMA13_CS_INT_LSB 2
CM_TIMERCTL_BUSY_MSB 7
AVE_IN_SYNC_CTRL_RESET 0000000000
MPHI_OUTDS_WORDS_SET 0x001fffff
APERF1_GEN_CTRL 0x7ee08000:RW
AVE_IN_STATUS_FRAME_RATE_MSB 9
DMA6_CS_ERROR_SET 0x00000100
CM_PLLA_HOLDDSI0_LSB 1
ARM_C0_APROTUSER 0x00000000
SCALER_BASE_ADDRESS 0x7e400000
I2C_SPI_SLV_CR_INV_TXF_MSB 13
VCE_BUSY_BKPT 0x00
USB_DIEPINT12_WIDTH 32
USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_SET 0x80000000
CM_CKSM_FRCE_CLR 0xffff00ff
JICST_INTCD (1 << 0)
SMI_DSR1_RSETUP_BITS 29:24
USB_DOEPTSIZ11_WIDTH 32
HDMI_RAM_PACKET_5_0_MASK 0xffffffff
USB_GPVNDCTL_STS_BSY_MSB 26
DMA5_TXFR_LEN_YLENGTH_BITS 29:16
DMA1_DEST_AD_D_ADDR_SET 0xffffffff
USB_GI2CCTL_BSY_DNE_SET 0x80000000
DSI1_PHY_AFEC1 0x7e700074:RW
DMA1_CS_PRIORITY_CLR 0xfff0ffff
TB_BOOT_OPT_DONT_SET_VPU_CLK_BITS 10:10
DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
CMI_CAM1_HSSRC_SET 0x00000003
PWM_CTL_MODE3_BITS 17:17
SD_VIN_VIO_BITS 20:20
SCALER_DISPDITHER 0x7e400014:RW
A2W_PLLA_ANA_KAIP_KP_MSB 3
CMPLL1 0x7C:RW
DMA9_CS_ABORT_BITS 30:30
DMA15_NEXTCONBK_ADDR_SET 0xffffffe0
USB_DOEPINT11_MASK 0xffffffff
TXP_DST_PTR_WIDTH 32
DMA_CS(n) MACRO
AC_MAXCTABLE_OFFSET(t) MACRO
USB_GINTMSK_USB_RST_CLR 0xffffefff
ARM_C0_UNUSED05 0x00000020
PCM_GRAY_RXFIFOLEVEL_BITS 21:16
PM_GRAFX_CFG_MSB 22
TB_BOOT_STATUS_CPRMAN_PROGRAMMED_SET 0x00000001
A2W_PLLA_CTRL_NDIV_CLR 0xfffffc00
SYSAC_V3D_LIMITER_INCREMENT_RESET 0x0
DMA10_DEBUG_DMA_STATE_BITS 24:16
SD_DQLCRC1_RISE_CLR 0x0000ffff
DMA13_DEST_AD_D_ADDR_SET 0xffffffff
HDMI_RAM_PACKET_7_8_WIDTH 32
A2W_PLLA_ANA_SSCSR_WIDTH 17
CAM1_CAMIHSTA 0x7e801124:RW
MPHI_C1INDDB_TENDINT_SET 0x20000000
DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
AVE_IN_BUF1_ADDRESS_BUF1_ADDR_LSB 0
SD_PT1_T_INIT3_CLR 0xf00000ff
GP_FSEL4_FSEL48_LSB 24
DMA_ENABLE_EN14_CLR 0xffffbfff
CM_BURSTCTL_ENAB_BITS 4:4
GRSDOF 0x1A005800 + 0x24:RW
EMMC_BUS_CTRL_BUS_WIDTH_MSB 14
PWMSTA_GAPO1 4
DMA3_STRIDE_WIDTH 32
PWMSTA_GAPO3 6
PWMSTA_GAPO4 7
HDMI_TX_PHY_TX_PHY_CTL_1_RESET 0x0404a808
USB_DOEPCTL0_TXF_NUM_MSB 25
MS_SEMA_24_RESET 0000000000
DMA11_CS_ERROR_BITS 8:8
DMA1_TI_TDMODE_BITS 1:1
SH_CMD_WRITE_CMD_BITS 8:7
GP_FSEL2_FSEL20_BITS 2:0
SD_DQRCRC2_FALL_MSB 15
A2W_PLLC_CORE1_CHENB_CLR 0xfffffeff
DMA10_CS_RESET_LSB 31
HDMI_CTS_0_MASK 0x000fffff
MPHI_MOUTFS_UFLOW_SET 0x80000000
A2W_XOSC_CTRL_PLLBOK_BITS 19:19
HDMI_HORZA_MANUAL_HAP_MSB 12
CM_LOCK_LOCKD_MSB 3
MPHI_MINFS_RPTR_LSB 20
A2W_PLLB_ANA_SSCS_MASK 0x0001ffff
CM_INTEN_FLOSSB_BITS 15:15
MPHI_C0INDCF_EMPTY_SET 0x80000000
DMA5_TXFR_LEN_YLENGTH_CLR 0xc000ffff
L1_D_PRIORITY_WIDTH 28
L1_L1_SANDBOX_START6_MASK 0x3fffffff
HDMI_RAM_PACKET_9_5_RESET 0000000000
USB_GOTGCTL_DEV_HNP_EN_CLR 0xfffff7ff
SD_MR_ADDR_LSB 0
CAM1_CAMDAT0_WIDTH 32
CM_TCNTCTL_KILL_BITS 6:6
DMA4_TI_SRC_WIDTH_LSB 9
SD_DQRCRC11_FALL_LSB 0
HD_MAI_THR_PANICLOW_RESET 0x1
DMA2_DEBUG_VERSION_LSB 25
DMA9_TI_DEST_DREQ_BITS 6:6
SLIM_DCC0_PA0 0x7e210200:RW
DMA13_SOURCE_AD_S_ADDR_SET 0xffffffff
A2W_PLLH_FRACR_RESET 0000000000
USB_GINTMSK_EOPF_MSB 15
SMI_DSR2_RSTROBE_LSB 0
GP_AFEN2_AFENn64_CLR 0xffffffc0
PM_PADS0_DRIVE_MSB 2
L1_IC0_CONTROL_DISABLE_VLINE_LSB 5
SD_SECEND1_ADDR_LS_BITS 12:0
DMA_CS_INT (1<<2)
EMMC_BOOT_TIMEOUT_TIMEOUT_SET 0xffffffff
CM_V3DCTL_BUSYD_LSB 8
AVE_IN_CTRL_BUF0_IRQ_EN_BITS 1:1
MS_SEMA_16_MASK_MSB 0
DMA4_DEBUG_VERSION_BITS 27:25
USB_HPRT_SUSP_RESET 0x0
MS_SEMA_22_MASK_LSB 0
HDMI_FIFO_CTL_USE_PLL_LOCK_CLR 0xffffffef
OTP_BITSEL_REG 0x7e20f014:RW
SLIM_DCC7_CON_RESET 0000000000
SD_MRT_T_MRW_LSB 0
SD_DQRCRC3_RISE_CLR 0x0000ffff
DMA1_CS_END_LSB 1
SMI_CS_SETERR_BITS 13:13
HDMI_SCHEDULER_CONTROL_MODE_REQ_CLR 0xfffffffe
SLIM_CRX_DMA (11*(1<<16))
MPHI_HSINDCF_HANDLE_LSB 20
CM_PCMCTL_SRC_SET 0x0000000f
A2W_PLLA_CCP2_BYPEN_MSB 9
DMA7_TXFR_LEN_XLENGTH_SET 0x0000ffff
DMA5_TI_WAITS_BITS 25:21
EMMC_IRPT_EN_WRITE_RDY_CLR 0xffffffef
PM_PROC_MASK 0x007f107f
ASB_H264_M_CTRL_RCOUNT_SET 0x00003ff0
HDMI_HDCP_KEY_1_MASK 0xffffff3f
SD_DQRCRC13_RISE_RESET 0x0
PM_CAM1_CTRLEN_BITS 0:0
DMA14_DEBUG_READ_ERROR_CLR 0xfffffffb
EMMC_IRPT_MASK_CARD_OUT_MSB 7
GP_FSEL1_FSEL14_MSB 14
DMA11_DEBUG_OUTSTANDING_WRITES_BITS 7:4
DMA8_CS_DREQ_MSB 3
PCM_CS_A_TXE_SET 0x00200000
EMMC_HWCAP0_BUS64_BITS 28:28
CM_TECCTL_SRC_CLR 0xfffffffc
USB_GINTMSK_GOUT_NAK_EFF_LSB 7
GP_FSEL3_FSEL35_CLR 0xfffc7fff
A2W_SMPS_L_SPAR_MASK 0x000003ff
DMA1_TI_SRC_IGNORE_BITS 11:11
USB_GGPIO_GPI_BITS 15:0
MPHI_C1INDCF_MTERM_MSB 28
DMA15_DEST_AD 0x7ee05010:RO
USB_DOEPCTL0_MPS_LSB 0
USB_HCCHAR0_EP_DIR_RESET 0x0
AVE_IN_STATUS_HSYNC_DET_CLR 0xffffffdf
SMICS_DONE 1
DMA6_TI_DEST_DREQ_BITS 6:6
DMA2_TI_WAITS_MSB 25
DMA11_DEBUG_DMA_STATE_LSB 16
SCALER_DISPSLAVE2_MASK 0xffffffff
USB_GHWCFG4_EN_VBUSVALID_FILTER_CLR 0xffdfffff
CM_INTEN_OCDONE_BITS 21:21
USB_DIEPTSIZ0_SUP_CNT_LSB 29
HD_MAI_CTL_ERRORF_CLR 0xfffffffd
V3D_INTDIS_MASK 0xffffffff
I2C_SPI_SLV_TDR_DATA_BITS 7:0
DMA13_TI_SRC_IGNORE_BITS 11:11
DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
DMA6_TI_WIDTH 27
VPU0_THREAD_CTRL_BASE_ADDRESS 0x18011000
EMMC_IRPT_EN_ADMA_ERR_CLR 0xfdffffff
CM_VPUCTL_BUSYD_SET 0x00000100
A2W_SMPS_CTLB1_MASK 0x00ffffff
EMMC_IRPT_MASK_CTO_ERR_CLR 0xfffeffff
PM_RSTC_DRCFG_LSB 0
PCM_MODE_A_CLKM_LSB 23
CM_PLLA_HOLDCCP2_BITS 3:3
GP_LEN2_LENn64_BITS 5:0
USB_HCINT0_STALL_RESET 0x0
CCP2TX_TTC_LSC_CLR 0xffffff0f
SPI_FIFO_MASK 0x000000ff
ASB_H264_M_CTRL_CLR_REQ_MSB 0
DMA13_DEST_AD_MASK 0xffffffff
HD_VID_CTL_BLANKPIX_MSB 18
OTP_INIT_STATUS_REG 0x7e20f024:RW
DMA14_NEXTCONBK_ADDR_MSB 31
CCP2TX_TTC_LCN_SET 0x0000000f
USB_DAINT_OUT_EP_INT_LSB 16
AVE_OUT_Y_COEFF_GREEN_COEFF_SET 0x000ffc00
SMI_CS_RXF_CLR 0x7fffffff
SPI_CS_TXD_MSB 18
AVE_IN_CTRL_HSYNC_IRQ_EN_BITS 5:5
PM_AVS_EVENT_ALERT_H264_I_BITS 2:2
CM_GP0CTL_KILL_BITS 5:5
AVE_OUT_OFFSET_GREEN_OFFSET_MSB 15
DMA10_TI_BURST_LENGTH_MSB 15
SYSAC_H264_PRIORITY_PRIORITY_MSB 3
USB_GHWCFG3_DFIFO_DEPTH_MSB 31
A2W_PLLH_CTRL_NDIV_LSB 0
USB_DOEPINT9_MASK 0xffffffff
AVE_IN_STATUS_LINE_NUM_HIT_MSB 4
SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_CLR 0xffff00ff
ASB_H264_S_CTRL_EMPTY_CLR 0xfffffffb
CM_CAM1CTL_BUSYD_BITS 8:8
GP_FSEL2_FSEL24_SET 0x00007000
TB_HDMI_WIDTH 32
HDMI_RAM_PACKET_2_8_RESET 0000000000
DMA8_DEBUG_READ_ERROR_BITS 2:2
PM_CAM0_LDOCTRL_LSB 3
SD_DQLCRC10_RISE_MSB 31
MPHI_CTRL_SOFT_RST_DNE_RESET 0x0
SD_DQLCRC7_FALL_MSB 15
CM_VPUCTL_SRC_LSB 0
CM_CAM0CTL_BUSYD_MSB 8
SH_HBLC_BLOCKCOUNT_LSB 0
TB_JTB_CONFIG_TDO_RISE_MSB 10
EMMC_INTERRUPT_ADMA_ERR_BITS 25:25
CM_TDCLKEN_PLLDBYP_LSB 3
SD_SA_CLKSTOP_RESET 0x1
HDMI_RAM_PACKET_2_0 0x7e902448:RW
PM_DSI1_LDOHPEN_CLR 0xfffffffb
DMA7_TI_DEST_INC_MSB 4
HDMI_CP_STATUS_RESET 0x00000100
GP_CLR1_CLRn32_BITS 31:0
DMA1_CS_PAUSED_CLR 0xffffffef
TB_BOOT_SECURE_MODE_JTAG_SECURE_LSB 0
MPHI_TXAXICFG_INTHRESH_MSB 16
SYSAC_DMA_ARBITER_CONTROL_PER_WIDTH 16
A2W_PLLC_ANA_STAT 0x7e102430:RW
CCP2TX_TDL_LEN_LSB 0
HDCP_KEY_KY0_RESET 0000000000
DMA1_TXFR_LEN_YLENGTH_MSB 29
SD_RWC_RXOVR_RESET 0x0
PM_PXBG_CTRL_LSB 0
I2C_SPI_SLV_IMSC_RXIM_LSB 0
HD_VID_CTL_UFEN_SET 0x40000000
DMA6_TI_DEST_DREQ_MSB 6
CM_ARMCTL_WIDTH 13
GP_REN1_RENn32_SET 0xffffffff
UART_LSR 0x7e201014:RW
USB_GUSBCFG_SRP_CAP_LSB 8
HDMI_READ_POINTERS_DOMAIN_HALF_FULL_CLR 0xbfffffff
SCALER_2_DMA (23*(1<<16))
I2C_SPI_SLV_DR_RXFE_BITS 17:17
USB_DIEPINT0_SETUP_LSB 3
A2W_HDMI_CTL1R_RESET 0x00011c00
CM_DFTDIV_WIDTH 17
DPHY_CSR_BASE 0x7ee07000
USB_GINTMSK_CON_ID_STS_CHNG_SET 0x10000000
SYSAC_V3D_LIMITER_SPARE_SET 0x0000000e
CM_CCP2CTL_BUSYD_MSB 8
EMMC_CONTROL2_EN_AINT_BITS 30:30
JP_OADDR 0x7e005038:RW
CM_CCP2CTL_BUSY_LSB 7
UART_MSR_DCD_BITS 7:7
AVE_OUT_STATUS_HSYNC_BITS 6:6
VEC_CONFIG4_MASK 0xffffffff
DMA13_CS_ABORT_MSB 30
DMA1_TXFR_LEN_XLENGTH_LSB 0
USB_DTKNQR3_WIDTH 32
A2W_XOSC_CTRL_PLLDEN_BITS 5:5
DPHY_CSR_BYTE2_SLAVE_DLL_OFFSET 0x7ee07024:RW
DMA12_DEBUG_LITE_MSB 28
PM_GRAFX_ISFUNC_MSB 5
SMI_CS_CLEAR_RESET 0x0
EMMC_FORCE_IRPT_SDOFF_ERR_LSB 23
SD_SF_POWSAV_T_BITS 18:9
HDMI_SCHEDULER_CONTROL_VSYNC_PHYST_EN_BITS 17:17
SMI_DSW3_RESET 0x0101000c
USB_DCTL_PWRON_PRG_DONE_SET 0x00000800
DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
GP_FSEL1_FSEL10_LSB 0
A2W_SMPS_CTLC2R_RESET 0000000000
CAM1_CAMIBSA0_RESET 0000000000
TS_TSENSCTL_CLR_INT_LSB 7
MPHI_C1INDS_WORDS_BITS 20:0
TH1T3UD 0x1A008000 + 0x2C:RW
EMMC_CONTROL1_CLK_FREQ_MS2_LSB 6
CM_H264CTL_BUSYD_MSB 8
DMA10_DEBUG_READ_ERROR_MSB 2
SPI_CS_RXD_BITS 17:17
SLIM_DCC9_PROT_MASK 0xc001ffff
A2W_PLLA_DSI0_CHENB_CLR 0xfffffeff
PCM_CS_A_STBY_MSB 25
DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
DMA13_SOURCE_AD_MASK 0xffffffff
DMA5_TI_DEST_INC_CLR 0xffffffef
CCP2TX_TTC_LSC_MSB 7
L1_IC1_CONTROL_START_FLUSH_LSB 1
TB_JTB_CONFIG_BUSY_CLR 0x7fffffff
USB_GRSTCTL_INT_TKN_Q_FLSH_LSB 3
GROPCTR_FOVCULLEDPRIMS 0x01
CM_GNRICDIV_WIDTH 24
AVE_IN_OUTSTANDING_BUFF0 0x7e910034:RW
AVE_IN_OUTSTANDING_BUFF1 0x7e910038:RW
HDMI_RAM_PACKET_4_0 0x7e902490:RW
DMA0_TI_TDMODE_SET 0x00000002
DMA4_CS_ERROR_LSB 8
I2C1_FIFO_WIDTH 8
CM_TECCTL_FRAC_LSB 9
MS_SEMA_22_WIDTH 1
SD_PHYC_BIST_MODE_MSB 8
DMA11_TI_DEST_DREQ_BITS 6:6
EMMC_HWCAP1_DRV18_TYPEC_MSB 5
V3D_CT1CS_WIDTH 32
PWM_DMAC_DREQ_BITS 7:0
EMMC_IRPT_EN_ATA_ERR_BITS 29:29
DMA2_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
L1_L1_SANDBOX_END5_MASK 0x3fffffe0
DSI1_HS_DLT4_RESET 0000000000
CM_CKSM_OSC_LSB 18
PCM_TXC_A_CH2EN_MSB 14
USB_DOEPINT0_AHB_ERR_LSB 2
HDMI_RAM_PACKET_9_3_WIDTH 32
A2W_PLLC_ANA_VCO_RANGE_CLR 0xfffffffe
HDMI_RAM_PACKET_3_7_MASK 0xffffffff
PM_RSTS_HADDRH_SET 0x00000004
DMA1_TI_SRC_DREQ_CLR 0xfffffbff
USB_DIEPTSIZ3_WIDTH 32
CM_GP2DIV_DIV_SET 0x00ffffff
SYSAC_ISP_PRIORITY_PRIORITY_LSB 0
A2W_XOSC_CPR_CPR1_LSB 4
HDMI_PACKET_FIFO_STATUS_MASK 0x03073f1f
EMMC_SLOTISR_VER_WIDTH 32
EMMC_INTERRUPT_CCRC_ERR_SET 0x00020000
DMA4_STRIDE_D_STRIDE_MSB 31
MS_SEMA_29_MASK_LSB 0
DMA4_SOURCE_AD_WIDTH 32
SH_HSTS_BLOCK_IRPT_LSB 9
SD_DQRCRC10_RISE_RESET 0x0
A2W_PLLD_ANA_SSCL_WIDTH 22
CM_ARMCTL_FRAC_CLR 0xfffffdff
DMA12_CS_DISDEBUG_SET 0x20000000
JDCCTRL_DISDC (1 << 20)
TB_JTB_CONFIG_D_HOLD_MSB 13
USB_DOEPCTL0_SNAK_CLR 0xf7ffffff
CM_GNRICCTL_ENAB_SET 0x00000010
DMA2_TI_DEST_WIDTH_CLR 0xffffffdf
SLIM_DCC7_PA1_RESET 0000000000
TXP_CTRL_LINEAR_UTILE_LSB 7
HDMI_RAM_PACKET_5_5_WIDTH 32
EMMC_FORCE_IRPT_TUNE_ERR_SET 0x04000000
A2W_SMPS_A_VOLTS_VOLTS_MSB 4
SMI_DSR2_FSETUP_BITS 22:22
DMA9_TI_DEST_IGNORE_LSB 7
VPU_ARB_CTRL_UC_LIMIT_SET 0x00000003
SCALER_DISPSLAVE0_WIDTH 32
CM_EVENT_FGAINB_CLR 0xfffff7ff
CM_OSCCOUNT_MASK 0x00ffffff
USB_DOEPINT0_STS_PHSE_RCVD_RESET 0x0
USB_HCSPLT0_XACT_POS_SET 0x0000c000
MS_ICCLR_0_ICCLR_0_LSB 0
SH_HSTS_CRC7_ERROR_LSB 4
DMA1_TI_PERMAP_CLR 0xffe0ffff
EMMC_CONTROL0_WAKE_ONINT_EN_BITS 24:24
HD_VID_CTL_RESET 0x00040000
DMA5_DEBUG_LITE_MSB 28
VIDEOCORE_NUM_CORES 2
L1_IC1_CONTROL_RAS_DISABLE_SET 0x00000010
USB_DFIFO11 0x7e98c000:RW
USB_DFIFO12 0x7e98d000:RW
HDMI_RAM_PACKET_1_7_WIDTH 32
USB_DFIFO14 0x7e98f000:RW
USB_DFIFO15 0x7e990000:RW
APERF0_BW0_CTRL_WIDTH 32
AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_SET 0x80000000
EMMC_CONTROL0_HCTL_DWIDTH_MSB 1
SYSAC_L2_ARBITER_CONTROL_ALGORITHM_CLR 0xffffff3f
TB_BOOT_OPT_EIGHT_BANK_SET 0x00000002
DMA7_NEXTCONBK_ADDR_LSB 5
SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_BITS 15:8
APERF1_BW0_CTRL_RESET_LSB 31
EMMC_STATUS_CMD_LEVEL_MSB 24
DSI1_RXPKT_FIFO 0x7e700024:RW
CM_TCNTCTL_SRC1_BITS 13:12
EMMC_INTERRUPT_DEND_ERR_LSB 22
AJB_INV_CLK 0x000080
A2W_PLLB_ANA1R_WIDTH 24
HDMI_RAM_PACKET_7_2_RESET 0000000000
DMA2_CS_PRIORITY_CLR 0xfff0ffff
AVE_IN_CTRL_BUF_SER_IRQ_EN_BITS 3:3
A2W_XOSC_CTRL_PLLCOK_LSB 12
DMA6_SOURCE_AD_MASK 0xffffffff
JQCTRL 0x7e005000 + 0x48:RW
DMA0_TI_DEST_INC_BITS 4:4
A2W_PLLA_ANA_MULTI_RESET 0000000000
DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
A2W_PLLB_ANA_KAIP_KP_MSB 3
MS_SEMA_11_MASK_CLR 0xfffffffe
USB_GRSTCTL_C_SFT_RST_SET 0x00000001
IC0_C 0x7e002000:RW
USB_DFIFO10 0x7e98b000:RW
DMA12_CONBLK_AD_MASK 0xffffffe0
CM_ARMCTL_AXIHALF_MSB 12
IC1_C_RESET 0000000000
DMA_TI_S_IGNORE (1<<11)
USB_DIEPINT0_BNA_RESET 0x0
USB_DFIFO13 0x7e98e000:RW
A2W_PLLA_PER_DIV_MSB 7
EMMC_CMDTM_CMD_INDEX_BITS 29:24
PM_CAM1_CTRLEN_LSB 0
DMA15_STRIDE_S_STRIDE_BITS 15:0
A2W_PLLB_ANA_SSCSR_WIDTH 17
CM_H264DIV_DIV_BITS 15:4
CM_TD1DIV_DIV_LSB 0
APERF1_BW2_CTRL_ID_EN_CLR 0xdfffffff
DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
USB_GHWCFG3_TRANS_COUNT_WIDTH_LSB 0
ASB_ISP_M_CTRL_CLR_ACK_MSB 1
DMA_ENABLE_EN10_LSB 10
A2W_PLLD_DSI1_DIV_SET 0x000000ff
SLIM_DCC1_STAT_MASK 0xc0ff00c7
SD_SA 0x7ee00004:RW
SD_SB 0x7ee00008:RW
SD_SC 0x7ee0000c:RW
SD_SD 0x7ee00094:RW
SD_SE 0x7ee00098:RW
A2W_PLLA_ANA_SSCL 0x7e102210:RW
USB_DFIFO12_WIDTH 32
V3D_VPMBASE 0x7ec00000 +0x0504:RW
CCP2TX_TIC_TQIT_SET 0x000000f0
A2W_PLLA_ANA_SSCS 0x7e102110:RW
DSI0_HS_DLT4_RESET 0000000000
A2W_PLLH_RCAL_CHENB_BITS 8:8
I2C_SPI_SLV_IFLS_TXIFPSEL_MSB 8
MPHI_C0INDS_HANDLE_SET 0x1fe00000
USB_DOEPDMAB3_WIDTH 32
EMMC_FORCE_IRPT_DMA_LSB 3
GRPABS 0x1A005600 + 0x60:RW
CCP2TX_TPC_TNP_CLR 0xfffffff0
A2W_PLLH_AUXR_RESET 0x00000100
EMMC_CONTROL1_CLK_STABLE_SET 0x00000002
USB_HPRT_RES_BITS 6:6
CM_HSMCTL_KILL_SET 0x00000020
EMMC_CONTROL0_PWCTL_SDVOLTS_LSB 9
MPHI_HSINDDA_START_LSB 0
USB_HPRT_OVR_CURR_ACT_RESET 0x0
USB_HPRT_PWR_MSB 12
HDMI_CTS_PERIOD_0_MASK 0xff0fffff
DMA1_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
DMA9_CS_INT_BITS 2:2
SD_SECEND0_MASK 0xffffffff
L1_L1_SANDBOX_END4_MASK 0x3fffffe0
PIXELVALVE0_INTSTAT_MASK 0x000003ff
EMMC_IRPT_EN_DATA_DONE_LSB 1
CM_PLLC_WIDTH 10
DMA11_CS_ACTIVE_CLR 0xfffffffe
CCP2TX_TAC_CLAC_CLR 0xff00ffff
SMI_CS_INTD_SET 0x00000200
CCP2TX_TDL_WIDTH 30
AVE_IN_CTRL_BYTE_ORDER_LSB 11
MS_MBOX_3_MBOX_LSB 0
VEC_WSE_WSS_DATA_WIDTH 32
GP_PUDCLK1_PUDCLKn32_SET 0xffffffff
SMI_DSR1_RHOLD_MSB 21
CM_EVENT_FGAINA_CLR 0xfffffbff
JICST_INTSD (1 << 1)
CM_GP2CTL_BUSYD_LSB 8
CM_SYSCTL_RESET 0x00000040
EMMC_INTERRUPT_ACMD_ERR_MSB 24
A2W_PLLB_FRAC_WIDTH 20
SD_IDL_MASK 0x0fffffff
RNG_DATA_WIDTH 32
I2C0_FIFO_WIDTH 8
DMA12_CS_END_BITS 1:1
MPHI_INTCTRL_HSDCOFLW_MSB 20
SH_VDD_POWER_ON_BITS 0:0
PWM_CTL_POLA2_BITS 12:12
DMA13_CS_DREQ_SET 0x00000008
A2W_PLLB_ANA_STATR 0x7e102cf0:RW
DMA6_DEBUG_FIFO_ERROR_SET 0x00000002
SD_SD_T_XP_MSB 18
V3D_IDENT2_MASK 0xffffffff
DMA5_CONBLK_AD_MASK 0xffffffe0
USB_HFIR_IN_LSB 0
AUX_MU_CNTL_FLOW1 0x20
EMMC_HWCAP0_V3_3_MSB 24
HDMI_HDCP_CTL 0x7e902044:RW
USB_GINTMSK_FET_SUSP_MSB 22
PWMCTL_SBIT1 3
USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_BITS 15:0
PWMCTL_SBIT3 19
PWMCTL_SBIT4 27
A2W_XOSC_CTRL_PLLBOK_CLR 0xfff7ffff
CM_PLLA_HOLDDSI0_MSB 1
EMMC_CMDTM_WIDTH 30
SLIM_DCC6_CON 0x7e2102c8:RW
SMI_DSR0_RHOLD_LSB 16
DMA1_CS_DREQ_STOPS_DMA_SET 0x00000020
DMA13_CS_RESET_CLR 0x7fffffff
I2C_SPI_SLV_CR_HOSTCTRLEN_BITS 12:12
DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
EMMC_HWCAP0_ADMA2_LSB 19
SD_DQLCRC6_FALL_BITS 15:0
I2C_SPI_SLV_TDR_DATA_MSB 7
DSI0_CMD_PKTC_RESET 0000000000
USB_HPRT_OVR_CURR_CHNG_MSB 5
DMA9_DEBUG_READ_ERROR_LSB 2
DMA9_DEBUG_DMA_STATE_SET 0x01ff0000
ALIAS_ANY_NONALLOCATING_READ(x) MACRO
A2W_PLLB_ARM_CHENB_BITS 8:8
APERF1_BW0_WTWAIT 0x7ee08054:RO
ASB_V3D_S_CTRL_CLR_REQ_SET 0x00000001
MPHI_OUTDS 0x7e006030:RW
SD_DQRCRC9_FALL_RESET 0x0
PCM_INTEN_A_TXERR_LSB 2
HDMI_HORZB_MASK 0x3fffffff
SMI_DSW0_WWIDTH_CLR 0x3fffffff
A2W_PLLH_RCAL_CHENB_SET 0x00000100
L1_IC0_PRIORITY_IC0_APRIORITY0_LSB 0
GP_FSEL2_FSEL29_MSB 29
AUX_MU_CNTL_FLOW3 0x00
DMA4_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
DMA7_DEST_AD_MASK 0xffffffff
A2W_PLLA_ANA_STAT_DATA_SET 0x00000fff
DMA15_TI_SRC_IGNORE_CLR 0xfffff7ff
CM_TD0CTL 0x7e1010d0:RW
USB_GUSBCFG_CORRUPT_TX_RESET 0x0
USB_HCTSIZ0_PKT_CNT_RESET 0x0
A2W_HDMI_CTL_RCAL_RSTB_LSB 16
MPHI_C1INDFS_DFIFOLVL_CLR 0xffff0000
A2W_PLLD_ANA_STAT_WIDTH 12
SCALER_DISPECTRL_CR_BUSY_SET 0xfffff800
I2C_BASE_0 0x7e205000
A2W_PLLC_CTRL_PDIV_CLR 0xffff8fff
L1_IC0_PRIORITY_RESET 0x000034af
USB_GOTGINT_A_DEV_TOUT_CHG_SET 0x00040000
GROPCTR_FBC_CZ_UM_STALLS 0x2F
APERF0_BW2_CTRL_BUS_BITS 4:0
PM_DSI1_LDOCTRL_MSB 20
CCP2TX_TS_TQL_MSB 12
PIXELVALVE0_HORZA_MASK 0xffffffff
EMMC_IRPT_EN_DTO_ERR_BITS 20:20
DMA8_TI_DEST_DREQ_CLR 0xffffffbf
DMA8_TI_MASK 0x03fffff9
AVE_IN_STATUS_CSYNC_FIELD_MSB 13
DMA14_TXFR_LEN_MASK 0x0000ffff
USB_HCINT0_FRM_OVRUN_CLR 0xfffffdff
EMMC_HWCAP0_XMEDBUS_LSB 18
SCALER_DISPSTAT_DSP2_IRQ_BITS 31:3
CM_PLLH_DIGRST_BITS 9:9
CM_TDCLKEN_PLLBDIV2_SET 0x00000020
A2W_XOSC_CTRLR_RESET 0000000000
DMA15_TI_TDMODE_LSB 1
DMA0_SOURCE_AD_S_ADDR_SET 0xffffffff
TXP_DIM_MASK 0x0fff0fff
PWM_STA_STA3_MSB 11
EMMC_CONTROL0_SPI_MODE_BITS 20:20
USB_GAXIDEV 0x7e980054:RW
HDMI_VERTB1_MANUAL_VSPO1_CLR 0xffc001ff
A2W_PLLC_CTRLR_WIDTH 18
SD_RAC_MASK 0x0fffffff
TB_TASK_STATUS_MASK 0xffffffff
HD_CSC_12_11_WIDTH 32
DMA0_CS_PRIORITY_BITS 19:16
CM_PLLC_LOADCORE0_CLR 0xfffffffe
DMA13_DEBUG_WIDTH 29
DMA8_TI_DEST_INC_MSB 4
DMA14_TI_INTEN_MSB 0
CM_PLLD_LOADDSI0_CLR 0xfffffffe
DMA13_CS_END_CLR 0xfffffffd
CM_EVENT_BADPASS_LSB 18
DMA3_TI_SRC_INC_MSB 8
I2C_SPI_SLV_CR_CPOL_MSB 4
CM_INTEN_LOSSB_SET 0x00000040
EMMC_IRPT_EN_CTO_ERR_SET 0x00010000
SD_SB_WIDTH 32
USB_HCTSIZ0_PID_SET 0x60000000
GP_FSEL3_FSEL39_SET 0x38000000
EMMC_HWCAP0_HS_LSB 21
FPGA_STATUS0_SPARE_IN_LSB 19
DMA13_CS_RESET_BITS 31:31
CM_H264CTL_SRC_CLR 0xfffffff0
DMA_INT_STATUS_INT12_MSB 12
DMA8_SOURCE_AD 0x7e00780c:RO
PIXELVALVE_2_BASE_ADDRESS 0x7e807000
SD_SE_T_FAW_BITS 17:12
A2W_PLLH_ANA2R_WIDTH 24
USB_DIEPINT9_MASK 0xffffffff
PM_HDMI_LDOCTRL_LSB 2
USB_GPVNDCTL_WIDTH 32
GP_PUD_PUD_CLR 0xfffffffc
EMMC_HWCAP0_RESUME_CLR 0xff7fffff
PM_PADS2_SLEW_CLR 0xffffffef
APERF0_BW2_RPEND_RESET 0000000000
DMA7_CS_ABORT_MSB 30
DMA1_DEBUG_READ_ERROR_CLR 0xfffffffb
FPGA_DCM_WR_DATA_ADDRESS_CLR 0xff00ffff
A2W_PLLH_ANA_KAIP_KP_LSB 0
DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
HDMI_READ_POINTERS_DOMAIN_RESYNC_RD_SET 0x07000000
SD_RWC_WRTVAL_RESET 0x0
FPGA_STATUS0_SD_WP_CLR 0xffffffef
A2W_PLLC_CORE2_CHENB_SET 0x00000100
DMA8_CS_PAUSED_LSB 4
USB_DOEPDMA8_MASK 0xffffffff
SLIM_DCC4_STAT 0x7e21028c:RW
CMI_CAM0_RX1SRC_MSB 5
USB_GHWCFG3_RM_OPT_FEATURES_MSB 10
EMMC_IRPT_EN_RETUNE_CLR 0xffffefff
EMMC_CONTROL2_UHSMODE_CLR 0xfff8ffff
CCP2TX_TS_TFF_BITS 5:5
PM_AVS_RSTDR_V3D_G_SET 0x00000008
DMA14_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
HDMI_RAM_PACKET_7_0_WIDTH 32
CM_VECCTL_BUSY_MSB 7
DMA_INT_STATUS_INT3_MSB 3
APERF0_BW2_ATRANS_MASK 0xffffffff
TXP_CTRL_POWERDOWN_CLR 0xffdfffff
MPHI_HSINDFS_DFIFOLVL_MSB 0
MS_VPU_STAT_VPU_STAT_LSB 0
MPHI_C1INDDB_MTERM_RESET 0x0
USB_HCINT0_ACK_RESET 0x0
CCP2TX_TC_CLKM_BITS 2:2
APERF1_BW1_CTRL_BUS_BITS 4:0
UART_MSR_TERI_SET 0x00000004
DSI1_TXPKT2_C_MASK 0xffffffff
PM_AVS_INTEN_ALERT_H264_I_SET 0x00000004
USB_DOEPTSIZ0_PKT_CNT_LSB 19
SMI_DCS_EANBLE_MSB 0
APERF0_BW1_ATWAIT_WIDTH 32
HDMI_RAM_PACKET_3_2_WIDTH 32
SMI_DSW3_WPACEALL_CLR 0xffff7fff
MPHI_C1INDCF_MASK 0xffffffff
L1_IC1_CONTROL_DISABLE_VLINE_MSB 6
UART_LCR_DLAB_CLR 0xffffff7f
PCM_GRAY_RXFIFOLEVEL_MSB 21
DSI0_PHYC_forcehsstop_sync_BITS 2:2
SD_DQLCRC1_FALL_CLR 0xffff0000
EMMC_INTERRUPT_BOOTACK_BITS 13:13
USB_DOEPCTL0_NEXT_EP_RESET 0x0
DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
GP_FSEL2_FSEL25_LSB 15
DMA7_TI_SRC_WIDTH_SET 0x00000200
SD_CS_DLLCAL_BITS 11:10
CCP2TX_TAC_PTATADJ_BITS 27:24
VEC_WSE_RESET 0x7e8060c0:RW
CCP2TX_TC_TEN_CLR 0xfffffffe
I2C_SPI_SLV_SLV_WIDTH 7
CM_DPICTL_ENAB_CLR 0xffffffef
USB_HCFG_MASK 0x00000007
CM_LOCK_WIDTH 13
DMA13_CS_DREQ_BITS 3:3
SMI_DSW2_WPACE_CLR 0xffff80ff
USB_GPVNDCTL_REG_ADDR_BITS 21:16
APERF1_BW2_CTRL_WIDTH 32
CM_TCNTCTL_KILL_SET 0x00000040
EMMC_BLKSIZECNT_BLKCNT_LSB 16
DMA11_TI_DEST_WIDTH_BITS 5:5
MPHI_C1INDDB_MENDINT_LSB 30
SD_CS_RDH_IDLE_LSB 16
DMA2_TI_SRC_DREQ_CLR 0xfffffbff
MS_SEMA_18_WIDTH 1
A2W_HDMI_CTL_MULTI_WIDTH 0
A2W_PLLH_CTRL_PRSTN_LSB 17
USB_HPRT_RST_SET 0x00000100
AVE_OUT_STATUS_VSYNC_BITS 9:9
PM_PROC_ISPOW_CLR 0xfffffffb
DMA5_SOURCE_AD_WIDTH 32
DMA3_STRIDE_S_STRIDE_CLR 0xffff0000
HDCP_KEY_ADR_WIDTH 8
SCALER_DISPLACT2_WIDTH 32
APERF0_BW0_RTRANS_RESET 0000000000
USB_GUSBCFG_IND_COMP_MSB 23
HDMI_VERTA0_MANUAL_VFP0_LSB 13
PWM_CTL_USEF2_SET 0x00002000
DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
HDMI_RAM_PACKET_1_1_RESET 0000000000
EMMC_RESP1_RESET 0000000000
CGMSAE_RESET 0x7e806040:RW
VEC_CLMP0_END_WIDTH 32
A2W_PLLH_RCALR_RESET 0x00000100
MS_SEMA_5_MASK_SET 0x00000001
PM_IMAGE_CFG_SET 0x007f0000
SLIM_DCC5_STAT_MASK 0xc0ff00c7
DSI1_TA_TO_CNT_MASK 0xffffffff
DMA15_TI_BURST_LENGTH_BITS 15:12
DMA10_CS_DREQ_LSB 3
USB_GUID_WIDTH 32
MPHI_INTSTAT_OMFUFLW_SET 0x10000000
MPHI_C0INDFS_WIDTH 32
I2CS_RXF (1 << 7)
DMA15_TI_SRC_IGNORE_LSB 11
HDMI_VERTA1_MANUAL_VAL1_SET 0x00001fff
HDMI_TST_AN1_WIDTH 32
SMI_CS_START_CLR 0xfffffff7
CPG_IntStatus_MASK 0xffffffff
DMA0_TI_SRC_WIDTH_BITS 9:9
SD_DQRCRC6_FALL_RESET 0x0
APERF1_BW0_RPEND_MASK 0x000000ff
A2W_PLLH_ANA_SCTL_RESET_LSB 4
A2W_SMPS_CTLC2_RESET 0000000000
SPI_CS_DMAEN_CLR 0xfffffeff
MPHI_CTRL_EIGHTBIT_LSB 12
SD_PHYC_IOB_TMODE_RESET 0x0
SD_DQRCRC3_FALL_CLR 0xffff0000
APERF1_BW2_WMAX_WIDTH 28
EMMC_HWCAP0_ADMA2_MSB 19
PCM_CS_A_RXSYNC_CLR 0xffffbfff
A2W_PLLA_ANA_KAIP_KI_SET 0x00000070
USB_GUSBCFG_PHY_IF_BITS 3:3
A2W_PLLH_ANA_STAT_DATA_MSB 11
DMA4_TI_SRC_IGNORE_SET 0x00000800
A2W_PLLH_ANA_KAIP_KI_CLR 0xffffff8f
DMA3_CS_PRIORITY_CLR 0xfff0ffff
SD_DQLCRC2_WIDTH 32
DMA10_CS_PRIORITY_BITS 19:16
GP_AREN0_ARENn0_CLR 0x00000000
USB_GUSBCFG_PHY_LPWR_CLK_SEL_RESET 0x0
I2C2_S_WIDTH 32
GRTBCOL5 0x1A0052A0 + 0x0C:RW
A2W_PLLC_ANA_KAIP_KP_MSB 3
USB_HPRT_ENA_BITS 2:2
CM_DFTCTL_ENAB_MSB 4
SD_SECEND0_ADDR_LS_MSB 12
SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_SET 0x000000c0
VEC_CGMSAE_BOT_DATA_MASK 0xffffffff
SD_RWC_RXVAL_SET 0x0000001f
CM_GP2CTL_SRC_LSB 0
GRSDZS 0x1A005800 + 0x40:RW
PCM_MODE_A_PDMN_BITS 27:27
SMI_DSW3_WSETUP_BITS 29:24
PM_PADS4_DRIVE_BITS 2:0
DMA12_DEBUG_RESET 0000000000
CAM1_CAMIPIPE 0x7e80110c:RW
SLIM_EA0_MASK 0xffff00ff
EMMC_IRPT_MASK_BOOTACK_CLR 0xffffdfff
A2W_PLLC_ANA_SSCSR_WIDTH 17
DMA7_CS_PAUSED_MSB 4
A2W_PLLC_CORE2_CHENB_MSB 8
AVE_OUT_CR_COEFF 0x7e240014:RW
USB_GOTGINT_SES_END_DET_BITS 2:2
SYSAC_DMA_ARBITER_CONTROL_LITE_WIDTH 16
SH_HCFG_DATA_IRPT_EN_SET 0x00000010
USB_DOEPCTL0_USB_ACT_EP_SET 0x00008000
USB_HCINT4_MASK 0xffffffff
DMA2_DEST_AD_D_ADDR_SET 0xffffffff
FPGA_DCM_CTRL_WIDTH 32
USB_GRXSTSP_HST_CH_NUM_BITS 3:0
DMA10_CS_END_CLR 0xfffffffd
CM_DFTCTL_ENAB_LSB 4
USB_DIEPTXF14_WIDTH 32
CM_SDCCTL_BUSY_LSB 7
HDMI_DETECTED_VERTA0_MANUAL_VFP0_SET 0x000fe000
SD_SECSRT0_EN_RESET 0x0
ARM_C0_SIZ256M 0x00000001
USB_DCTL_TST_CTL_BITS 6:4
CCP2TX_TS_TFE_SET 0x00000010
DMA14_SOURCE_AD_S_ADDR_MSB 31
DMA1_DEBUG_OUTSTANDING_WRITES_LSB 4
SD_SC_T_RFC_LSB 24
A2W_PLLA_DIG0_MASK 0x00ffffff
EMMC_IRPT_EN_INT_C_MSB 11
VCE_CONTROL_SET_RUN 1
USB_GHWCFG4_NUM_IN_EPS_LSB 26
USB_GUSBCFG_ULPI_UTMI_SEL_MSB 4
DMA1_CS_RESET_CLR 0x7fffffff
MPHI_INTSTAT_IMFOFLW_LSB 29
UART_LCR_PEN_CLR 0xfffffff7
PIXELVALVE1_DSI_HACT_ACT_MASK 0x0000ffff
CM_DSI1ECTL_BUSYD_CLR 0xfffffeff
AVE_IN_BUF0_ADDRESS_RESET 0000000000
SLIM_DCC3_PA1_MASK 0x00ffff3f
A2W_PLLA_ANA_SSCL_MASK 0x003fffff
GP_HEN2_HENn64_MSB 5
SD_DQLCRC10_FALL_MSB 15
CMI_CAM1_RX2SRC_SET 0x000000c0
CM_SDCCTL_ENAB_BITS 4:4
DMA9_CS_END_CLR 0xfffffffd
INTERRUPT_VIDEOSCALER ((64) + 33 )
PCM_MODE_A_FSM_MSB 21
SMI_DSR0_RSTROBE_CLR 0xffffff80
AVE_IN_CTRL_HIGH_PRIORITY_LSB 20
PWMSTA_FULL1 0
L1_L1_SANDBOX_START2_CTRL_BITS 0:0
DMA13_BASE 0x7e007d00
DSI_PR_TO_CNT 0x7e209000 + 0x3C:RW
A2W_PLLH_PIX_MASK 0x000003ff
AVE_IN_CTRL_BUF0_IRQ_EN_LSB 1
DMA8_DEBUG_DMA_ID_MSB 15
L1_IC1_CONTROL_MASK 0x0000007f
SLIM_DMA_MC_TX_WIDTH 32
DMA8_TXFR_LEN_XLENGTH_MSB 15
RNG_STATUS 0x7e104004:RW
TH0_ADDR_MASK 0x0000003F
VPU_ARB_CTRL_UC_CHANNEL_INIBIT_BITS 15:8
MPHI_OUTDDB_TENDINT_CLR 0xdfffffff
USB_DIEPDMA10_MASK 0xffffffff
A2W_SMPS_B_STATR_RESET 0000000000
DSI1_INT_STAT 0x7e700030:RW
IC1_MASK4_RESET 0000000000
ARM_T_LOAD 0x7E00B000 +0x400:RW
DMA6_BASE 0x7e007600
SLIM_DMA_MC_RX_MASK 0xffffffff
L1_L1_SANDBOX_START7_CTRL_MSB 0
A2W_SMPS_L_SIV_MASK 0x0000001f
SD_CS_PUSKIP_CLR 0xffffffef
HDMI_DVO_TIMING_ADJUST_A_RESET 0x00088888
GP_LEV1_LEVn32_MSB 31
DMA7_CS_RESET_CLR 0x7fffffff
SYSAC_HVSM_PRIORITY_P_PRIORITY_CLR 0xffffff0f
TXP_CTRL_PILOT_SET 0xff000000
DMA14_DEST_AD 0x7e007e10:RO
SLIM_DMA_DC7_MASK 0xffffffff
HDMI_CEC_TX_DATA_2_MASK 0xffffffff
EMMC_INTERRUPT_DATA_DONE_CLR 0xfffffffd
CM_PLLC_LOADPER_BITS 6:6
HDMI_ASYNC_RM_FORMAT (HDMI_BASE_ADDRESS + 0x300) + 24:RW
HDMI_HORZB_MANUAL_HFP_MSB 9
HDMI_FIFO_CTL_INV_CLK_XFR_LSB 3
SD_DQLCRC11_RISE_CLR 0x0000ffff
CAM0_CAMIDC_MASK 0xffffffff
SD_SECSRT0_ADDR_LS_SET 0x00001ffe
DMA2_STRIDE_S_STRIDE_BITS 15:0
USB_DIEPDMA4_WIDTH 32
SD_DQLCRC8_FALL_CLR 0xffff0000
DMA_INT_STATUS_INT7_BITS 7:7
PWM_STA_BERR_BITS 8:8
GP_FSEL6_FSEL64_MSB 14
HDMI_CEC_TX_DATA_1_RESET 0000000000
CAM1_CAMIBEA1_WIDTH 32
USB_DIEPCTL0_EO_FR_NUM_RESET 0x0
DMA1_CS_PAUSED_BITS 4:4
I2C_SPI_SLV_MIS_RXMIS_BITS 0:0
DMA0_DEBUG_READ_ERROR_MSB 2
EMMC_IRPT_EN_CBAD_ERR_CLR 0xfff7ffff
L1_IC0_BP_MISSES 0x7ee0204c:RO
TXP_PROGRESS 0x7e004010:RO
APERF1_BW1_WTRANS 0x7ee08090:RO
DMA10_CS_ABORT_CLR 0xbfffffff
A2W_PLLH_AUX_BYPEN_LSB 9
MPHI_TXAXICFG_TXPPRIO_RESET 0x0
USB_DOEPDMAB10_WIDTH 32
CM_DFTCTL_KILL_CLR 0xffffffdf
GP_LEN1 0x7e200074:RW
GP_LEN2 0x7e200078:RW
CM_PLLH_LOADPIX_SET 0x00000001
SH_HCFG_SDIO_IRPT_EN_CLR 0xffffffdf
CM_DSI1PDIV_DIV_LSB 12
EMMC_INTERRUPT_RETUNE_MSB 12
SMI_CS_PVMODE_MSB 12
CM_BURSTCTL_BUSY_MSB 7
NU_HOSTIO_OF_MASK 0xffffffff
USB_DIEPCTL0_USB_ACT_EP_LSB 15
SD_SF_POWSAV_T_SET 0x0007fe00
A2W_PLLD_CORE_CHENB_CLR 0xfffffeff
APERF0_BW1_CTRL_BUS_RESET 0x0
DMA7_TI_PERMAP_MSB 20
USB_DOEPINT0_STS_PHSE_RCVD_BITS 5:5
SPI_CS_CPHA_CLR 0xfffffffb
EMMC_CONTROL0_PWCTL_HWRST_MSB 12
SMI_FD_FCNT_CLR 0xffffffc0
USB_DPTXFSIZ14_MASK 0xffffffff
CM_DFTCTL_SRC_BITS 3:0
USB_DIEPINT0_EP_DISBLD_BITS 1:1
EMMC_IRPT_MASK_DMA_ERR_BITS 28:28
GP_EDS0_RESET 0000000000
USB_GUSBCFG_OTG_I2C_SEL_MSB 16
EMMC_CMDTM_TM_AUTO_CMD_EN_CLR 0xfffffff3
CM_TD1DIV_DIV_BITS 23:0
CM_EMMCCTL_BUSY_SET 0x00000080
FPGA_CTRL0_LV_SPARE_OUT_CLR 0xfff3ffff
SD_SD_T_RPab_BITS 31:28
VRF_SIZE (4096+64+64)
HDMI_MAI_CHANNEL_MAP_MASK 0x00ffffff
SD_DQRCRC3_FALL_RESET 0x0
A2W_PLLD_PER_MASK 0x000003ff
HDMI_DETECTED_HORZA 0x7e902138:RW
DMA7_DEBUG_DMA_STATE_LSB 16
DMA14_TI_WAIT_RESP_SET 0x00000008
HDMI_RAM_PACKET_12_8_RESET 0000000000
DMA10_TI_DEST_INC_CLR 0xffffffef
HD_MAI_CTL_DLATE_RESET 0x0
SH_DATA_DATA_SET 0xffffffff
CCP2TX_TS_MASK 0x000f1f7f
DMA3_DEBUG_OUTSTANDING_WRITES_MSB 7
I2C2_FIFO_MASK 0x000000ff
DMA9_TI_DEST_INC_MSB 4
ARM_1_MAIL1_POL (0x7E00B000 +0x900)+0xB0:RW
SMI_DSW0_WWIDTH_LSB 30
A2W_PLLA_ANA2_WIDTH 24
CM_PLLC_HOLDCORE1_CLR 0xfffffff7
DC1CS 0xffffffff:RW
USB_DOEPINT0 0x7e980b08:RW
USB_DOEPINT1 0x7e980b28:RW
USB_DOEPINT2 0x7e980b48:RW
A2W_PLLD_CORE_DIV_CLR 0xffffff00
CM_CCP2DIV_RESET 0x00001000
USB_DOEPINT5 0x7e980ba8:RW
USB_DOEPINT6 0x7e980bc8:RW
USB_DOEPINT7 0x7e980be8:RW
USB_DOEPINT8 0x7e980c08:RW
USB_DOEPINT9 0x7e980c28:RW
GP_SET2_SETn64_BITS 5:0
A2W_PLLH_DIG0R_MASK 0x00ffffff
APERF0_BW2_CTRL_RESET_SET 0x80000000
CM_SLIMDIV_MASK 0x00ffffff
GRSAADR 0x1A005800 + 0x1C:RW
PCM_MODE_A_FSI_LSB 20
SD_DQLCRC12_WIDTH 32
DMA11_CS_PAUSED_LSB 4
USB_HCCHAR0_EP_TYPE_LSB 18
CM_SLIMCTL_ENAB_CLR 0xffffffef
DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
L1_D1_RD_SNOOPS_MASK 0000000000
CM_PLLD_DIGRST_LSB 9
A2W_PLLC_ANA_SSCLR_WIDTH 17
USB_DFIFO9_WIDTH 32
USB_DOEPTSIZ0_XFERSIZE_RESET 0x0
CCP2TX_TTC_FSP_CLR 0xffffefff
DMA_INT_STATUS_INT14_MSB 14
IC1_SRC1_MASK 0xffffffff
CM_DSI1PCTL_BUSYD_LSB 8
ARM_1_MAIL0_WRT (0x7E00B000 +0x900)+0x80:RW
SLIM_DCC4_CON_RESET 0000000000
CPG_Config_WIDTH 32
A2W_PLLD_PER_BYPEN_SET 0x00000200
DMA10_CONBLK_AD_WIDTH 32
USB_GHWCFG3_I2C_INTERFACE_MSB 8
SLIM_DCC0_PROT 0x7e210210:RW
SCALER_CONTEXT_MEMORY_START (0x7e400000 + 0x2000)
A2W_PLLC_ANA_SCTL_SEL_MSB 2
USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_SET 0x00000020
USB_DIEPTXF8_WIDTH 32
CM_EMMCDIV_DIV_SET 0x0000fff0
HDMI_HOTPLUG_WIDTH 1
SD_SC_T_RFC_SET 0x7f000000
PIXELVALVE2_DSI_HACT_ACT_WIDTH 16
OTP_WRITE_DATA_READ_REG_MASK 0xffffffff
USB_DOEPINT0_BACK2BACK_SETUP_LSB 6
DMA12_CS_ERROR_CLR 0xfffffeff
CM_PWMDIV_RESET 0000000000
USB_DTXFSTS3_WIDTH 32
USB_GHWCFG3_MODE_MSB 7
USB_GMDIOCSR_WIDTH 16
CM_TIMERCTL_BUSYD_BITS 8:8
CM_PWMDIV_DIV_SET 0x00ffffff
I2C_SPI_SLV_RIS_TXRIS_BITS 1:1
AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_LSB 31
SLIM_BASE 0x7e210000
CM_PWMCTL_KILL_LSB 5
DMA1_DEBUG_VERSION_MSB 27
DMA2_DEBUG_DMA_ID_LSB 8
CAM0_CAMCAP1_RESET 0000000000
CCP2TX_TS_TEI_SET 0x00040000
SD_SE_RL_RESET 0x8
DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
HDMI_CEC_CNTRL_5_MASK 0x0fffffff
A2W_PLLA_ANA_SCTLR_RESET 0000000000
APERF1_BW1_RTRANS_RESET 0000000000
SLIM_MC_IN_STAT_MASK 0x0000000f
SLIM_DMA_DC_CON_RESET 0000000000
CM_INTEN_FGAINC_CLR 0xffffefff
USB_GHWCFG3_DFIFO_DEPTH_RESET 0x0
USB_DFIFO14_WIDTH 32
IC1_SRC0_WIDTH 32
DMA7_CS 0x7e007700:RW
SMI_DC_REQR_LSB 6
USB_GNPTXSTS_TX_Q_SPC_AVAIL_RESET 0x0
TS_TSENSCTL_EN_INT_MSB 5
PM_RSTS_HADWRQ_SET 0x00000010
USB_DIEPDMA8_MASK 0xffffffff
HD_VID_CTL_UFEN_RESET 0x0
A2W_PLLH_CTRL_PWRDN_LSB 16
PCM_TXC_A_CH1EN_SET 0x40000000
DMA6_CS_END_CLR 0xfffffffd
PWM_CTL_MODE4_SET 0x02000000
I2C_SPI_SLV_CR_TXE_SET 0x00000100
APERF1_BW0_RTRANS_MASK 0xffffffff
PM_PROC_POWOK_BITS 1:1
USB_HCSPLT6_MASK 0xffffffff
HD_CSC_32_31_RESET 0000000000
APERF0_BW1_CTRL_WIDTH 32
DSI0_PHYC_dlane_hsen_1_sync_MSB 5
L1_L1_SANDBOX_START1_START_ADDR_BITS 29:5
DMA7_SOURCE_AD_MASK 0xffffffff
USB_DOEPCTL0_SET_ODD_FR_LSB 29
PM_AUDIO_CTRLEN_SET 0x00100000
GP_AJBCONF_RESET 0000000000
A2W_XOSC1_MASK 0x00ffffff
DMA0_DEBUG_LITE_CLR 0xefffffff
SLIM_DCC3_CON_WIDTH 32
DMA13_CS_DREQ_STOPS_DMA_MSB 5
GP_REN2_RENn64_CLR 0xffffffc0
DMA9_CS_ERROR_BITS 8:8
A2W_SMPS_C_MULTI_WIDTH 0
USB_DIEPINT0_TX_FIFO_UNDRN_LSB 8
DMA13_TXFR_LEN_XLENGTH_SET 0x0000ffff
TS_TSENSCTL_DIRECT_CLR 0xffffffbf
SD_SB_EIGHTBANK_CLR 0xffffffef
USB_GINTMSK_WK_UP_INT_MSB 31
L1_IC0_CONTROL_WIDTH 7
USB_DIEPCTL0_TYPE_MSB 19
MPHI_MOUTFS_LEVEL_LSB 0
CM_INTEN_LOSSC_LSB 7
DMA3_TI_SRC_DREQ_CLR 0xfffffbff
DMA3_TI_WAIT_RESP_MSB 3
CM_GNRICCTL_GATE_BITS 6:6
USB_HCCHAR3_MASK 0xffffffff
CM_LOCK_LOCKB_CLR 0xfffffffd
MPHI_C0INDFS_CFIFOLVL_BITS 31:16
DSI0_RX2_PKTH_WIDTH 32
DMA9_DEBUG_LITE_SET 0x10000000
DMA10_CONBLK_AD_SCB_ADDR_MSB 31
EMMC_HWCAP1_DATA_RETUNE_LSB 14
HDMI_AN1_RESET 0000000000
AVE_IN_CTRL_LENGTH_IN_PXLS_MSB 8
L1_L1_SANDBOX_START3_CTRL_MSB 0
A2W_PLLA_CORE_WIDTH 10
SD_RWC_WRTVAL_CLR 0xffffe0ff
CPG_Trigger_WIDTH 2
CAM0_CAMDBCTL_WIDTH 32
CM_INTEN_BADPASS_MSB 18
ALIAS_L1_NONALLOCATING(x) MACRO
CM_DPICTL_BUSYD_SET 0x00000100
PCM_CS_A_TXTHR_MSB 6
HDMI_TX_PHY_TX_PHY_STATUS_WIDTH 32
CAM1_CAMDBSA0 0x7e801204:RW
SD_SB_COLBITS_BITS 1:0
USB_GHWCFG3_I2C_INTERFACE_RESET 0x0
DMA10_DEBUG_FIFO_ERROR_BITS 1:1
USB_GINTMSK_ERLY_SUSP_LSB 10
L1_IC0_FLUSH_E_MASK 0xffffffe0
CM_PLLA_HOLDCCP2_MSB 3
CM_EMMCCTL_BUSY_BITS 7:7
IC1_MASK2_WIDTH 31
APERF0_BW1_WMAX_WIDTH 16
PM_AVS_RSTDR_SYSTEM_A_LSB 1
EMMC_IRPT_EN_BOOTACK_CLR 0xffffdfff
BOOTROM_BASE_ADDRESS 0x10000000
CM_DPICTL_FRAC_SET 0x00000200
USB_DCTL_PWRON_PRG_DONE_CLR 0xfffff7ff
SD_DQLCRC15_FALL_BITS 15:0
DSI1_RXPKT1_H_WIDTH 32
PM_AUDIO_WIDTH 22
SD_PT1_T_INIT1_CLR 0xffffff00
CM_VPUCTL_FRAC_CLR 0xfffffdff
DMA1_DEST_AD 0x7e007110:RO
DMA_ENABLE_EN12_CLR 0xffffefff
DMA11_TI_PERMAP_LSB 16
VPU_ARB_CTRL_L2_THRESHOLD_LSB 4
PIXELVALVE_HSYNC_0 PIXELVALVE0_HSYNC
PIXELVALVE_HSYNC_1 PIXELVALVE1_HSYNC
HDMI_READ_POINTERS_DRFT_HOLD_RD_SET 0x00400000
DMA_INT_STATUS_INT10_LSB 10
EMMC_IRPT_MASK_SDOFF_ERR_BITS 23:23
A2W_PLLB_ANA_KAIP_KI_SET 0x00000070
MS_SEMA_20_MASK_SET 0x00000001
APERF0_BW2_RMAX_RESET 0000000000
A2W_PLLA_ANA2R_RESET 0000000000
VCE_BAD_ADDR 0x7f000000 + 0x140030:RW
GRTCFG0 0x1A005200 + 0x04:RW
GRTCFG1 0x1A005220 + 0x04:RW
GRTCFG2 0x1A005240 + 0x04:RW
DMA4_CS_PRIORITY_CLR 0xfff0ffff
GRTCFG4 0x1A005280 + 0x04:RW
GRTCFG5 0x1A0052A0 + 0x04:RW
GRTCFG6 0x1A0052C0 + 0x04:RW
GRTCFG7 0x1A0052E0 + 0x04:RW
SLIM_DCC2_PA0_MASK 0x00ffff1f
JOWDATA 0x7e005000 + 0x3C:RW
CM_PULSECTL_BUSY_CLR 0xffffff7f
DMA13_NEXTCONBK_WIDTH 32
SH_HSTS_FIFO_ERROR_LSB 3
A2W_PLLD_ANA_KAIP_KP_MSB 3
HDMI_RAM_PACKET_13_0_MASK 0xffffffff
I2C_SPI_SLV_DMACR 0x7e214028:RW
DMA5_CS_RESET 0000000000
SD_DQRCRC4_RISE_BITS 31:16
CM_LOCK_LOCKB_MSB 1
DMA5_SOURCE_AD_S_ADDR_CLR 0x00000000
MPHI_CTRL_INVERT_SET 0x00000100
DMA10_SOURCE_AD_MASK 0xffffffff
A2W_XOSC_CTRLR_MASK 0x000000ff
APERF1_BW2_CTRL_BUS_RESET 0x0
GP_LEV0 0x7e200034:RO
GP_LEV1 0x7e200038:RO
GP_LEV2 0x7e20003c:RO
SD_DQRCRC0_FALL_RESET 0x0
USB_GUSBCFG_DDR_SEL_LSB 7
DMA9_TI_DEST_WIDTH_LSB 5
PCMCS_RXTHR_LSB 7
CCP2TX_TC_MEN_LSB 1
USB_DOEPCTL5_MASK 0xffffffff
CCP2TX_TTC_LEC_BITS 11:8
A2W_PLLD_ANA_SSCSR_WIDTH 17
CM_VPUCTL_GATE_BITS 6:6
PCM_INTSTC_A_RXR_SET 0x00000002
I2C_SPI_SLV_FR_TXFLEVEL_SET 0x00000000000
IC0_FORCE0_CLR 0x7e002050:RW
CM_PULSEDIV_DIV_CLR 0xff000fff
GP_LEN2_LENn64_LSB 0
CM_PLLC_LOADCORE1_LSB 2
AUX_SPI0_CNTL0_REG (0x7E215000 +0x080)
DMA5_DEST_AD_D_ADDR_LSB 0
DMA10_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
MPHI_C0INDCF_LENGTH_CLR 0xfff00000
A2W_XOSC_CTRL_PLLAEN_MSB 6
INTERRUPT_HW_NUM (64)
A2W_PLLC_ANA_SCTLR_MASK 0x0000001f
USB_DVBUSPULSE_PULSE_BITS 11:0
AVE_OUT_CB_COEFF_GREEN_COEFF_LSB 10
CM_GP0CTL_MASH_LSB 9
HDMI_RAM_GCP_8_WIDTH 32
HDMI_CP_TST_WIDTH 22
USB_DIEPINT0_IN_TKN_TXFEMP_BITS 4:4
A2W_XOSC_CTRL_SMPSEN_SET 0x00000008
PM_PADS0_HYST_LSB 3
unix 1
DMA3_TI_INTEN_SET 0x00000001
I2C_SPI_SLV_IMSC_TXIM_CLR 0xfffffffd
DMA14_CS_ACTIVE_SET 0x00000001
DMA_INTERRUPT(n) MACRO
USB_GUSBCFG_USB_TRD_TIM_CLR 0xffffc3ff
I2C_SPI_SLV_MIS_OEMIS_SET 0x00000008
CCP2TX_TAC_BPD_MSB 2
PCM_INTSTC_A_RESET 0000000000
CM_HSMCTL_GATE_SET 0x00000040
EMMC_IRPT_MASK_ATA_ERR_CLR 0xdfffffff
TS_TSENSCTL_PRWDW_CLR 0xfffffffe
PM_AVS_INTEN_ALERT_SYSTEM_A_CLR 0xfffffffd
GP_AJBTMS_WIDTH 32
APERF0_BW0_CTRL_ID_MSB 12
PCM_RXC_A_CH1WID_SET 0x000f0000
OTP_PUBLIC_KEY_ROW_REDUNDANT (((((((((((((((8 +4)+4)+1)+1)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+4)
DMA4_TI_DEST_IGNORE_CLR 0xffffff7f
SD_TMC_TS_RESET 0x0
DMA12_DEBUG_DMA_ID_LSB 8
HDMI_RAM_PACKET_12_6_WIDTH 32
CM_PLLC_HOLDCORE1_BITS 3:3
DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
USB_GUSBCFG_DDR_SEL_RESET 0x0
DMA13_CS_RESET 0000000000
SMI_DSW1_WWIDTH_MSB 31
USB_DIEPINT0_AHB_ERR_CLR 0xfffffffb
DMA12_TI_WAITS_MSB 25
DMA8_CS_RESET_CLR 0x7fffffff
SYSAC_USB_PRIORITY_PRIORITY_BITS 3:0
DMA2_TI_BURST_LENGTH_BITS 15:12
USB_HPRT_TST_CTL_CLR 0xfffe1fff
OTP_BOOTMODE_REG 0x7e20f000:RW
GP_FSEL3_FSEL33_CLR 0xfffff1ff
CM_TSENSCTL_BUSY_CLR 0xffffff7f
DMA9_TI_SRC_DREQ_LSB 10
A2W_PLLD_ANA_SCTL_UPDATE_CLR 0xfffffff7
USB_GMDIOGEN_MASK 0xffffffff
EMMC_INTERRUPT_ENDBOOT_SET 0x00004000
DMA15_NEXTCONBK_MASK 0xffffffe0
DMA1_TI_BURST_LENGTH_CLR 0xffff0fff
DMA2_NEXTCONBK_ADDR_CLR 0x0000001f
INTERRUPT_DMA11 ((64) + 27 )
INTERRUPT_DMA12 ((64) + 28 )
INTERRUPT_DMA13 ((64) + 29 )
INTERRUPT_DMA14 ((64) + 30 )
DMA2_DEBUG_LITE_MSB 28
USB_HCTSIZ2_WIDTH 32
PM_IMAGE_PERIRSTN_BITS 6:6
HDMI_DETECTED_VERTB0_RESET 0x00000021
USB_PCGCR 0x7e980e00:RW
IC1_MASK6_WIDTH 31
USB_GHWCFG2_HSPHY_INTERFACE_RESET 0x0
EMMC_FORCE_IRPT_DTO_ERR_LSB 20
CM_H264CTL_ENAB_MSB 4
PM_AVS_EVENT_ALERT_ARM_P_CLR 0xffffffef
L1_L1_SANDBOX_END7_RESET 0000000000
USB_DIEPTSIZ5_WIDTH 32
DMA12_TI_DEST_WIDTH_LSB 5
APERF0_BW2_RMAX_WIDTH 24
DMA0_DEST_AD_D_ADDR_CLR 0x00000000
USB_HCSPLT0_PRT_ADDR_SET 0x0000007f
A2W_PLLB_ANA_VCO_RANGE_SET 0x00000001
SCALER_COB_FIFO_SIZE (0x4000)
DSI1_RXPKT2_H_MASK 0xffffffff
A2W_HDMI_CTL_HFEN_HFEN_SET 0x00000001
DMA14_NEXTCONBK_ADDR_CLR 0x0000001f
DMA1_TI_PERMAP_BITS 20:16
SPI_CS_RXD_CLR 0xfffdffff
HDMI_RAM_PACKET_12_1 0x7e9025b4:RW
HDMI_RAM_PACKET_12_2 0x7e9025b8:RW
HDMI_RAM_PACKET_12_4 0x7e9025c0:RW
HDMI_RAM_PACKET_12_5 0x7e9025c4:RW
CM_DSI0EDIV_RESET 0000000000
HDMI_RAM_PACKET_12_7 0x7e9025cc:RW
SLIM_DMA_MC_CON_RESET 0000000000
CM_HSMCTL 0x7e101088:RW
ASB_ISP_M_CTRL_EMPTY_MSB 2
EMMC_CONTROL2_EN_PSV_SET 0x80000000
DMA0_CS_PANIC_PRIORITY_MSB 23
IC0_MASK1 0x7e002014:RW
IC0_MASK2 0x7e002018:RW
IC0_MASK3 0x7e00201c:RW
IC0_MASK4 0x7e002020:RW
IC0_MASK5 0x7e002024:RW
IC0_MASK6 0x7e002028:RW
IC0_MASK7 0x7e00202c:RW
USB_HCCHAR5 0x7e9805a0:RW
USB_HCCHAR6 0x7e9805c0:RW
V3D_PCTR0_MASK 0xffffffff
DMA12_DEST_AD_D_ADDR_CLR 0x00000000
DSI0_PHYC_dsi_esc_lpdt_LSB 12
HDMI_FIFO_CTL_FIFO_RESET_LSB 5
HDMI_RAM_PACKET_STATUS_RESET 0000000000
A2W_PLLH_DIG0_RESET 0000000000
SMI_CS_RXD_CLR 0xdfffffff
SLIM_DMA_DC4_WIDTH 32
USB_GAHBCFG_P_TXF_EMP_LVL_RESET 0x0
SLIM_DMA_DC_CON 0x7e210084:RW
CM_TSENSDIV_DIV_SET 0x0001f000
UNICAM_DBCTL(x) MACRO
CM_SLIMCTL_SRC_CLR 0xfffffff0
A2W_PLLB_ANA_SCTL_RESET_MSB 4
USB_GUSBCFG_IND_PASS_THRU_BITS 24:24
GP_FSEL2_FSEL22_SET 0x000001c0
USB_GI2CCTL_DEV_ADR_MSB 27
ARM_IRQ_ENBL1 0x7E00B000 +0x210:RW
SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_SET 0x00000003
SH_CMD_NO_RESPONSE_MSB 10
A2W_PLLD_ANA_SSCS_STEP_LSB 0
HDMI_SCHEDULER_CONTROL_ENC_ONLY_WHEN_AUTH_CLR 0xffffffbf
CM_PULSECTL_BUSY_SET 0x00000080
I2C_SPI_SLV_DR_RXDMAPREQ_MSB 12
SMI_DSR1_RSETUP_LSB 24
GROPCTR_FBC_CZ_PBE_MISSES 0x26
SLIM_DCC3_PA1_WIDTH 24
SD_DQLCRC11_MASK 0xffffffff
A2W_SMPS_CTLA0_WIDTH 24
STCHI_0 0x7e003008:RO
STCHI_1 0xffffffff:RO
GROPCTRS4 0x1A005100 + 0x0A4:RW
CCP2TX_TS_TFF_LSB 5
I2C0_BASE 0x7e205000
SD_SD_T_RAS_BITS 12:8
TB_TASK_NUM_MSB 15
EMMC_CONTROL0_HCTL_8BIT_CLR 0xffffffdf
A2W_PLLC_FRAC_FRAC_SET 0x000fffff
ARM_T_FREECNT 0x7E00B000 +0x420:RW
DMA1_SOURCE_AD_S_ADDR_MSB 31
GPAFEN0 0x7e200000 + 0x88:RW
GPAFEN1 0x7e200000 + 0x8C:RW
GPAFEN2 0x7e200000 + 0x90:RW
CM_V3DCTL_FRAC_SET 0x00000200
HDMI_DETECTED_HORZA_MANUAL_HAP_BITS 12:0
PIXELVALVE1_VERTB_MASK 0xffffffff
A2W_PLLB_DIG2R_RESET 0x00100401
CM_AVEODIV_WIDTH 16
SD_SE_MASK 0x13f3f73f
L1_D_PRIORITY_c1_per_priority_MSB 27
V3D_VPMBASE_MASK 0xffffffff
SLIM_DMA_DC1_MASK 0xffffffff
SCALER_0_DMA (21*(1<<16))
CM_PLLD_LOADCORE_BITS 4:4
DMA14_TI_INTEN_BITS 0:0
SYSAC_PERI_ARBITER_CONTROL_LIMIT_SET 0x00000003
DMA14_SOURCE_AD 0x7e007e0c:RO
USB_GUSBCFG_FORCE_HST_MODE_MSB 29
A2W_PLLA_CORE 0x7e102400:RW
STCHI_x(x) MACRO
PCM_MODE_A_CLKI_MSB 22
HD_VID_CTL_RST_FRAMEC_SET 0x20000000
HD_MAI_THR_DREQLOW_RESET 0x1
AVE_IN_STATUS_OVERRUN_DET_LSB 0
A2W_PLLC_ANA_STAT_DATA_CLR 0xfffff000
MS_SEMA_15_MASK 0x00000001
USB_GNPTXFSIZ_NP_TXF_ST_ADDR_SET 0x0000ffff
USB_DOEPCTL3_WIDTH 32
USB_DIEPCTL0_TXF_NUM_RESET 0x0
EMMC_HWCAP0_V1_8_MSB 26
DMA11_TI_DEST_INC_CLR 0xffffffef
USB_GOTGCTL_HST_NEG_SCS_MSB 8
ARM_IRQ_PEND0 0x7E00B000 +0x200:RW
ARM_IRQ_PEND1 0x7E00B000 +0x204:RW
ARM_IRQ_PEND2 0x7E00B000 +0x208:RW
APERF1_BW2_CTRL_LATHALT_RESET 0x0
DMA15_DEBUG_DMA_STATE_LSB 16
GP_LEN0_RESET 0000000000
APERF1_BW0_AMAX_WIDTH 24
DMA7_DEBUG_OUTSTANDING_WRITES_MSB 7
DMA10_CS_ACTIVE_LSB 0
A2W_PLLA_ANA_STATR_RESET 0000000000
USB_DOEPCTL0_DPID_MSB 16
L1_IC1_PRIORITY_IC1_APRIORITY0_BITS 3:0
DMA11_CS_INT_BITS 2:2
SD_SE_T_RTP_RESET 0x3
PCM_CS_A_DMAEN_CLR 0xfffffdff
DMA0_DEBUG_FIFO_ERROR_CLR 0xfffffffd
USB_GINTMSK_HCH_INT_MSB 25
HDMI_RAM_PACKET_4_0_MASK 0xffffffff
MS_SEMA_26_MASK_BITS 0:0
PCMCS_TXCLR (1 << 3)
PM_PADS3_RESET 0x0000001b
EMMC_FORCE_IRPT_DMA_ERR_MSB 28
MS_SEMA_27_MASK_SET 0x00000001
A2W_PLLC_ANA_VCOR_MASK 0x00000001
DMA14_CS_ERROR_LSB 8
USB_GUSBCFG_ULPI_EXT_VBUS_DRV_LSB 20
HD_VID_CTL_BLANKPIX_SET 0x00040000
I2CDLEN_0 0x7e205000 + 0x08:RW
I2CDLEN_1 0x7e804000 + 0x08:RW
I2CDLEN_2 0x7e805000 + 0x08:RW
I2CDLEN_3 I2C_BASE_3 + 0x08:RW
SLIM_DCC9_PA0_MASK 0x00ffff1f
DMA2_CONBLK_AD_MASK 0xffffffe0
DMA12_SOURCE_AD_WIDTH 32
CM_TECCTL_BUSYD_BITS 8:8
MS_SEMA_20_MASK 0x00000001
SD_CS_DLLCAL_CLR 0xfffff3ff
DMA0_TI_PERMAP_SET 0x001f0000
USB_DCFG_MASK 0x03fc1ff7
ASB_ISP_M_CTRL_RCOUNT_CLR 0xffffc00f
DMA11_CONBLK_AD_WIDTH 32
DMA14_TI_BURST_LENGTH_MSB 15
SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_LSB 8
MPHI_INTSTAT_RX0MEND_LSB 0
PWM_DMAC_PANIC_BITS 15:8
PM_RSTC_SRCFG_LSB 8
SYSAC_TRANS_PRIORITY_P_PRIORITY_BITS 7:4
CCP2TX_TC_CLKM_SET 0x00000004
DMA_INT_STATUS_INT6_BITS 6:6
CM_GNRICCTL_SRC_MSB 3
DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
USB_DIEPTXF1_FIFO_STADDR_SET 0x0000ffff
USB_DIEPINT5_WIDTH 32
EMMC_CONTROL0_HCTL_DMA_SET 0x00000018
TXP_XTRA 0x7e004018:RW
TH0CFG 0x18011000 + 0x04:RW
HDMI_DETECTED_VERTB1_MANUAL_VSPO1_CLR 0xffc001ff
HDMI_RAM_PACKET_9_0 0x7e902544:RW
HDMI_RAM_PACKET_9_1 0x7e902548:RW
HDMI_RAM_PACKET_9_2 0x7e90254c:RW
HDMI_CEC_RX_DATA_2_WIDTH 32
HDMI_RAM_PACKET_9_4 0x7e902554:RW
HDMI_RAM_PACKET_9_5 0x7e902558:RW
HDMI_RAM_PACKET_9_6 0x7e90255c:RW
DMA10_CS_PAUSED_MSB 4
HDMI_RAM_PACKET_9_8 0x7e902564:RW
HDMI_HORZB_MANUAL_HSP_CLR 0xfff003ff
VEC_FREQ3_2_MASK 0xffffffff
ASB_H264_S_CTRL_CLR_REQ_LSB 0
AJBTDO 0x7e2000c0 +0x0c:RW
EMMC_STATUS_DAT_ACTIVE_MSB 2
DMA6_TXFR_LEN_YLENGTH_LSB 16
CM_DSI0PCTL_BUSYD_MSB 8
USB_DOEPDMA11_WIDTH 32
A2W_PLLB_ANA_SCTLR_RESET 0000000000
MS_SEMA_5_WIDTH 1
APERF1_GEN_CTRL_RESET_CLR 0xfffffffd
USB_HCSPLT2_WIDTH 32
HDMI_READ_POINTERS_DRFT_ALMOST_MT_SET 0x00040000
SCALER_DISPBKGND0_WIDTH 32
A2W_PLLA_ANA_STAT_WIDTH 12
A2W_XOSC_CTRL_PLLAOK_BITS 18:18
UART_LCR_EPS_MSB 4
CM_GP1CTL_KILL_CLR 0xffffffdf
CM_VECDIV_DIV_CLR 0xffff0fff
JC0S 0x7e005000 + 0x58:RW
EMMC_FORCE_IRPT_RESET 0x00000001
JC0W 0x7e005000 + 0x64:RW
DMA7_CS_PRIORITY_MSB 19
SH_RSP0_CARD_STATUS_SET 0xffffffff
EMMC_IRPT_MASK_CMD_DONE_BITS 0:0
MPHI_INTSTAT_RX0DISC_SET 0x00100000
CAM0_CAMDBEA1_MASK 0xffffffff
DMA6_TI_NO_WIDE_BURSTS_LSB 26
MS_SEMA_15 0x7e00003c:RW
SCALER_DISPSTAT_DSP1_STATUS_SET 0x003f0000
CM_TECDIV_RESET 0000000000
APERF1_BW0_RMAX 0x7ee08064:RO
HD_MAI_CTL_FLUSH_CLR 0xfffffdff
DMA15_DEBUG_VERSION_SET 0x0e000000
SD_SECEND2_ADDR_MS_SET 0xffffe000
SYSAC_JPEG_PRIORITY_N_PRIORITY_RESET 0x0
CM_TECCTL_WIDTH 10
GPEDS1 0x7e200000 + 0x44:RW
L1_D1_WBACKS_MASK 0000000000
CM_PERIICTL_MASK 0x00000040
CM_SMIDIV_DIV_BITS 15:4
SLIM_DCC4_STAT_RESET 0000000000
JP_MADDR 0x7e005030:RW
UART_LCR_LOOP_MSB 4
AVE_IN_BUF1_ADDRESS_BUF1_ADDR_MSB 31
USB_DOEPCTL10_WIDTH 32
DMA_BASE 0x7e007fe0
USB_HCFG_LS_PHY_CLK_SEL_LSB 0
SD_DQRCRC14_FALL_BITS 15:0
ASB_V3D_M_CTRL_CLR_ACK_CLR 0xfffffffd
JC1W 0x7e005000 + 0x68:RW
UART_BASE 0x7e201000
DMA4_TI_SRC_DREQ_CLR 0xfffffbff
I2C_SPI_SLV_ICR_BEIC_CLR 0xfffffffb
APERF1_BW1_CTRL_ID_EN_MSB 29
USB_DVBUSPULSE_PULSE_RESET 0x0
DMA15_DEBUG_READ_ERROR_LSB 2
DMA4_TI_SRC_IGNORE_BITS 11:11
APERF1_BW0_CTRL_ID_LSB 8
APERF0_BW1_CTRL_RESET 0000000000
DMA0_CS_END_CLR 0xfffffffd
USB_GPVNDCTL_CTRL_UTMI_SET 0x00000f00
SYSAC_V3D_LIMITER_HOLDOFF_LSB 0
V3D_FDBG0_WIDTH 32
DMA15_CS_DISDEBUG_SET 0x20000000
IFORCE0_0 0x7e002040:RW
HDMI_RAM_PACKET_11_7_MASK 0xffffffff
TE_0C 0x7e20e000:RW
DMA11_CS_END_MSB 1
DMA8_TI_DEST_WIDTH_MSB 5
L1_IC0_PRIORITY_IC0_APRIORITY2_MSB 11
JC2S 0x7e005000 + 0x60:RW
JC2W 0x7e005000 + 0x6C:RW
DMA12_TXFR_LEN_XLENGTH_BITS 15:0
DMA5_CS_END_BITS 1:1
PM_IMAGE_MEMREP_MSB 3
EMMC_INTERRUPT_OEM_ERR_CLR 0x3fffffff
PM_SPAREW_SPARE_MSB 23
APERF1_BW1_RPEND 0x7ee08068:RO
DMA6_CS_DREQ_SET 0x00000008
HDMI_PERT_LFSR_FEEDBACK_MASK 0x7e90207c:RW
GP_PUDCLK2_RESET 0000000000
EMMC_IRPT_EN_CEND_ERR_MSB 18
EMMC_FORCE_IRPT_DATA_DONE_LSB 1
HDMI_FIFO_CTL_MASTER_SLAVE_N_CLR 0xfffffffe
MPHI_INTSTAT_RX1MEND_RESET 0x0
SD_CS_PUSKIP_MSB 4
DMA1_DEST_AD_WIDTH 32
DMA1_TI_INTEN_LSB 0
TB_TASK_NUM_LSB 0
PCMINTSTC 0x7e203000 + 0x1c:RW
IC0_FORCE0_CLR_WIDTH 32
MS_MBOX_1_MBOX_SET 0xffffffff
TE_1C 0x7e20e00c:RW
HDMI_RAM_PACKET_1_8_WIDTH 32
A2W_PLLC_ANA_KAIP_KI_SET 0x00000070
SLIM_DCC7_CON 0x7e2102e8:RW
PWM_CTL_MSEN3_BITS 23:23
USB_DOEPTSIZ15_WIDTH 32
A2W_PLLH_ANA_MULTI 0x7e102f70:RW
L1_D_PRIORITY_c0_uc_priority_CLR 0xffffff0f
USB_DIEPCTL0_SET_EVEN_FR_SET 0x10000000
HDMI_RAM_PACKET_6_4_MASK 0xffffffff
MPHI_C0INDCF_EMPTY_BITS 31:31
USB_DOEPTSIZ14_MASK 0xffffffff
HDMI_RAM_PACKET_10_3_WIDTH 32
CM_PLLA_HOLDPER_BITS 7:7
A2W_PLLH_ANA_SCTL_SEL_BITS 2:0
DMA11_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
GP_FEN0_FENn0_LSB 0
DMA8_DEBUG_DMA_STATE_LSB 16
USB_HCINT0_DATA_TGL_ERR_RESET 0x0
HD_CSC_CTL_PADMSB_RESET 0x0
DSI0_TST_MON_RESET 0000000000
FPGA_STATUS0_SD_CD_BITS 5:5
HD_MAI_THR_PANICLOW_LSB 16
CAM1_CAMMISC_WIDTH 32
USB_HCCHAR0_MPS_RESET 0x0
I2CFIFO 0x7e205000 + 0x10:RW
DMA10_TI_BURST_LENGTH_SET 0x0000f000
USB_DIEPINT0_TIMEOUT_LSB 3
A2W_PLLH_DIG3R_RESET 0000000000
SMI_CS_PRDY_MSB 24
GP_LEV1_RESET 0000000000
VEC_CPS32_CPC_WIDTH 32
TXP_XTRA_NOSTBY_SET 0x00000001
DMA6_CS_DREQ_STOPS_DMA_SET 0x00000020
EMMC_FORCE_IRPT_CEND_ERR_LSB 18
SD_DQRCRC0_RISE_RESET 0x0
A2W_PLLB_SP1_CHENB_BITS 8:8
SH_HCFG_WIDE_INT_BUS_BITS 1:1
SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_BITS 5:4
USB_DIEPCTL0_TXF_NUM_SET 0x03c00000
SLIM_DCC6_PROT_RESET 0x000093a0
A2W_PLLA_ANA_SCTL_SEL_SET 0x00000007
USB_DOEPDMAB3_MASK 0xffffffff
DMA6_TI_SRC_IGNORE_CLR 0xfffff7ff
DMA7_TI 0x7e007708:RO
DMA8_CONBLK_AD_SCB_ADDR_MSB 31
DMA2_CS_END_MSB 1
SLIM_DCC5_PA1_MASK 0x00ffff3f
PM_AVS_EVENT_ALERT_V3D_G_LSB 3
DMA0_TXFR_LEN_XLENGTH_SET 0x0000ffff
DMA14_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
ARM_C0_PASSHALT 0x00080000
DMA11_TI_DEST_WIDTH_MSB 5
CM_EVENT_FLOSSD_BITS 17:17
HDMI_RAM_PACKET_12_0_RESET 0000000000
MAX_DMA_NUM 8
SD_SD_T_RPab_RESET 0xa
AVE_IN_CTRL_FRAME_RATE_IRQ_EN_CLR 0xffffffbf
MPHI_INTSTAT_TXEND_BITS 16:16
EMMC_CONTROL2_ACNOX_ERR_BITS 0:0
DMA5_TI_WAIT_RESP_BITS 3:3
GP_AREN2_MASK 0x0000003f
CCP2TX_TS_TXB_LSB 0
TB_JTB_TMS_WIDTH 32
A2W_PLLB_CTRL_PDIV_SET 0x00007000
CSI2_DTOV_x(x) MACRO
PWM_DMAC_PANIC_MSB 15
ARM_T_MSKIRQ 0x7E00B000 +0x414:RW
V3D_IDENT2_WIDTH 32
SH_HCFG_BLOCK_IRPT_EN_LSB 8
DMA6_TI_WAITS_MSB 25
CM_TD0CTL_FLIP_BITS 11:11
DSI_HS_DLT3 0x7e209000 + 0x50:RW
DSI_HS_DLT4 0x7e209000 + 0x54:RW
DSI_HS_DLT5 0x7e209000 + 0x58:RW
I2C_SPI_SLV_IFLS_RXIFPSEL_LSB 9
SD_SF_PHYHOLD_CLR 0xdfffffff
PM_SPAREW_WIDTH 24
SD_VIN_MULT_LSB 24
AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_LSB 0
USB_DIEPCTL5_MASK 0xffffffff
APERF1_BW1_CTRL_LATHALT_CLR 0xefffffff
SD_TMC_TSTCLK_CLR 0xfffffffe
PM_SMPS_UPEN_SET 0x00000004
SD_SECSRT1_ADDR_MS_LSB 13
IC1_WAKEUP_MASK 0xfffffffe
SD_CS_EN_BITS 1:1
DMA5_TXFR_LEN_MASK 0x3fffffff
CM_VECCTL_ENAB_BITS 4:4
FPGA_DCM_WR_DATA_WIDTH 24
SMI_DSR1_FSETUP_LSB 22
USB_DFIFO1_WIDTH 32
AVE_OUT_CTRL_WIDTH 32
USB_GI2CCTL_REG_ADDR_BITS 15:8
DMA15_TI_WAIT_RESP_CLR 0xfffffff7
SLIM_DCC4_CON 0x7e210288:RW
CM_TCNTCTL_SRC0_SET 0x0000000f
USB_DOEPTSIZ0_MC_SET 0x60000000
SD_DQLCRC12_FALL_MSB 15
PIXELVALVE1_VERTB_EVEN_WIDTH 32
EMMC_CONTROL2_ACEND_ERR_SET 0x00000008
SMI_DSR3_RWIDTH_CLR 0x3fffffff
AUX_SPI_CNTL0_CS1_N 0x000A0000
HDMI_CEC_RX_DATA_4_MASK 0xffffffff
USB_DOEPCTL0_EO_FR_NUM_BITS 16:16
I2C_SPI_SLV_RSR_RXDMABREQ_BITS 5:5
SD_SECSRT1_ADDR_MS_BITS 31:13
A2W_XOSC_CTRL_PLLCEN_BITS 0:0
A2W_PLLB_DIG0_MASK 0x00ffffff
CM_PLLA_HOLDDSI0_BITS 1:1
TB_JTB_CONFIG_SBITS_BITS 4:0
V3D_PCTRS7_MASK 0x0000001f
CM_DSI1PCTL_BUSY_LSB 7
DMA13_TI_BURST_LENGTH_BITS 15:12
GP_FSEL2_FSEL27_MSB 23
A2W_PLLC_ANA_STAT_DATA_MSB 11
A2W_PLLB_ANA_SSCLR 0x7e102af0:RW
DMA5_DEBUG_DMA_ID_SET 0x0000ff00
SYSAC_ISP_PRIORITY_PRIORITY_RESET 0x0
TXP_CTRL_VSTART_AT_EOF_SET 0x00008000
CM_CAM1CTL_ENAB_CLR 0xffffffef
A2W_SMPS_CTLC1R_RESET 0000000000
CCP2TX_TS_IEB_BITS 1:1
A2W_PLLB_SP0R_RESET 0x00000100
A2W_PLLB_CTRL_PRSTN_CLR 0xfffdffff
L1_D_CONTROL_DC_EN_STATS_SET 0x00000008
SD_DQLCRC3_RISE_LSB 16
MPHI_CTRL_REQ_SOFT_RST_MSB 16
EMMC_IRPT_MASK_BOOTACK_BITS 13:13
HDMI_SCHEDULER_CONTROL_ALWS_REKEY_KEEPOUT_SET 0x00000010
DMA1_TI_DEST_IGNORE_LSB 7
CM_TD0CTL_ENAB_MSB 4
CM_PCMCTL_MASH_BITS 10:9
SD_DMRCRC1_HIGH_SET 0xffff0000
EMMC_CONTROL2_TUNEON_SET 0x00400000
I2CC_INTR (1 << 10)
OTP_CONTROL_SIZE_IN_ROWS 1
CM_SDCCTL_FRAC_BITS 9:9
ASB_ISP_S_CTRL_CLR_ACK_LSB 1
DMA4_NEXTCONBK_WIDTH 32
MPHI_AXIPRIV 0x7e006040:RW
SLIM_DCC1_STAT_RESET 0000000000
AVE_OUT_CTRL_COEFF_IRQ_EN_MSB 1
USB_GINTMSK_GOUT_NAK_EFF_RESET 0x0
EMMC_HWMAXAMP0_AMP_30V_MSB 15
DMA15_TI_TDMODE_CLR 0xfffffffd
MS_SEMA_12_WIDTH 1
DMA3_TI_NO_WIDE_BURSTS_SET 0x04000000
HDMI_FIFO_CTL_VB_CNT_SET 0x00000f00
INTERRUPT_SW_NUM (32)
SMI_DSR1_RDREQ_SET 0x00000080
PM_PADS3_SLEW_BITS 4:4
HDMI_FIFO_CTL_ON_VB_CLR 0xffffff7f
MS_SEMA_7_WIDTH 1
DMA13_TI_DEST_IGNORE_LSB 7
HD_CSC_CTL_RESET 0000000000
USB_GINTMSK_GIN_N_NAK_EFF_BITS 6:6
I2C_SPI_SLV_FR_TXFE_SET 0x00000010
DMA10_DEBUG_LITE_BITS 28:28
DMA12_CS_ERROR_BITS 8:8
DMA15_TI_SRC_WIDTH_CLR 0xfffffdff
PWM_STA_GAPO2_BITS 5:5
PM_HDMI_MASK 0x000fffff
EMMC_FORCE_IRPT 0x7e300050:RW
HDMI_RAM_PACKET_8_8_MASK 0xffffffff
EMMC_INTERRUPT_CBAD_ERR_SET 0x00080000
A2W_SMPS_A_MODER_MASK 0x00000001
SYSAC_DUMMY_STATUS_IDLE_SET 0x00000001
CM_EMMCCTL_SRC_LSB 0
HDMI_RAM_PACKET_2_7_MASK 0xffffffff
TB_PRINTER_CTRL_TASKNO_SET 0x0000fff0
A2W_PLLC_ANA_SSCS_MASK 0x0001ffff
SD_STALL 0x7ee000a0:RW
GP_PUDCLK0_PUDCLKn0_BITS 31:0
DMA_INT_STATUS_INT5_MSB 5
DMA11_NEXTCONBK_ADDR_LSB 5
I2C_SPI_SLV_DR_TXDMAPREQ_BITS 10:10
AVE_IN_STATUS_FRAME_RATE_CLR 0xfffffcff
USB_DOEPINT0_OUT_PKT_ERR_RESET 0x0
A2W_PLLB_ANA1_MASK 0x00ffffff
SLIM_DCC1_PA0_RESET 0000000000
MS_SEMA_18 0x7e000048:RW
CAM0_CAMIDCA_WIDTH 32
PM_CAM0_LDOLPEN_CLR 0xfffffffd
PM_AVS_STAT_ALERT_SYSTEM_A_SET 0x00000002
IDCMDIDU 0x10002004:RW
CM_PCMCTL_MASH_SET 0x00000600
D1CACHE_BASE 0xffffffff:RW
CAM1_CAMDAT1 0x7e80101c:RW
CAM1_CAMDAT2 0x7e801020:RW
CAM1_CAMDAT3 0x7e801024:RW
MPHI_HSINDCF_EMPTY_SET 0x80000000
EMMC_INTERRUPT_CARD_BITS 8:8
DMA1_TI_DEST_DREQ_CLR 0xffffffbf
TXP_DIM_WIDTH_RESET 0x0
DMA12_TI_DEST_INC_CLR 0xffffffef
CM_PLLD_WIDTH 10
CM_PCMDIV_DIV_LSB 0
SD_DQRCRC5_RISE_LSB 16
A2W_PLLD_ANA_SSCSR_MASK 0x0001ffff
AVE_IN_STATUS_CURRENT_BUF_CLR 0xfffdffff
A2W_PLLB_ANA_STATR_RESET 0000000000
CM_TSENSCTL_SRC_LSB 0
CM_CKSM_STATE_LSB 0
USB_GPVNDCTL_CTRL_UTMI_RESET 0x0
DMA3_CS_DREQ_LSB 3
MS_SEMA_7_MASK_MSB 0
SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_LSB 2
USB_GI2CCTL_SUSP_CTL_MSB 25
PWM_CTL_SBIT4_BITS 27:27
CM_OTPDIV_RESET 0x00004000
DMA1_TI_TDMODE_LSB 1
SH_CMD_WRITE_CMD_LSB 7
EMMC_INTERRUPT_CEND_ERR_CLR 0xfffbffff
SMI_DSW0_WSWAP_SET 0x00400000
EMMC_BUS_CTRL 0x7e3000e0:RW
SCALER_DISPPROF_MASK 0xffffffff
APERF0_GEN_CTRL_RESET_MSB 1
CM_ISPCTL_BUSY_CLR 0xffffff7f
DMA6_TI_WAITS_BITS 25:21
V3D_PCTR3_MASK 0xffffffff
GP_PUDCLK0_WIDTH 32
DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
DMA_INT_STATUS_WIDTH 16
CCP2TX_TAC_DLAC_SET 0x0000ff00
HDMI_VERTB1_MANUAL_VBP1_BITS 8:8
PWMDMAC_DREQ 0
DMA3_CS_RESET_SET 0x80000000
MS_ICCLR_1_MASK 0x00000001
A2W_XOSC_CTRL_HDMIOK_MSB 13
USB_HCCHAR0_CH_DIS_CLR 0xbfffffff
DMA12_CONBLK_AD_WIDTH 32
DSI0_PHYC_clane_hsen_sync_CLR 0xfffffeff
SLIM_DCC3_PROT_RESET 0x000093a0
A2W_PLLA_CCP2_DIV_MSB 7
DMA3_STRIDE_D_STRIDE_CLR 0x0000ffff
USB_DOEPDMAB6_MASK 0xffffffff
PM_CAM0_CTRLEN_CLR 0xfffffffe
GP_FSEL2_FSEL23_LSB 9
DMA6_CONBLK_AD 0x7e007604:RW
PM_GNRIC_ENAB_BITS 12:12
PCM_INTSTC_A 0x7e20301c:RW
CM_TDCLKEN_PLLADIV2_MSB 4
EMMC_IRPT_EN_INT_C_LSB 11
HDCP_BASE 0x7e809000
PIARBCTL_CAM_THRESHOLD_SET 0x00000030
INTERRUPT_CSI2 ((64) + 39 )
DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
PIARBCTL_CAM_CHANNEL_INIBIT_CLR 0xffff00ff
USB_DIEPINT0_IN_EP_NAK_EFF_RESET 0x0
CM_TD0DIV_DIV_CLR 0xff000000
HDMI_HDCP_KEY_2_RESET 0000000000
UART_MCR 0x7e201010:RW
SCALER_DISPLSTAT_MASK 0xffffffff
DMA5_DEBUG_RESET 0000000000
MPHI_OUTDS_HANDLE_LSB 21
USB_DOEPINT0_OUT_PKT_ERR_MSB 8
USB_GHWCFG1 0x7e980044:RW
USB_GUSBCFG_CORRUPT_TX_LSB 31
USB_GHWCFG3 0x7e98004c:RW
USB_GHWCFG4 0x7e980050:RW
DMA10_TI_SRC_WIDTH_MSB 9
A2W_PLLC_ANA_SCTLR_RESET 0000000000
HDMI_RAM_GCP_0_WIDTH 32
CM_TD0CTL_KILL_CLR 0xffffffdf
SH_HBCT_BYTECOUNT_LSB 0
L1_L1_SANDBOX_START4_CTRL_CLR 0xfffffffe
SH_EDM_STATE_MACHINE_BITS 3:0
USB_DIEPCTL0_SET_D0_PID_SET 0x10000000
DMA3_DEBUG_VERSION_LSB 25
GP_AJBTDI 0x7e2000c8:RW
DMA3_DEBUG_DMA_STATE_MSB 24
EMMC_CONTROL0_GAP_STOP_SET 0x00010000
GP_AJBTDO 0x7e2000cc:RW
DMA7_TXFR_LEN_WIDTH 16
DMA14_TXFR_LEN_XLENGTH_MSB 15
MPHI_CTRL_ENABLE_CLR 0x7fffffff
USB_GINTMSK_INCOMPL_ISO_OUT_CLR 0xffdfffff
USB_DIEPCTL0_STALL_CLR 0xffdfffff
I2C1_DLEN_WIDTH 16
MPHI_C0INDDB_TENDINT_CLR 0xdfffffff
USB_GUSBCFG_FORCE_DEV_MODE_CLR 0xbfffffff
DMA15_DEBUG_DMA_ID_SET 0x0000ff00
CM_DSI1ECTL_KILL_LSB 5
PCM_CS_A_RXF_LSB 22
A2W_PLLD_MULTI_RESET 0000000000
DSI_RX2_PKTH 0x7e209000 + 0x10:RW
CM_TD0CTL_SRC_BITS 3:0
SD_DESCRIPTION "SDRAM"
USB_DOEPCTL0_SET_D1_PID_LSB 29
DMA8_CS_PANIC_PRIORITY_MSB 23
USB_DIEPCTL0_SET_ODD_FR_LSB 29
DMA10_TI_DEST_IGNORE_BITS 7:7
APERF0_BW1_RTRANS_WIDTH 32
HD_VID_CTL_VPOL_LSB 28
PM_RSTC 0x7e10001c:RW
DMA8_DEBUG_READ_ERROR_SET 0x00000004
DMA9_TI_DEST_DREQ_SET 0x00000040
SMI_D_WIDTH 32
SDSC 0x7ee0000c:RW
EMMC_STATUS_DAT_INHIBIT_MSB 1
DMA0_TI_SRC_WIDTH_SET 0x00000200
PM_RSTS 0x7e100020:RW
DMA11_CS_ABORT_CLR 0xbfffffff
HDMI_READ_POINTERS_DRFT_OVERFLOW_BITS 19:19
SMIA 0x7e600000 + 0x08:RW
SMID 0x7e600000 + 0x0C:RW
HD_HDM_CTL_RFSTBY_CLR 0xffffff3f
DMA2_CS_PAUSED_CLR 0xffffffef
SMIL 0x7e600000 + 0x04:RW
CAM0_CAMIDPO_WIDTH 32
TB_JTB_CONFIG_TDO_RISE_SET 0x00000400
CM_BURSTCTL_ENAB_CLR 0xffffffef
OTP_CODE_SIGNING_PARITY_ROW ((((((((((8 +4)+4)+1)+1)+1)+4)+4)+1)+4)+4)
DMA8_SOURCE_AD_WIDTH 32
I2C_SPI_SLV_DR_RESET 0x00120000
CGMSAE_BOT_CONTROL 0x7e806048:RW
TB_PRINTER_CTRL_TASKNO_MSB 15
VCE_PC_PF0 0x7f000000 + 0x140008:RW
CM_DSI0ECTL_BUSYD_SET 0x00000100
MS_SEMA_12 0x7e000030:RW
AVE_IN_CURRENT_LINE_NUM_INTERLACED_LSB 30
CM_GP1CTL_ENAB_SET 0x00000010
SMI_CS_EDREQ_SET 0x00008000
CCP2TX_TAC_BPD_CLR 0xfffffffb
PM_GRAFX_MRDONE_CLR 0xffffffef
CM_PERIACTL_GATE_BITS 6:6
PM_IMAGE_H264RSTN_LSB 7
DMA13_DEBUG_LITE_SET 0x10000000
EMMC_CONTROL0_BOOT_EN_CLR 0xffdfffff
USB_DCFG_EP_MIS_CNT_RESET 0x0
GP_FSEL3_FSEL31_BITS 5:3
MPHI_CTRL_HATVAL_SET 0x00000001
MS_MBOX_0_MASK 0xffffffff
DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
DMA7_TI_DEST_DREQ_BITS 6:6
DSI1_PHYC_RESET 0000000000
SD_SECEND0_ADDR_LS_RESET 0xfff
USB_GINTMSK_SOF_LSB 3
APERF0_BW2_RPEND_MASK 0x000000ff
CM_VECDIV_DIV_BITS 15:12
MPHI_OUTDDB_LENGTH_LSB 0
PM_AUDIO_RSTN_CLR 0xffdfffff
CM_TD1CTL_STEP_SET 0x00001000
L1_IC1_BP_MISSES_MASK 0000000000
GP_FSEL2_FSEL23_BITS 11:9
MS_SEMA_11_MASK_BITS 0:0
PIXELVALVE2_VSYNCD_EVEN_MASK 0x0001ffff
SYSAC_V3D_LIMITER_ENABLE_LSB 0
A2W_XOSC_PWR_RSTB_MSB 2
PCM_CS_A_TXW_MSB 17
AVE_OUT_CTRL_MASK 0xc0fff13f
A2W_SMPS_C_CLK_TDEN_BITS 3:3
SD_DQRCRC15 0x7ee00148:RO
CGMSAE_TOP_CONTROL 0x7e806044:RW
CAM1_CAMDAT0_MASK 0xffffffff
HDMI_READ_POINTERS_DRFT_FULL_MINUS_LSB 20
A2W_PLLD_ANA_KAIP_KI_SET 0x00000070
MS_SEMA_17 0x7e000044:RW
GP_LEV0_MASK 0xffffffff
L1_D_PRIORITY_c1_uc_priority_CLR 0xff0fffff
DMA11_TI_DEST_DREQ_CLR 0xffffffbf
MPHI_C1INDCF_EMPTY_BITS 31:31
PM_GRAFX_POWOK_MSB 1
A2W_PLLA_ANA_KAIP_WIDTH 11
SMI_DSW0_WDREQ_MSB 7
SH_HCFG_SLOW_CARD_BITS 3:3
SD_SB_REORDER_SET 0x00000080
GP_FSEL0_FSEL07_BITS 23:21
V3D_DBQGHC_MASK 0xffffffff
HDMI_CPU_SET 0x7e902344:RW
EMMC_FORCE_IRPT_CEND_ERR_BITS 18:18
HDMI_RAM_PACKET_3_4_RESET 0000000000
DMA13_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
SCALER_DISPSTAT_0 0x7e400000 + 0x48:RW
GR_SYSTEM_BASE 0x1A005000
USB_DOEPINT0_TXF_EMPTY_BITS 7:7
SD_MR_DONE_LSB 31
HDMI_READ_POINTERS_DRFT_HOLD_WR_CLR 0xff7fffff
A2W_PLLB_SP0_BYPEN_MSB 9
CM_GP2CTL_RESET 0000000000
SD_CS_STALLING_RESET 0x0
HD_CSC_CTL_PADMSB_SET 0x00000010
EMMC_FORCE_IRPT_ATA_ERR_CLR 0xdfffffff
UART_SCR 0x7e20101c:RW
GP_FSEL6_FSEL68_BITS 26:24
A2W_PLLC_DIG0R_WIDTH 24
SMI_DC_DMAP_MSB 24
GRDACFG0 0x1A005A00 + 0x20:RW
GRDACFG1 0x1A005A00 + 0x24:RW
GRDACFG2 0x1A005A00 + 0x28:RW
GRDACFG3 0x1A005A00 + 0x2C:RW
CCP2TX_TAC_APD_SET 0x00000002
L2_WR_HITS_MASK 0xffffffff
GRDACFG6 0x1A005A00 + 0x38:RW
GRDACFG7 0x1A005A00 + 0x3C:RW
A2W_PLLH_ANA_VCOR_MASK 0x00000001
A2W_PLLH_PIX_CHENB_MSB 8
SH_HSTS_BUSY_IRPT_BITS 10:10
USB_HPRT_SUSP_MSB 7
HDMI_RAM_PACKET_6_8_WIDTH 32
EMMC_HWCAP0_SLOT_TYPE_CLR 0x3fffffff
ASB_H264_M_CTRL_EMPTY_CLR 0xfffffffb
SMI_CS_DONE_CLR 0xfffffffd
SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_CLR 0xfffffff7
DMA4_CS_END_MSB 1
OTP_JTAG_DISABLE_REDUNDANT_BIT 17
SMI_FD_FLVL_BITS 13:8
EMMC_HWCAP0 0x7e300040:RW
EMMC_HWCAP1 0x7e300044:RW
ASB_ISP_S_CTRL_RCOUNT_BITS 13:4
DMA10_TI_DEST_DREQ_BITS 6:6
SD_SA_RFSH_T_LSB 16
CAM0_CAMSTA_WIDTH 32
SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_LSB 4
DMA_INT_STATUS_INT15_MSB 15
EMMC_CONTROL0_BOOT_EN_LSB 21
EMMC_TUNE_STEPS_STD_STEPS_SET 0x0000003f
APERF0_BW2_WTWAIT_WIDTH 32
AVE_IN_CURRENT_LINE_BUF1_WIDTH 32
SPI_CS_CLEAR_LSB 4
TB_PRINTER_CTRL_OFFSET_BITS 1:0
USB_GINTMSK_I2C_INT_LSB 9
VPU_ARB_CTRL_L2_ALGORITHM_LSB 6
USB_GHWCFG4_EN_B_VALID_FILTER_SET 0x00800000
PM_RSTC_WRCFG_BITS 5:4
DMA2_DEBUG_READ_ERROR_LSB 2
DMA6_CS_DISDEBUG_BITS 29:29
USB_DTHRCTL_ISO_THR_EN_CLR 0xfffffffd
SD_TMC_TSTCLK_RESET 0x0
DMA6_DEBUG_LITE_SET 0x10000000
SCALER_DISPECTRL_Y_NE_CTRL_CLR 0x0fffffff
A2W_PLLB_DIG0 0x7e1020e0:RW
USB_GHWCFG2_DFIFO_DYNAMIC_MSB 19
A2W_PLLB_DIG2 0x7e1020e8:RW
A2W_PLLB_DIG3 0x7e1020ec:RW
PCM_BASE 0x7e203000
A2W_PLLH_ANA1R_WIDTH 24
SLIM_DCC0_PROT_RESET 0x000093a0
HDMI_ENCODER_CTL_MASK 0x00000001
MPHI_OUTDS_VALID_BITS 30:30
SD_DQRCRC2_MASK 0xffffffff
HDMI_READ_POINTERS_DOMAIN_WR_ADDR_MSB 29
HDMI_RAM_PACKET_8_5_RESET 0000000000
DMA10_CS_ERROR_MSB 8
USB_GHWCFG2_DFIFO_DYNAMIC_RESET 0x0
HD_VID_CTL_CLRRGB_LSB 23
PCM_RXC_A_CH2WEX_LSB 15
TXP_CTRL_FIELD_LSB 3
USB_DOEPINT0_IN_TKN_EP_MIS_SET 0x00000020
I2C2_C_WIDTH 16
DMA2_TI_PERMAP_CLR 0xffe0ffff
DMA15_CS_END_CLR 0xfffffffd
CM_ISPCTL_BUSY_BITS 7:7
V3D_PCTRS12_WIDTH 5
USB_DTXFSTS12_WIDTH 32
GP_FSEL6_FSEL62_MSB 8
PWM_CTL_RPTL3_SET 0x00040000
A2W_SMPS_B_STAT_MASK 0x0000111f
SCALER_DISPECTRL_TWOD_SINGLE_BITS 31:25
A2W_PLLC_ANA3_WIDTH 24
SMI_DSW3_WHOLD_LSB 16
A2W_HDMI_CTL_HFEN_HFEN_CLR 0xfffffffe
USB_DOEPTSIZ0_RX_DPID_BITS 30:29
SH_HSTS_SDIO_IRPT_SET 0x00000100
USB_GGPIO_MASK 0xffffffff
MPHI_INTCTRL_IMFOFLW_LSB 8
USB_GUSBCFG_FORCE_HST_MODE_SET 0x20000000
CM_VPUCTL_RESET 0x00000041
DMA9_CS_PAUSED_LSB 4
MS_SEMA_4_MASK 0x00000001
CM_TSENSCTL_KILL_SET 0x00000020
USB_GOTGCTL_HST_NEG_SCS_RESET 0x0
APERF0_BW0_CTRL_ID_CLR 0xffffe0ff
SMI_DSW2_WFORMAT_CLR 0xff7fffff
AVE_OUT_CB_COEFF 0x7e240010:RW
ASB_ISP_S_CTRL_WIDTH 24
TH1_BASE 0x1A008000
CM_DSI0ECTL_ENAB_SET 0x00000010
ARM_0_SEMCLRDBG (0x7E00B000 +0x800)+0xE0:RW
DMA10_TI_SRC_WIDTH_SET 0x00000200
HDMI_DETECTED_VERTA1_RESET 0x002141e0
DSI1_TXPKT1_C_MASK 0xffffffff
SD_RWC_RXOVR_SET 0x00000080
SYSAC_HVSM_PRIORITY_N_PRIORITY_LSB 0
USB_HCINTMSK1_MASK 0xffffffff
V3D_FDBGR_MASK 0xffffffff
EMMC_HWCAP1_RETUNE_TMR_CLR 0xfffff0ff
ASB_V3D_S_CTRL_FULL_LSB 3
MS_MBOX_5_MBOX_MSB 31
SD_PHYC_VREF_ENB_BITS 4:4
USB_GGPIO_GPO_LSB 16
GP_HEN2_WIDTH 6
HDMI_DETECTED_VERTA0_MANUAL_VAL0_SET 0x00001fff
DMA14_TI_SRC_INC_LSB 8
FPGA_DCM_CTRL_REMOTE_EN_BITS 12:8
CM_EVENT_FGAINC_SET 0x00001000
HDMI_TX_PHY_TX_PHY_TMDS_CFG_MASK 0xffffffff
SMI_DSR2_RWIDTH_LSB 30
PWM_CTL_USEF4_BITS 29:29
DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
PCM_MODE_A_PDME_LSB 26
A2W_PLLD_ANA_VCO_RANGE_CLR 0xfffffffe
CM_EMMCCTL_FRAC_BITS 9:9
DMA3_SOURCE_AD_MASK 0xffffffff
HD_HDM_CTL_CECOVR_MSB 8
EMMC_HWCAP1_SDR50_TUNE_BITS 13:13
A2W_PLLH_PIX_BYPEN_CLR 0xfffffdff
PIXELVALVE0_HORZB_MASK 0xffffffff
DMA11_DEBUG_LITE_BITS 28:28
CM_PERIIDIV_DIV_LSB 12
USB_GAXIDEV_WIDTH 32
A2W_PLLD_DSI0_CHENB_SET 0x00000100
SD_CS_SDUP_RESET 0x0
SD_CS_STOP_SET 0x00000080
USB_DIEPINT0_TXF_EMPTY_SET 0x00000080
DMA3_TI_DEST_WIDTH_CLR 0xffffffdf
CMI_CAM1_RX2SRC_BITS 7:6
USB_DTXFSTS7_MASK 0xffffffff
L1_IC1_PRIORITY_IC1_APRIORITY3_BITS 15:12
USB_GOTGCTL_CON_ID_STS_CLR 0xfffeffff
I2C_SPI_SLV_RSR_UE_SET 0x00000002
CM_CAM1CTL_FRAC_SET 0x00000200
ASB_CPR_CTRL_CLR_REQ_SET 0x00000001
H264_RC 0x7f000000:RW
HD_MAI_CTL_EMPTY_BITS 10:10
USB_GINTMSK_ISO_OUT_DROP_BITS 14:14
CM_GNRICCTL_FLIP_CLR 0xfffff7ff
HD_MAI_CTL_ENABLE_CLR 0xfffffff7
V3D_BXCF_WIDTH 2
FPGA_CTRL0_TV_ACTIVITY_SET 0x00002000
DMA3_CS_END_CLR 0xfffffffd
GP_AJBTMS 0x7e2000c4:RW
GROPCTR_FBC_EZ_EVICTIONS 0x3F
CM_GP0CTL_BUSYD_BITS 8:8
USB_DIEPCTL0_SNAK_CLR 0xf7ffffff
USB_GINTMSK_INCOMPL_ISO_IN_CLR 0xffefffff
CMI_CAM0_HSSRC_SET 0x00000003
CM_VECCTL_KILL_BITS 5:5
USB_HCINT0_NAK_SET 0x00000010
MPHI_HSINDS_HANDLE_SET 0x1fe00000
A2W_XOSC_CTRL_HDMIEN_CLR 0xfffffffd
CM_TCNTCTL_SRC1_LSB 12
GRMMCT 0x1A005C00 + 0x1C:RW
CM_H264CTL_FRAC_LSB 9
A2W_HDMI_CTL_RCAL_MANR_SET 0x00000f00
DMA12_CS_ACTIVE_CLR 0xfffffffe
SMI_DSR2_RPACEALL_MSB 15
USB_DIEPDMAB2_WIDTH 32
DMA2_DEST_AD_D_ADDR_LSB 0
AVE_OUT_BLOCK_ID_MASK 0xffffffff
DMA13_TI_DEST_INC_CLR 0xffffffef
MS_SEMA_10 0x7e000028:RW
MS_SEMA_11 0x7e00002c:RW
A2W_PLLA_CCP2R_RESET 0x00000100
MS_SEMA_13 0x7e000034:RW
MS_SEMA_14 0x7e000038:RW
APHY_CSR_GLBL_ADDR_DLL_CNTRL 0x7ee0600c:RW
MS_SEMA_16 0x7e000040:RW
DMA11_SOURCE_AD_S_ADDR_CLR 0x00000000
DMA12_NEXTCONBK_MASK 0xffffffe0
MS_SEMA_19 0x7e00004c:RW
USB_GINTMSK_WK_UP_INT_RESET 0x0
MPHI_MINFS_RPTR_MSB 29
PWM_CTL_RESET 0000000000
A2W_PLLC_ANA_STATR_RESET 0000000000
PM_RSTS_HADDRF_CLR 0xfffffffd
APERF1_BW2_ATWAIT_MASK 0xffffffff
SD_DMRCRC1_MASK 0xffffffff
A2W_SMPS_CTLB2_RESET 0000000000
CM_DSI0ECTL_BUSYD_BITS 8:8
SD_MR_ADDR_MSB 7
AVE_IN_STATUS_OVERRUN_DET_BITS 0:0
DMA1_NEXTCONBK_WIDTH 32
SD_DQRCRC11_FALL_MSB 15
MULTICORE_SYNC_SEMA_MASK_10 MULTICORE_SYNC_BASE_ADDRESS + 0x28:RW
EMMC_IRPT_MASK_ADMA_ERR_MSB 25
DMA2_DEBUG_VERSION_MSB 27
USB_GAHBCFG_P_TXF_EMP_LVL_CLR 0xfffffeff
SD_DQRCRC11_WIDTH 32
USB_DIEPINT0_OUT_PKT_ERR_BITS 8:8
PM_PADS6_POWOK_LSB 5
HDMI_RAM_PACKET_4_0_RESET 0000000000
USB_GNPTXSTS_TXF_SPC_AVAIL_RESET 0x0
A2W_SMPS_CTLC0 0x7e1020c0:RW
SMI_DSW3_WPACE_SET 0x00007f00
CM_TSENSCTL_SRC_MSB 1
HDMI_RAM_GCP_2_RESET 0000000000
CM_INTEN_FGAINA_CLR 0xfffffbff
MS_SEMA_20 0x7e000050:RW
MS_SEMA_21 0x7e000054:RW
MS_SEMA_22 0x7e000058:RW
MS_SEMA_23 0x7e00005c:RW
MS_SEMA_24 0x7e000060:RW
A2W_PLLC_CORE0_CHENB_CLR 0xfffffeff
MS_SEMA_26 0x7e000068:RW
MS_SEMA_27 0x7e00006c:RW
MS_SEMA_28 0x7e000070:RW
DMA0_SOURCE_AD_MASK 0xffffffff
CM_V3DCTL_BUSYD_MSB 8
SD_SECEND1_ADDR_MS_RESET 0x0
HD_CSC_CTL_MODE_BITS 3:2
MPHI_C1INDDB_MORUN_RESET 0x0
L1_L1_SANDBOX_START2_RESET 0000000000
DMA13_CONBLK_AD_WIDTH 32
CM_GP1CTL_SRC_CLR 0xfffffff0
A2W_SMPS_CTLC1 0x7e1020c4:RW
CM_PLLC_LOADCORE2_SET 0x00000010
CM_DSI0ECTL_SRC_CLR 0xfffffff0
I2C_SPI_SLV_CR_I2C_BITS 2:2
DSI1_PHY_AFEC1_MASK 0xffffffff
SMI_CS_PXLDAT_LSB 14
DMA9_TI_PERMAP_LSB 16
DMA4_TI_SRC_WIDTH_MSB 9
CAM0_CAMICTL_RESET 0000000000
A2W_PLLH_FRAC_MASK 0x000fffff
ARM_C0_BOOTHI 0x00000010
HD_VID_CTL_EMPRGB_CLR 0xfff7ffff
DMA0_TI_TDMODE_MSB 1
CM_AVEOCTL_FRAC_SET 0x00000200
GP_HEN0_HENn0_BITS 31:0
SMI_DSR3_RSTROBE_BITS 6:0
MPHI_HSINDCF_HANDLE_MSB 27
DMA0_CS_DREQ_STOPS_DMA_LSB 5
APHY_CSR_DDR_PLL_LOCK_STATUS 0x7ee06048:RW
MS_SEMA_30 0x7e000078:RW
MS_SEMA_31 0x7e00007c:RW
CM_AVEOCTL_WIDTH 10
HD_CSC_34_33 0x7e808058:RW
TB_TASK_STATUS_WIDTH 32
CM_SDCCTL_CTRL_LSB 12
PM_SMPS_RESET 0000000000
DMA8_TI_BURST_LENGTH_BITS 15:12
MPHI_OUTDDB_HANDLE_CLR 0xf00fffff
USB_DOEPTSIZ7_WIDTH 32
CM_INTEN_LOSSA_LSB 5
A2W_PLLD_ANA_SCTLR_RESET 0000000000
USB_GRXSTSP_HST_DPID_CLR 0xfffe7fff
USB_DCTL_CGOUT_NAK_BITS 10:10
HDMI_PERT_DATA_WIDTH 24
PM_SPAREW_MASK 0x00ffffff
SD_DQRCRC12_RISE_CLR 0x0000ffff
USB_HCTSIZ3_WIDTH 32
SD_DQRCRC15_RISE_LSB 16
I2C_SPI_SLV_DMACR_RXDMAE_MSB 0
OTP_JTAG_DEBUG_KEY_PARITY_START_BIT 0
A2W_SMPS_CTLB2R_RESET 0000000000
USB_DIEPCTL0_MPS_LSB 0
A2W_PLLD_CTRL_PDIV_CLR 0xffff8fff
MS_SEMA_12_MASK_LSB 0
PM_CCP2TX_CTRLEN_BITS 0:0
CAM0_CAMDBSA1_RESET 0000000000
SLIM_DCC6_CON_RESET 0000000000
SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_MSB 15
PM_DSI1_LDOLPEN_BITS 1:1
DMA4_CONBLK_AD_SCB_ADDR_BITS 31:5
GP_AREN1_MASK 0xffffffff
SYSAC_L2_ARBITER_CONTROL_THRESHOLD_SET 0x00000030
DMA11_DEBUG_DMA_STATE_MSB 24
A2W_PLLA_ANA_KAIP 0x7e102310:RW
AVE_IN_CTRL_BUF_SER_IRQ_EN_LSB 3
USB_DIEPTSIZ0_SUP_CNT_MSB 30
A2W_SMPS_L_SIV_VOLTS_BITS 4:0
SLIM_DCC2_CON_MASK 0xffff0070
EMMC_HWCAP0_RESUME_SET 0x00800000
SMI_DSW0_WPACEALL_SET 0x00008000
USB_GRXSTSP_DEV_FN_BITS 24:21
CMI_CAM1_RX1SRC_SET 0x00000030
PM_IMAGE_PERIRSTN_LSB 6
SMI_CS_INTR_RESET 0x0
SCALER_DISPECTRL_POSTED_STATUS_SET 0x00007000
CM_TIMERCTL_SRC_CLR 0xfffffffc
HDMI_MAI_CONFIG_WIDTH 28
DMA5_NEXTCONBK_MASK 0xffffffe0
A2W_SMPS_C_CLK_MASK 0x0000000f
DMA14_DEBUG_FIFO_ERROR_LSB 1
EMMC_FORCE_IRPT_ADMA_ERR_CLR 0xfdffffff
CAM1_CAMSTA_RESET 0000000000
PM_RSTC_DRCFG_MSB 1
PCM_MODE_A_CLKM_MSB 23
I2C_SPI_SLV_DR_TXDMAPREQ_LSB 10
V3D_CT0CS_WIDTH 32
USB_DTXFSTS6_MASK 0xffffffff
SCALER_DISPSTAT_DMA_ERR_BIT0_SET 0xffffc000
DMA6_TI_SRC_DREQ_CLR 0xfffffbff
A2W_PLLB_ANA_SSCSR_MASK 0x0001ffff
USB_DAINT_OUT_EP_INT_MSB 31
CM_VPUCTL_FRAC_SET 0x00000200
A2W_PLLC_CORE1_DIV_BITS 7:0
DMA9_SOURCE_AD_WIDTH 32
USB_HCINT0_XFER_COMPL_BITS 0:0
HDMI_RAM_PACKET_8_3_WIDTH 32
A2W_PLLH_CTRL_NDIV_MSB 7
CM_GP2CTL_FRAC_CLR 0xfffffdff
DMA14_CS_RESET_BITS 31:31
DMA10_CS_WIDTH 32
V3D_PCTRS15_MASK 0x0000001f
CM_DFTCTL_BUSY_SET 0x00000080
CAM1_CAMCMP1_WIDTH 32
DMA1_TI_DEST_WIDTH_SET 0x00000020
A2W_PLLC_ANA_VCO_RANGE_SET 0x00000001
USB_DOEPDMAB0_MASK 0xffffffff
DMA3_TI_WAITS_CLR 0xfc1fffff
I2C2_DIV_MASK 0x0000ffff
USB_GRXSTSP_DEV_EP_NUM_BITS 3:0
CM_ISPCTL_ENAB_SET 0x00000010
SH_HBLC_BLOCKCOUNT_MSB 8
EMMC_CMDTM_TM_BLKCNT_EN_BITS 1:1
DMA_ENABLE_EN12_SET 0x00001000
HDMI_RAM_PACKET_4_5_WIDTH 32
DMA13_CS_ABORT_BITS 30:30
V3D_SQCNTL 0x7ec00000 +0x0418:RW
CAM1_CAMDLT_MASK 0xffffffff
MPHI_RXAXICFG_RXNPRIO_BITS 3:0
CM_TD0DIV 0x7e1010d4:RW
USB_DIEPDMAB11_WIDTH 32
TB_BOOT_SECURE_MODE_JTAG_SECURE_MSB 1
EMMC_IRPT_EN_DEND_ERR_LSB 22
I2C_SPI_SLV_VCSTAT_WIDTH 4
USB_DSTS_SUSP_STS_CLR 0xfffffffe
CAM1_CAMIBWP 0x7e80111c:RW
INTERRUPT_PIXELVALVE0 ((64) + 44 )
INTERRUPT_PIXELVALVE1 ((64) + 42 )
DMA13_TI_INTEN_SET 0x00000001
A2W_PLLC_ANA_SCTL_UPDATE_LSB 3
CM_TD1CTL_SRC_SET 0x0000000f
A2W_PLLB_ANA_STAT_DATA_SET 0x00000fff
PM_PXBG_CTRL_MSB 15
ARM_1_BELL0 (0x7E00B000 +0x900)+0x40:RW
EMMC_CONTROL0_WAKE_ONINS_EN_BITS 25:25
CM_DFTCTL_ENAB_BITS 4:4
SLIM_DCC3_PA0_WIDTH 24
UART_MSR 0x7e201018:RW
USB_GUSBCFG_SRP_CAP_MSB 8
SH_DATA_DATA_BITS 31:0
A2W_XOSC0R_MASK 0x00ffffff
GROPCTR_FBC_CZ_FE_DISCARDED 0x2E
EMMC_CONTROL0_SPI_MODE_SET 0x00100000
DMA0_CS_PRIORITY_SET 0x000f0000
APERF1_BW0_WTRANS 0x7ee08050:RO
SD_DQLCRC9_FALL_RESET 0x0
USB_DIEPINT0_SETUP_MSB 3
A2W_XOSC_PWR_RSTB_SET 0x00000004
A2W_PLLH_ANA_KAIP_MASK 0x0000077f
DMA7_CS_PRIORITY_CLR 0xfff0ffff
APERF1_BW2_CTRL_BUS_BITS 4:0
CMI_CAM1 0x7e802004:RW
MPHI_HSINDS_HANDLE_RESET 0x0
DMA4_CS_WIDTH 32
USB_HCCHAR7 0x7e9805e0:RW
SD_DQLCRC3_FALL_LSB 0
SYSAC_SRC_ARBITER_CONTROL_WIDTH 16
AVE_OUT_BASE 0x7e240000
CM_PLLTCNT2_RESET 0000000000
CM_TCNTCTL_SRC0_BITS 3:0
ARM_1_BELL3 (0x7E00B000 +0x900)+0x4C:RW
CM_CAM1CTL_BUSYD_CLR 0xfffffeff
PWM_DMAC_DREQ_CLR 0xffffff00
PWM_CTL_USEF1_LSB 5
AVE_OUT_STATUS_HSYNC_CLR 0xffffffbf
DMA15_STRIDE_S_STRIDE_CLR 0xffff0000
AVE_OUT_CR_COEFF_GREEN_COEFF_LSB 10
DMA1_TXFR_LEN_XLENGTH_MSB 15
TB_PRINTER_CTRL_OFFSET_SET 0x00000003
CM_PLLC_LOADPER_CLR 0xffffffbf
EMMC_FORCE_IRPT_SDOFF_ERR_MSB 23
DMA7_CONBLK_AD_SCB_ADDR_LSB 5
AVE_OUT_CTRL_BYTE_SWAP_MSB 23
TE0C TECTL_BASE_ADDRESS + 0x00:RW
SH_HSTS_BUSY_IRPT_CLR 0xfffffbff
IC0_C_RESET 0000000000
GP_FSEL1_FSEL10_MSB 2
DMA9_DEBUG_DMA_STATE_BITS 24:16
DMA9_TI_WAIT_RESP_LSB 3
HDMI_RAM_PACKET_2_4_RESET 0000000000
TB_JTB_CONFIG_SBITS_CLR 0xffffffe0
EMMC_INTERRUPT_DCRC_ERR_LSB 21
USB_HCCHAR0_CH_DIS_LSB 30
HDMI_PACKET_FIFO_CTL_WIDTH 2
GP_FSEL3_FSEL31_CLR 0xffffffc7
VEC_CONFIG4_WIDTH 32
GP_FSEL6_FSEL66_BITS 20:18
CM_HSMCTL_BUSY_SET 0x00000080
SMI_DSR2_RSTROBE_MSB 6
FPGA_MB_XV3D_BUILD_NUM 0x7e20b714:RO
I2C_SPI_SLV_ICR_OEIC_LSB 3
GP_LEV2_LEVn64_LSB 0
HD_VID_CTL_HPOL_CLR 0xf7ffffff
GP_FSEL5_FSEL58_BITS 26:24
USB_GRSTCTL_INT_TKN_Q_FLSH_MSB 3
I2C_SPI_SLV_HCTRL_DATA_CLR 0xffffff00
A2W_PLLB_DIG0R 0x7e1028e0:RW
CAM1_CAMDBEA0 0x7e801208:RW
CAM1_CAMDBEA1 0x7e801314:RW
USB_DSTS_WIDTH 22
A2W_PLLD_DSI0_DIV_SET 0x000000ff
SCALER_DISPSTAT2_WIDTH 32
TE1C TECTL_BASE_ADDRESS + 0x04:RW
SD_RWC_WRTOVR_CLR 0xffff7fff
DMA11_CS_DREQ_STOPS_DMA_BITS 5:5
DMA4_CS_ERROR_MSB 8
CM_TECCTL_FRAC_MSB 9
USB_DIEPTSIZ11 0x7e980a70:RW
HDMI_RAM_GCP_1_MASK 0xffffffff
DMA14_CS_ABORT_CLR 0xbfffffff
PM_GNRIC_RSTN_LSB 6
HDMI_FIFO_CTL_USE_PLL_LOCK_LSB 4
ARM_AIS0_HAVESPAC 0x00000020
CM_PLLC_DIGRST_CLR 0xfffffdff
PCM_MODE_A_CLKI_LSB 22
DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
PIXELVALVE2_DSI_HACT_ACT 0x7e807030:RW
DMA4_CS_INT_BITS 2:2
A2W_PLLC_CORE0_CHENB_MSB 8
DSI0_PHYC_clane_hsen_sync_LSB 8
PM_AUDIO_RSTN_BITS 21:21
PM_IMAGE_MRDONE_SET 0x00000010
SLIM_DCC8_PROT_MASK 0xc001ffff
EMMC_FORCE_IRPT_ATA_ERR_BITS 29:29
USB_HCINTMSK2_WIDTH 32
CM_DPIDIV_DIV_BITS 15:4
CM_CKSM_OSC_MSB 19
A2W_SMPS_CTLB0_WIDTH 24
DMA1_STRIDE_MASK 0xffffffff
A2W_PLLB_DIG1R 0x7e1028e4:RW
A2W_PLLD_ANA_KAIP_KP_BITS 3:0
SD_DQRCRC5_FALL_LSB 0
SYSAC_ISP_PRIORITY_PRIORITY_MSB 3
A2W_XOSC_CPR_CPR1_MSB 4
I2C_SPI_SLV_DR_RXBUSY_MSB 21
L1_L1_SANDBOX_END3_RESET 0000000000
PCM_CS_A_TXSYNC_LSB 13
AVE_IN_CTRL_EN_OVERRUN_ABORT_CLR 0xffff7fff
GP_FSEL2_FSEL20_SET 0x00000007
MS_SEMA_29_MASK_MSB 0
SH_HSTS_BLOCK_IRPT_MSB 9
ARM_IRQ_ENBL2 0x7E00B000 +0x214:RW
SCALER_DISPSTAT_DMA_ERR_BIT1_BITS 31:15
EMMC_ARG2_WIDTH 32
HD_CSC_24_23_WIDTH 32
PM_RSTS_HADSRQ_LSB 8
HD_MAI_SMP 0x7e80802c:RW
TXP_CTRL_LINEAR_UTILE_MSB 7
MS_STATUS_RESET 0000000000
SD_MR_RDATA_RESET 0x0
DSI0_HSTX_TO_C_RESET 0000000000
DMA9_TI_DEST_IGNORE_MSB 7
L1_L1_SANDBOX_START0_WIDTH 30
PM_RSTS_MASK 0x00001777
USB_DIEPEMPMSK_MASK 0x0000ffff
DMA_ENABLE_EN9_CLR 0xfffffdff
A2W_PLLB_DIG2R 0x7e1028e8:RW
GPREN0 0x7e200000 + 0x4C:RW
USB_GRXSTSP_HST_PKT_STS_BITS 20:17
ASB_H264_S_CTRL_RCOUNT_SET 0x00003ff0
CM_TDCLKEN_IMAGETD_LSB 13
CM_EVENT_OCDONE_BITS 21:21
MS_ICCLR_0_ICCLR_0_MSB 0
DMA12_DEBUG_OUTSTANDING_WRITES_LSB 4
DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
SCALER_DISPCTRL_DSP1_IRQ_CTRL_CLR 0xfffff9ff
DMA11_TI_SRC_IGNORE_LSB 11
MS_SEMA_19_MASK_LSB 0
DMA0_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
PIXELVALVE_INTEN_1 0x7e207024:RW
SD_SB_INHIBIT_LA_CLR 0xfffffeff
L1_IC0_CONTROL_DISABLE_VLINE_MSB 6
SD_DQRCRC14_RISE_LSB 16
EMMC_STATUS_DAT_LEVEL0_LSB 20
DMA7_NEXTCONBK_ADDR_MSB 31
GROPCTR_FEVALIDPRIMS 0x05
SLIM_DCC_CON(n) MACRO
A2W_PLLA_ANA_STAT 0x7e102410:RW
USB_HCINT7_WIDTH 32
SLIM_DCC6_PA1_RESET 0000000000
A2W_PLLH_ANA_KAIP 0x7e102370:RW
DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
A2W_PLLH_ANA_SCTL_UPDATE_CLR 0xfffffff7
A2W_PLLB_DIG3R 0x7e1028ec:RW
USB_GINTMSK_ERLY_SUSP_MSB 10
L2CS 0x7ee01000:RW
SLIM_DCC9_CON_MASK 0xffff0070
DMA5_DEST_AD_D_ADDR_MSB 31
APERF1_BW0_CTRL_EN_CLR 0xbfffffff
A2W_XOSC_CTRL_PLLCOK_MSB 12
PCM_MODE_A_FLEN_CLR 0xfff003ff
USB_HCCHAR0_MC_EC_SET 0x00300000
DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
HDMI_FIFO_CTL_INV_CLK_XFR_MSB 3
MS_SEMA_8_MASK_CLR 0xfffffffe
AVE_OUT_STATUS_HFRONT_PORCH_SET 0x00000010
DMA12_DEBUG_LITE_BITS 28:28
I2C_SPI_SLV_TDR_RESET 0000000000
MPHI_C1INDFS_DFIFOLVL_BITS 15:0
DMA4_CS_DREQ_STOPS_DMA_LSB 5
DMA13_SOURCE_AD_S_ADDR_BITS 31:0
CMI_APB_ID 0x00636d69
EMMC_CONTROL0_WAKE_ONREM_EN_LSB 26
DMA12_CS_PANIC_PRIORITY_SET 0x00f00000
DSI1_DISP1_CTRL 0x7e70002c:RW
PIXELVALVE_INTEN_x(x) MACRO
SMI_DSR3_RSETUP_CLR 0xc0ffffff
CCP2TX_TTC_BI_CLR 0xff00ffff
A2W_PLLD_ANA_SCTL 0x7e102550:RW
USB_GUSBCFG_PHY_SEL_SET 0x00000040
CM_INTEN 0x7e10111c:RW
PM_DSI1_CTRLEN_LSB 0
MS_SEMA_27_MASK_CLR 0xfffffffe
PM_PADS5_HYST_SET 0x00000008
DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
APHY_CSR_DDR_PLL_CH0_DESKEW_CTRL 0x7ee0605c:RW
PCMCS_RXCLR (1 << 4)
PWM_STA_RERR1_SET 0x00000008
MPHI_HSINDS_DISCARD_LSB 31
DMA6_TI_SRC_WIDTH_CLR 0xfffffdff
HD_VID_CTL_FULRGB_LSB 21
CM_EVENT_GAINC_CLR 0xfffffffb
V3D_DBQSTP_MASK 0xffffffff
CM_BASE 0x7e101000
CM_TD1DIV_DIV_MSB 23
CM_VECCTL_BUSYD_BITS 8:8
TE_2TIMER 0x7e20e020:RW
AVE_IN_BUF1_ADDRESS_RESET 0000000000
USB_DCFG 0x7e980800:RW
DMA1_TI_SRC_WIDTH_BITS 9:9
A2W_PLLB_ANA_SSCL_MASK 0x003fffff
CAM0_CAMDBEA0_WIDTH 32
PCM_CS_A_EN_LSB 0
USB_GHWCFG3_TRANS_COUNT_WIDTH_MSB 3
UNICAM_IHSTA(x) MACRO
DMA7_TI_MASK 0x03fffff9
EMMC_CONTROL1_CLK_EN_CLR 0xfffffffb
CM_SLIMDIV_DIV_LSB 0
SD_SECSRT1_ADDR_MS_MSB 31
CM_TD1CTL_SRC_CLR 0xfffffff0
A2W_PLLA_ANA_KAIP_KA_CLR 0xfffff8ff
APHY_CSR_ADDR_PVT_COMP_DEBUG 0x7ee0607c:RW
VPU_ARB_CTRL_UC_DELAY_LSB 2
CSI2_RC0 CSI2_BASE_ADDRESS + 0x100:RW
CSI2_RC1 CSI2_BASE_ADDRESS + 0x200:RW
ARM_MC_IHAVESPACEIRQPEND 0x00000020
CCP2TX_TC_TIP_CLR 0xffff00ff
ARM_EH_VPU0HALT 0x00000008
DMA5_TI_SRC_IGNORE_SET 0x00000800
AVE_IN_CURRENT_LINE_NUM_MASK 0xe0000fff
SD_CS_WIDTH 25
HDMI_SCHEDULER_CONTROL_MODE_REQ_LSB 0
A2W_PLLD_ANA_STATR_RESET 0000000000
USB_DOEPDMA4_WIDTH 32
SD_DQLCRC6_FALL_RESET 0x0
DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
PWM_STA_BERR_SET 0x00000100
TB_BOOT_OPT_FAST_OPT_MSB 0
DMA6_STRIDE_D_STRIDE_BITS 31:16
AVE_IN_CTRL_HIGH_PRIORITY_CLR 0xff0fffff
DMA0_CS_ABORT_SET 0x40000000
DMA1_CS_DREQ_CLR 0xfffffff7
APERF0_BW0_CTRL_RESET_BITS 31:31
DMA2_NEXTCONBK_WIDTH 32
VCE_PROGRAM_MEM_OFFSET 0x10000
ASB_V3D_S_CTRL 0x7e00a008:RW
DMA6_SOURCE_AD_S_ADDR_LSB 0
A2W_SMPS_B_STATR_MASK 0x0000111f
SH_HSTS_CRC16_ERROR_BITS 5:5
A2W_PLLA_ANA1R_RESET 0x001d0000
A2W_SMPS_CTLA1R_RESET 0000000000
GP_LEN0_MASK 0xffffffff
SCALER_DISPBKGND2_MASK 0xffffffff
GR_TU_BASE0 0x1A005200
GR_TU_BASE1 0x1A005220
GR_TU_BASE2 0x1A005240
GR_TU_BASE3 0x1A005260
GR_TU_BASE4 0x1A005280
GR_TU_BASE5 0x1A0052A0
GR_TU_BASE6 0x1A0052C0
GR_TU_BASE7 0x1A0052E0
SYSAC_V3D_LIMITER_MAX_PRIORITY_SET 0x000000f8
CM_TECCTL_ENAB_LSB 4
GRPBCC 0x1A005600 + 0x54:RW
PM_GRAFX_V3DRSTN_BITS 6:6
USB_GHWCFG4_HSPHY_DWIDTH_RESET 0x0
USB_HCCHAR0_ODD_FRM_MSB 29
MPHI_C0INDCF_LENERR_BITS 30:30
AVE_OUT_CTRL_NTSC_PAL_IDENT_MSB 13
A2W_PLLH_PIX_WIDTH 10
UART_MCR_WIDTH 5
MS_MBOX_3_MBOX_MSB 31
DMA14_CONBLK_AD_WIDTH 32
GRDCFG 0x1A005A00 + 0x04:RW
USB_DTXFSTS0_SPC_AVAIL_CLR 0x0000ffff
CM_EVENT_FGAIND_LSB 13
USB_DPTXFSIZ9_MASK 0xffffffff
MPHI_C0INDFS_DFIFOLVL_CLR 0xffff0000
ASB_V3D_S_CTRL_CLR_REQ_BITS 0:0
CM_GP2CTL_BUSYD_MSB 8
MS_STATUS_STATUS_LSB 0
APHY_CSR_DDR_PLL_BYPASS 0x7ee06054:RW
CM_CKSM_MASK 0x003fffff
A2W_PLLA_PER_CHENB_CLR 0xfffffeff
USB_HCTSIZ0_XFER_SIZE_SET 0x0007ffff
PM_AVS_STAT_ALERT_PERI_A_SET 0x00000001
PIXELVALVE2_VERTB_EVEN 0x7e807020:RW
USB_DCFG_DESC_DMA_LSB 23
DMA2_DEBUG_LITE_CLR 0xefffffff
SMI_CS_INTD_LSB 9
CM_CKSM_AUTO_BITS 20:20
V3D_FDBGS_WIDTH 32
SD_DQLCRC11_WIDTH 32
HDMI_RAM_PACKET_6_0_WIDTH 32
CMI_USBCTL_GATE_SET 0x00000040
CCP2TX_TS_ARE_BITS 2:2
DMA11_TI_DEST_IGNORE_BITS 7:7
USB_HFIR_IN_MSB 15
SCALER_OLEDCOEF1_WIDTH 32
EMMC_IRPT_EN_BOOTACK_BITS 13:13
L1_D_CONTROL_WIDTH 4
A2W_PLLH_ANA_STATR_MASK 0x001f1fff
CM_ARMCTL_ENAB_CLR 0xffffffef
HDMI_TX_PHY_TX_PHY_RESET_CTL_WIDTH 32
SCALER_DISPLIST1 0x7e400024:RW
CM_DPICTL_KILL_BITS 5:5
A2W_PLLA_ANA_SSCS_MODE_CLR 0xfffeffff
USB_GINTSTS_MASK 0xffffffff
DMA15_CS_DISDEBUG_CLR 0xdfffffff
DMA1_TI_NO_WIDE_BURSTS_LSB 26
ASB_ISP_M_CTRL_CLR_REQ_BITS 0:0
MPHI_HSINDDB_LENGTH_SET 0x000fffff
USB_DIEPTSIZ0_RX_DPID_MSB 30
PM_WDOG_RESET 0000000000
CM_TCNTCTL_BUSY_SET 0x00000080
DMA8_TI_PERMAP_MSB 20
DMA9_DEBUG_READ_ERROR_MSB 2
DMA7_DEBUG_FIFO_ERROR_SET 0x00000002
CM_CKSM_STEP_SET 0x00200000
L1_L1_SANDBOX_PERI_BR_sandbox_bootrom_SET 0x0000001f
USB_DIEPCTL0_NAK_STS_CLR 0xfffdffff
HDMI_DETECTED_VERTB1_MANUAL_VBP1_BITS 8:8
CAM0_CAMDAT0_MASK 0xffffffff
EMMC_IRPT_MASK_CBAD_ERR_BITS 19:19
PCM_INTEN_A_TXERR_MSB 2
EMMC_HWCAP1_SPI_BLOCKMODE_CLR 0xfdffffff
DMA11_TI_INTEN_LSB 0
HDMI_HORZA_MANUAL_HPOL_LSB 13
SLIM_DCC1_PA1_WIDTH 24
L1_IC0_PRIORITY_IC0_APRIORITY0_MSB 3
MPHI_AXIPRIV_RXPROT_LSB 4
DMA0_TI_DEST_INC_LSB 4
PM_AVS_INTEN_ALERT_PERI_A_CLR 0xfffffffe
USB_GNPTXFSIZ_IN_EP_TXF0_DEP_CLR 0x0000ffff
MS_SEMA_5_MASK_MSB 0
USB_DAINT_IN_EP_INT_BITS 15:0
USB_GHWCFG2_SINGLE_POINT_LSB 5
FPGA_CTRL0 0x7e20b608:RW
APERF1_BW2_RTRANS_MASK 0xffffffff
USB_DOEPINT2_MASK 0xffffffff
DMA4_NEXTCONBK 0x7e00741c:RO
L1_D0_RD_THRUS 0x7ee0214c:RO
USB_GRXSTSR_WIDTH 32
AVE_IN_STATUS_INTERLACED_BITS 10:10
EMMC_IRPT_EN_ENDBOOT_SET 0x00004000
SH_ARG_MASK 0xffffffff
PM_RSTS_HADPOR_SET 0x00001000
DMA0_TI_SRC_DREQ_SET 0x00000400
SD_DQLCRC5_FALL_BITS 15:0
USB_GINTMSK_IEP_INT_RESET 0x0
DMA7_TI_SRC_DREQ_CLR 0xfffffbff
CCP2TX_TSC_TSM_CLR 0xfffffff0
A2W_PLLA_ANA_SSCSR_MASK 0x0001ffff
HDMI_DETECTED_VERTA0_RESET 0x002141e0
MPHI_INTCTRL_RX0DISC_SET 0x00000001
EMMC_IRPT_MASK_INT_B_CLR 0xfffffbff
FPGA_DCM_CTRL_PERI_EN_CLR 0xf0ffffff
A2W_PLLC_CTRLR_MASK 0x000373ff
DMA5_TI_DEST_DREQ_LSB 6
HD_MAI_CTL_FLUSH_BITS 9:9
SCALER_DISPSLAVE1_WIDTH 32
EMMC_HWCAP0_XMEDBUS_MSB 18
MPHI_HSINDFS_CFIFOLVL_SET 0xffff0000
MS_MBOX_6_RESET 0000000000
HDMI_RAM_PACKET_10_2 0x7e902570:RW
A2W_SMPS_C_MULTI_MASK 0000000000
CM_PLLTCNT1_RESET 0000000000
HDMI_CP_CONFIG_WIDTH 31
EMMC_INTERRUPT_DTO_ERR_LSB 20
L1_L1_SANDBOX_START6_START_ADDR_LSB 5
L1_L1_SANDBOX_END1_WIDTH 30
A2W_HDMI_CTL_RCAL 0x7e102180:RW
MPHI_AXIPRIV_TXPROT_MSB 2
PWM_CTL_MODE2_SET 0x00000200
I2C_SPI_SLV_DR 0x7e214000:RW
PM_PADS4_SPARE_CLR 0xffffffef
SH_CMD_FAIL_FLAG_CLR 0xffffbfff
CM_OTPDIV_DIV_SET 0x0001f000
PWM_CTL_MODE3_LSB 17
HDMI_RAM_PACKET_10_4 0x7e902578:RW
DMA6_TI_DEST_IGNORE_BITS 7:7
USB_DIEPDMAB11_MASK 0xffffffff
ARM_I0_BELL0 0x00000004
GRFCCFG 0x1A005400 + 0x10:RW
A2W_PLLH_ANA_STAT_RCALCODE_CLR 0xfff0ffff
PM_RSTS_HADWRF_BITS 5:5
CM_EVENT_BADPASS_MSB 18
UART_LSR_DR_BITS 0:0
A2W_XOSC_CPRR_MASK 0x00000013
SD_DQLCRC13_RISE_CLR 0x0000ffff
EMMC_IRPT_EN_DTO_ERR_LSB 20
CM_CKSM_FRCE_SET 0x0000ff00
DMA2_CS 0x7e007200:RW
EMMC_HWCAP0_HS_MSB 21
FPGA_STATUS0_SPARE_IN_MSB 31
A2W_PLLH_ANA_STAT 0x7e102660:RW
USB_DOEPCTL0_SNP_BITS 20:20
SD_CS_EN_LSB 1
DSI2_DMA (16*(1<<16))
PM_HDMI_LDOCTRL_MSB 18
UART_LSR_OE_SET 0x00000002
DMA1_CS_PRIORITY_SET 0x000f0000
SMI_DSR0_RSETUP_CLR 0xc0ffffff
CM_TDCLKEN_MPHIRDFT_LSB 10
PM_AVS_EVENT_ALERT_V3D_G_BITS 3:3
DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
DSI0_BASE 0x7e209000
DMA8_CS_PRIORITY_CLR 0xfff0ffff
HD_VID_CTL_HPOL_BITS 27:27
EMMC_CONTROL1_CLK_FREQ8_MSB 15
CM_PLLH_RESET 0x00000300
ARM_MC_OPPISEMPTYIRQPEND 0x00000040
I2C_SPI_SLV_CR_I2C_LSB 2
A2W_PLLH_ANA_KAIP_KP_MSB 3
MPHI_OUTDS_VALID_SET 0x40000000
MS_SEMA_22_MASK_MSB 0
USB_GINTMSK_USB_RST_SET 0x00001000
I2C_SPI_SLV_RSR_OE_MSB 0
USB_GINTMSK_CON_ID_STS_CHNG_RESET 0x0
UART_EN_RESET 0000000000
SD_TMC_TSTPAT_RESET 0x0
SH_VDD_MASK 0x00000001
A2W_PLLA_CTRL_NDIV_SET 0x000003ff
ARM_0_ALL_IRQS (0x7E00B000 +0x800)+0xF8:RW
I2C1_S_WIDTH 32
SD_DQLCRC1_RISE_SET 0xffff0000
DMA4_TXFR_LEN_WIDTH 30
A2W_PLLB_DIG1R_RESET 0x00004000
DMA1_DEBUG_FIFO_ERROR_LSB 1
GROPCTR_TU0_CACHE_MISSES 0x14
DMA13_CS 0x7e007d00:RW
SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_CLR 0xfffffff3
DSI0_CTRL_WIDTH 3
SD_PT1_T_INIT3_SET 0x0fffff00
CCP2TX_TAC_ARST_LSB 0
INTERRUPT_PARALLELCAMERA ((64) + 43 )
CM_V3DDIV_RESET 0000000000
EMMC_FORCE_IRPT_DCRC_ERR_BITS 21:21
CM_OSCCOUNT_NUM_CLR 0xff000000
CRYPTO_IP_DMA (19*(1<<16))
CAM1_CAMPRI_WIDTH 32
APERF1_GEN_CTRL_ENABLE_LSB 0
SLIM_DCC2_CON 0x7e210248:RW
SDCMD SDCARD_BASE + 0x00:RW
AVE_IN_STATUS_BUF1_COMPL_MSB 2
USB_DOEPTSIZ0_PKT_CNT_MSB 28
APERF1_BW0_CTRL_BUS_SET 0x0000001f
SD_DQLCRC3_FALL_RESET 0x0
PWM_DAT3_RESET 0000000000
L1_IC1_CONTROL_WIDTH 7
I2C_SPI_SLV_DR_TXFF_MSB 18
A2W_PLLC_CORE1_CHENB_SET 0x00000100
APERF0_BW1_ATRANS_RESET 0000000000
GP_REN0_WIDTH 32
OTP_WRITE_DATA_READ_REG 0x7e20f020:RW
RNG_INT_MASK_MASK 0xffffffff
A2W_PLLC_CORE2_RESET 0x00000100
AVE_IN_CURRENT_ADDRESS_RESET 0000000000
VEC_CGMSAE_BOT_DATA 0x7e806058:RW
DMA9_TI_SRC_IGNORE_BITS 11:11
VEC_WSE_RESET_WIDTH 32
GP_SET1_SETn32_LSB 0
CM_DFTCTL_RESET 0000000000
SYSAC_H264_PRIORITY 0x7e009010:RW
DMA8_CS_DREQ_STOPS_DMA_LSB 5
V3D_PCTR1 0x7ec00688:RW
V3D_PCTR2 0x7ec00690:RW
V3D_PCTR3 0x7ec00698:RW
HDMI_RAM_PACKET_9_1_MASK 0xffffffff
V3D_PCTR5 0x7ec006a8:RW
DMA4_CS_PAUSED_LSB 4
V3D_PCTR7 0x7ec006b8:RW
V3D_PCTR8 0x7ec006c0:RW
V3D_PCTR9 0x7ec006c8:RW
USB_GINTMSK_OTG_INT_CLR 0xfffffffb
APERF1_BW1_CTRL_RESET_SET 0x80000000
SD_SECSRT3_ADDR_LS_LSB 1
A2W_SMPS_B_STAT_POK_MSB 12
MS_SEMA_25 0x7e000064:RW
USB_GINTMSK_INCOMPL_P_LSB 21
CM_PULSEDIV_RESET 0x0001b000
V3D_PCTRC 0x7ec00670:RW
GP_FSEL4_FSEL46_CLR 0xffe3ffff
V3D_PCTRE 0x7ec00674:RW
A2W_PLLA_ANA_SCTL_MASK 0x0000001f
DMA13_DEBUG_FIFO_ERROR_BITS 1:1
CM_SMICTL_ENAB_BITS 4:4
GROPCTR_TU0_CACHE_REQ_STALLS 0x13
USB_DPTXFSIZ7_WIDTH 32
DMA12_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
EMMC_INTERRUPT_DTO_ERR_BITS 20:20
DSI0_HS_CLT2_MASK 0x000003fc
V3D_PCTR13_MASK 0xffffffff
CAM0_CAMCMP0 0x7e80002c:RW
DMA10_DEBUG_LITE_SET 0x10000000
I2C_SPI_SLV_TDR_DATA_CLR 0xffffff00
MPHI_C0INDCF_MASK 0xffffffff
EMMC_BLKSIZECNT_BLKCNT_MSB 31
DMA3_TI_DEST_IGNORE_LSB 7
MPHI_C1INDDB_MENDINT_MSB 30
SD_CS_RDH_IDLE_MSB 16
APERF1_BW2_WTRANS_RESET 0000000000
HDMI_DETECTED_VERTA0 0x7e902140:RW
HDMI_DETECTED_VERTA1 0x7e902148:RW
FPGA_MB_SDC_ISP_FREQ_MASK 0xffffffff
A2W_PLLH_CTRL_PRSTN_MSB 17
EMMC_IRPT_MASK_ENDBOOT_LSB 14
VCE_STATUS_NANOFLAG_POS 25
HDMI_FIFO_CTL_USE_PLL_LOCK_SET 0x00000010
A2W_PLLD_ANA_VCO 0x7e102650:RW
CM_PCMCTL_MASH_CLR 0xfffff9ff
A2W_PLLB_SP0_WIDTH 10
DMA12_TI_PERMAP_LSB 16
SMICS_RXD 29
SD_DQRCRC3_RISE_SET 0xffff0000
SMICS_RXF 31
SCALER_DISPCTRL_IRQ_EN_CLR 0xffffff80
HDMI_SCHEDULER_CONTROL_MODE_REQ_SET 0x00000001
USB_GRXSTSP_HST_BCNT_MSB 14
HDMI_CP_INTEGRITY_MASK 0xffffff03
MS_STATUS_STATUS_SET 0xffffffff
SMICS_RXR 27
L1_IC1_CONTROL 0x7ee02080:RW
OTP_PUBLIC_PARITY_ROW ((((((((((((((((8 +4)+4)+1)+1)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+4)+4)
CM_GNRICCTL_RESET 0000000000
USB_DIEPTSIZ4_MASK 0xffffffff
A2W_PLLA_ANA_SCTL_UPDATE_SET 0x00000008
SCALER_DISPCTRL_DSP2_PANIC_LSB 28
EMMC_IRPT_EN_WRITE_RDY_SET 0x00000010
TXP_CTRL_ALPHA_INVERT_LSB 12
SMI_DSW3_WSTROBE_CLR 0xffffff80
HDMI_TX_PHY_TX_PHY_CTL_0_MASK 0xffffffff
DMA10_CS_DREQ_MSB 3
DMA14_DEBUG_READ_ERROR_SET 0x00000004
AVE_OUT_CTRL 0x7e240000:RW
HDMI_DETECTED_VERTB0 0x7e902144:RW
IC1_MASK3_MASK 0x77777777
SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_LSB 6
EMMC_FORCE_IRPT_DMA_BITS 3:3
MPHI_C0INDDA_MASK 0xffffffff
IC1_FORCE0_WIDTH 32
SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_LSB 8
CM_TECCTL_SRC_SET 0x00000003
GP_FSEL3_FSEL35_SET 0x00038000
TXP_CTRL_GO_MSB 0
A2W_SMPS_L_SPA_ANA_LSB 0
PM_WDOG_TIME_LSB 0
CM_DFTCTL_BUSY_CLR 0xffffff7f
MS_SEMA_29 0x7e000074:RW
TB_TASK_RXDATA2_WIDTH 32
DMA15_TI_DEST_DREQ_LSB 6
VPU_ARB_CTRL_L2_LIMIT_CLR 0xfffffffc
AVE_IN_STATUS_HSYNC_DET_SET 0x00000020
MPHI_CTRL_EIGHTBIT_MSB 12
A2W_PLLD_DIG2 0x7e102048:RW
HD_MAI_CTL_FLUSH_LSB 9
DMA4_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
A2W_PLLB_CTRL_PWRDN_LSB 16
SD_MRT_T_MRW_MSB 8
PM_DSI0_CTRLEN_CLR 0xfffffffe
USB_GHWCFG4_EN_VBUSVALID_FILTER_SET 0x00200000
DMA9_CS_DREQ_STOPS_DMA_BITS 5:5
DMA10_CS_ACTIVE_CLR 0xfffffffe
HD_MAI_CTL_ERRORF_SET 0x00000002
GP_AREN1_WIDTH 32
DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
A2W_PLLD_ANA_KAIPR_MASK 0x0000077f
EMMC_IRPT_EN_ADMA_ERR_SET 0x02000000
CCP2TX_TAC_TPC_BITS 3:3
MPHI_MINFS_WPTR_SET 0x000ffc00
EMMC_IRPT_MASK_CTO_ERR_SET 0x00010000
DMA13_TI_BURST_LENGTH_CLR 0xffff0fff
USB_DOEPDMAB10 0x7e980b1c:RW
SD_DQRCRC12_FALL_CLR 0xffff0000
CM_PLLB_LOADARM_LSB 0
A2W_PLLB_SP0_BYPEN_SET 0x00000200
SYSAC_JPEG_PRIORITY_N_PRIORITY_CLR 0xfffffff0
CAM1_CAMDBEA0_MASK 0xffffffff
CM_GP2CTL_SRC_MSB 3
MS_SEMA_11_WIDTH 1
CCP2TX_TTC_LSC_SET 0x000000f0
USB_DOEPDMAB11 0x7e980b1c:RW
CM_TECCTL_SRC_LSB 0
USB_DIEPCTL0_DIS_RESET 0x0
USB_DIEPCTL0_DPID_MSB 16
SMI_CS_TXE_MSB 30
DMA5_TI_NO_WIDE_BURSTS_LSB 26
SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_SET 0x0000ff00
ASB_H264_S_CTRL_EMPTY_SET 0x00000004
DMA3_DEBUG_LITE_SET 0x10000000
HDMI_RAM_PACKET_10_7_MASK 0xffffffff
CM_PLLD_LOADDSI1_BITS 2:2
A2W_PLLH_CTRLR 0x7e102960:RW
MS_SEMA_23_MASK_CLR 0xfffffffe
USB_DOEPDMAB14 0x7e980b1c:RW
EMMC_CONTROL0_GAP_IEN_LSB 19
CM_SDCCTL_BUSY_MSB 7
A2W_PLLB_ANA_KAIP_KA_CLR 0xfffff8ff
DMA15_TI_DEST_INC_CLR 0xffffffef
SD_RWC_RSTMAX_BITS 31:31
GRFDIMS 0x1A005400 + 0x0C:RW
DMA1_CS_PAUSED_SET 0x00000010
SMI_DSR0_FSETUP_LSB 22
SD_RTC_MASK 0xffffffff
JMCTRL_420_MODE (0 << 14)
PCMCS_TXTHR_1_QUARTER (1 << 5)
EMMC_IRPT_EN_INT_B_CLR 0xfffffbff
PM_AVS_EVENT_ALERT_PERI_A_BITS 0:0
A2W_PLLA_ANA_SCTL_RESET 0000000000
AVE_IN_STATUS_BUF_NOT_SERV_SET 0x00000008
USB_GHWCFG4_NUM_IN_EPS_MSB 27
SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_RESET 0x0
V3D_PCTRS2_MASK 0x0000001f
EMMC_IRPT_MASK_INT_B_MSB 10
APERF0_BW1_CTRL_RESET_BITS 31:31
CM_TIMERCTL_ENAB_LSB 4
MPHI_INTSTAT_IMFOFLW_MSB 29
DMA3_NEXTCONBK_WIDTH 32
HDMI_MISC_CONTROL_MASK 0x7fffffff
USB_DOEPTSIZ10_WIDTH 32
PCM_CS_A_RXTHR_LSB 7
HDMI_READ_POINTERS_DOMAIN_HALF_FULL_SET 0x40000000
USB_HCCHAR7_WIDTH 32
CM_LOCK_LOCKB_BITS 1:1
DMA7_TI_SRC_INC_LSB 8
USB_GINTMSK_SESS_REQ_INT_CLR 0xbfffffff
CM_GP0CTL_BUSY_CLR 0xffffff7f
PCM_GRAY_EN_MSB 0
EMMC_FORCE_IRPT_OEM_ERR_CLR 0x3fffffff
PM_IMAGE_POWUP_BITS 0:0
USB_DIEPTXF7_MASK 0xffffffff
USB_DCTL 0x7e980804:RW
CM_PWMCTL_BUSY_LSB 7
AVE_IN_CTRL_BUF0_IRQ_EN_MSB 1
HDMI_DETECTED_VERTA1_MANUAL_VAL1_LSB 0
DMA15_CONBLK_AD_WIDTH 32
SH_HSTS_DATA_FLAG_CLR 0xfffffffe
EMMC_CONTROL0_ALT_BOOT_EN_SET 0x00400000
SD_DQRCRC6_WIDTH 32
AVE_OUT_CTRL_REFRESH_RATE_MSB 3
HDMI_SCHEDULER_CONTROL_MODE_REQ_BITS 0:0
USB_DOEPINT15_MASK 0xffffffff
SD_DQLCRC8_RISE_SET 0xffff0000
CM_EMMCCTL_ENAB_CLR 0xffffffef
A2W_PLLH_DIG2R_RESET 0x000000aa
CM_PCMCTL_ENAB_LSB 4
VCE_VERSION_OFFSET 0x40004
CAM0_CAMDBG1_RESET 0000000000
DMA11_TI_SRC_INC_LSB 8
TB_PCM_MASK 0xffffffff
SD_DQLCRC0_FALL_RESET 0x0
ASB_ISP_S_CTRL_FULL_CLR 0xfffffff7
SMI_DSW0_WSWAP_LSB 22
SD_CS_SDTST_BITS 5:5
HDMI_VERTA0_MANUAL_VSP0_BITS 24:20
CM_TD0CTL_KILL_LSB 5
EMMC_INTERRUPT_READ_RDY_CLR 0xffffffdf
USB_GHWCFG2_NUM_EPS_RESET 0x0
ARM_IRQ_FAST 0x7E00B000 +0x20C:RW
CM_PLLB_HOLDARM_BITS 1:1
L1_L1_SANDBOX_START1_CTRL_BITS 0:0
USB_DIEPCTL0_ENA_RESET 0x0
JDCCTRL 0x7e005000 + 0x0C:RW
A2W_PLLA_DSI0_CHENB_SET 0x00000100
EMMC_IRPT_MASK_DCRC_ERR_SET 0x00200000
A2W_PLLD_FRAC_FRAC_SET 0x000fffff
TB_JTB_CONFIG_BUSY_SET 0x80000000
DMA5_TI_INTEN_LSB 0
MS_SEMA_30_MASK_BITS 0:0
DMA5_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
USB_GHWCFG4_NUM_PERIO_EPS_CLR 0xfffffff0
USB_GHWCFG2_FSPHY_INTERFACE_BITS 9:8
CM_CCP2DIV_MASK 0x00001000
DMA6_TI_DEST_WIDTH_BITS 5:5
DSI1_PHYC 0x7e70004c:RW
SDHSTS SDCARD_BASE + 0x20:RW
PWM_DAT1_WIDTH 32
EMMC_FORCE_IRPT_CBAD_ERR_CLR 0xfff7ffff
A2W_PLLC_CTRL_PDIV_BITS 14:12
DMA15_TI_INTEN_BITS 0:0
CM_PULSECTL_BUSYD_CLR 0xfffffeff
TB_JTB_PORTEN_WIDTH 8
A2W_PLLH_AUX_BYPEN_MSB 9
L1_IC0_RD_MISSES_WIDTH 0
IS_ALIAS_NORMAL(x) MACRO
CM_DSI1PCTL_MASK 0x0000039f
PIARBCTL_CAM_DELAY_MSB 3
A2W_PLLC_CORE0_WIDTH 10
CM_INTEN_BADPASS_CLR 0xfffbffff
CM_DSI1PDIV_DIV_MSB 12
DMA13_TI_DEST_WIDTH_LSB 5
CSI2_RS0 CSI2_BASE_ADDRESS + 0x108:RW
CSI2_RS1 CSI2_BASE_ADDRESS + 0x208:RW
USB_DOEPCTL0_SET_EVEN_FR_LSB 28
L1_D0_WR_THRUS 0x7ee0215c:RO
DMA_ENABLE_EN4_CLR 0xffffffef
A2W_PLLA_ANA1R_MASK 0x00ffffff
SCALER_DISPCTRL1_WIDTH 32
SD_DMRCRC0_LOW_BITS 15:0
SMI_DSW3_WWIDTH_SET 0xc0000000
DMA1_TI_SRC_DREQ_SET 0x00000400
I2C_SPI_SLV_DR_RXDMAPREQ_CLR 0xffffefff
USB_DIEPCTL0_USB_ACT_EP_MSB 15
MULTICORE_SYNC_MBOX_0 MULTICORE_SYNC_BASE_ADDRESS + 0xA0:RW
MULTICORE_SYNC_MBOX_1 MULTICORE_SYNC_BASE_ADDRESS + 0xA4:RW
DMA8_TI_SRC_DREQ_CLR 0xfffffbff
MULTICORE_SYNC_MBOX_3 MULTICORE_SYNC_BASE_ADDRESS + 0xAC:RW
MULTICORE_SYNC_MBOX_4 MULTICORE_SYNC_BASE_ADDRESS + 0xB0:RW
MULTICORE_SYNC_MBOX_5 MULTICORE_SYNC_BASE_ADDRESS + 0xB4:RW
MULTICORE_SYNC_MBOX_6 MULTICORE_SYNC_BASE_ADDRESS + 0xB8:RW
MULTICORE_SYNC_MBOX_7 MULTICORE_SYNC_BASE_ADDRESS + 0xBC:RW
USB_DOEPINT5_WIDTH 32
MPHI_OUTDDA_WIDTH 32
CM_CCP2CTL_FRAC_MSB 9
A2W_XOSC_CTRL_PLLBEN_BITS 7:7
CM_ARMCTL_FRAC_SET 0x00000200
HDMI_SCHEDULER_CONTROL_POSTLN_AVOID_BITS 13:8
MS_SEMA_3_MASK_LSB 0
L1_L1_SANDBOX_START7_CTRL_BITS 0:0
USB_DOEPCTL0_SNAK_SET 0x08000000
DMA2_TI_DEST_WIDTH_SET 0x00000020
USB_GNPTXSTS_TX_Q_TOP_BITS 30:24
CM_CKSM_RESET 0000000000
HDMI_RAM_PACKET_4_6_RESET 0000000000
TIMER_CTRL_PERIODIC (1 << 6)
I2C0_DEL_WIDTH 32
DMA7_DEBUG_DMA_STATE_MSB 24
DMA1_CS_ERROR_CLR 0xfffffeff
A2W_SMPS_CTLC0R_RESET 0000000000
APERF1_BW0_CTRL_ID_CLR 0xffffe0ff
HD_HDM_CTL_ENABLE_LSB 0
CAM1_CAMIBLS_MASK 0xffffffff
PM_DUMMY_WIDTH 1
PIXELVALVE2_VERTA_MASK 0xffffffff
SD_SA_PGEHLDE_RESET 0x0
I2C_SPI_SLV_DEBUG2_MASK 0x00ffffff
USB_DIEPINT2_MASK 0xffffffff
DMA4_TI_SRC_INC_LSB 8
DMA8_DEBUG_DMA_STATE_SET 0x01ff0000
USB_GINTMSK_SOF_RESET 0x0
SD_MRT 0x7ee00064:RW
SD_CS_ASHDN_T_SET 0x00780000
SCALER_DISPLACT0_WIDTH 32
SYSAC_L2_ARBITER_CONTROL_ALGORITHM_SET 0x000000c0
USB_DIEPCTL0_STALL_MSB 21
ARM_2_BELLCLRDBG (0x7E00B000 +0xA00)+0xE4:RW
DMA14_TI_DEST_IGNORE_BITS 7:7
DSI0_PHY_AFEC0_RESET 0000000000
USB_DCTL_SGNP_IN_NAK_MSB 7
DMA13_CS_END_LSB 1
UART_LCR_STB_LSB 2
SD_SECEND0_ADDR_MS_RESET 0x0
L1_IC0_RAS_PUSHES_WIDTH 0
USB_DOEPDMA1_MASK 0xffffffff
PCM_MODE_A_FSI_MSB 20
DMA11_CS_PAUSED_MSB 4
L2_CONT_OFF_l2_disable_BITS 0:0
DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
SPI_CS_DMAEN_SET 0x00000100
CM_PLLD_DIGRST_MSB 9
CM_PLLA_ANARST_CLR 0xfffffeff
USB_DIEPCTL0_SET_D0_PID_RESET 0x0
DSI0_LPRX_TO_C_WIDTH 32
DMA15_TI_SRC_INC_CLR 0xfffffeff
DSI1_TA_TO_CNT_RESET 0000000000
CM_DSI1PCTL_BUSYD_MSB 8
GP_CLR1_WIDTH 32
AVE_IN_BUF0_ADDRESS_BUF0_ADDR_MSB 31
PM_PADS3_DRIVE_CLR 0xfffffff8
L1_IC0_PRIORITY_IC0_APRIORITY3_BITS 15:12
I2C1_FIFO_MASK 0x000000ff
HDMI_RAM_PACKET_7_8_MASK 0xffffffff
CM_APB_ID 0x0000636d
CM_GP1CTL_WIDTH 11
CM_EVENT_GAINB_BITS 1:1
HDMI_RAM_PACKET_1_7_MASK 0xffffffff
A2W_PLLB_ANA_KAIP_KI_LSB 4
HDMI_FIFO_CTL_ON_VB_DONE_LSB 15
PM_PXLDO_RESET 0000000000
EMMC_HWCAP0_V1_8_BITS 26:26
USB_GINTMSK_ERLY_SUSP_RESET 0x0
CM_PULSEDIV_DIV_SET 0x00fff000
CM_CAM0DIV_DIV_MSB 15
MPHI_CTRL_HATVAL_BITS 0:0
A2W_PLLD_ANA_STAT_DATA_CLR 0xfffff000
SDCYC 0x7ee00030:RO
IS_ALIAS_L1_NONALLOCATING(x) MACRO
V3D_PCTR3_WIDTH 32
A2W_PLLD_DIG3R_WIDTH 24
CM_GNRICCTL_MASH_BITS 10:9
DMA15_CS_PANIC_PRIORITY_BITS 23:20
CM_PWMCTL_KILL_MSB 5
PM_DFT_RESET 0000000000
APERF1_BW2_CTRL_ID_EN_SET 0x20000000
SMI_A_ADDR_SET 0x0000003f
USB_HCCHAR0_EP_NUM_CLR 0xffff87ff
ARM_0_MAIL0_WRT (0x7E00B000 +0x800)+0x80:RW
A2W_PLLD_ANA_SCTL_RESET_MSB 4
DMA2_NEXTCONBK_MASK 0xffffffe0
PIXELVALVE2_STAT 0x7e80702c:RW
DMA14_CS_DREQ_CLR 0xfffffff7
GP_FSEL6_FSEL60_MSB 2
GP_CLR1_MASK 0xffffffff
INTERRUPT_MULTICORESYNC0 ((64) + 12 )
INTERRUPT_MULTICORESYNC1 ((64) + 13 )
INTERRUPT_MULTICORESYNC2 ((64) + 14 )
INTERRUPT_MULTICORESYNC3 ((64) + 15 )
ARM_3_MAIL1_STA (0x7E00B000 +0xB00)+0xB8:RW
DSI1_LPRX_TO_CNT_MASK 0xffffffff
USB_DOEPTSIZ9_MASK 0xffffffff
DMA11_TXFR_LEN_XLENGTH_CLR 0xffff0000
A2W_PLLH_CTRL_PWRDN_MSB 16
MPHI_OUTDDB_CHANNEL_RESET 0x0
DMA1_CS_DISDEBUG_CLR 0xdfffffff
CM_PERIADIV_RESET 0x00001000
VPU_ARB_CTRL_UC_LIMIT_MSB 1
PCM_INTSTC_A_TXW_CLR 0xfffffffe
CCP2TX_TPC_TNP_SET 0x0000000f
USB_GUSBCFG_ULPI_EXT_VBUS_IND_CLR 0xffdfffff
AUX_SPI1_PEEK_REG (0x7E215000 +0x0CC)
HD_VID_CTL 0x7e808038:RW
SD_DQLCRC2_RISE_BITS 31:16
DMA5_TXFR_LEN_XLENGTH_CLR 0xffff0000
PM_IMAGE_ISPOW_CLR 0xfffffffb
SD_MR_TIMEOUT_CLR 0xbfffffff
DMA1_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_CLR 0xffff00ff
GRFCCV1 0x1A005400 + 0x44:RW
GRFCCV2 0x1A005400 + 0x48:RW
GRFCCV3 0x1A005400 + 0x4C:RW
GRFCCV4 0x1A005400 + 0x50:RW
GRFCCV5 0x1A005400 + 0x54:RW
GRFCCV6 0x1A005400 + 0x58:RW
GRFCCV7 0x1A005400 + 0x5C:RW
DMA_DEBUG(n) MACRO
DSI0_TST_SEL 0x7e20906c:RW
MPHI_INTSTAT_RX1MEND_CLR 0xfffffeff
DMA11_CS_ACTIVE_SET 0x00000001
CCP2TX_TAC_CLAC_SET 0x00ff0000
PCM_CS_A_MASK 0x03ffe3ff
I2C_SPI_SLV_FR_TXFE_LSB 4
CM_INTEN_LOSSC_MSB 7
PM_GNRIC_POWOK_CLR 0xfffffffd
USB_DCFG_DESC_DMA_CLR 0xff7fffff
MS_MBOX_4_RESET 0000000000
GROPCTR_PBE_FE_STALLS 0x1E
CM_SMICTL_FRAC_LSB 9
USB_DFIFO3 0x7e984000:RW
CM_EVENT_FGAINA_SET 0x00000400
MPHI_OUTDS_HANDLE_BITS 28:21
DMA8_CS_ABORT_CLR 0xbfffffff
SMI_DSW1_WIDTH 32
DMA2_DEST_AD_WIDTH 32
CM_PLLTCNT3_CNT_LSB 0
DSI1_LPRX_TO_CNT_WIDTH 32
DMA8_TI_SRC_INC_CLR 0xfffffeff
SMI_CS_TXE_BITS 30:30
HDMI_PERT_CONFIG_RESET 0000000000
SMI_DSW3_WSTROBE_SET 0x0000007f
SLIM_DCC2_CON_WIDTH 32
VCE_CONTROL 0x7f000000 + 0x140020:RW
OTP_MACROVISION_REDUNDANT_START_BIT 20
MPHI_C1INDCF_HANDLE_BITS 27:20
GP_AFEN1_AFENn32_CLR 0x00000000
USB_HPRT_CONN_STS_LSB 0
A2W_SMPS_L_SPV_VOLTS_CLR 0xffffffe0
SDRAC 0x7ee0002c:RO
CAM0_CAMIBSA0_WIDTH 32
MPHI_C1INDCF_LENGTH_RESET 0x0
CM_GP0CTL_BUSYD_SET 0x00000100
AVE_OUT_STATUS_VBACK_PORCH_MSB 8
SLIM_MC_OUT_STAT_RESET 0000000000
DMA2_TI 0x7e007208:RO
I2C_SPI_SLV_ICR_RXIC_LSB 0
SCALER_DISPECTRL_SECURE_MODE_BITS 31:31
DSI0_PHYC_txulpshs_0_sync_CLR 0xfffffffd
HDMI_RAM_PACKET_13_3_RESET 0000000000
A2W_XOSC_CTRL_PLLBOK_SET 0x00080000
PM_AVS_RSTDR_SYSTEM_A_MSB 1
L2_CONT_OFF_l2_flush_BITS 2:2
DSI1_TST_MON_RESET 0000000000
USB_GUSBCFG_CORRUPT_TX_BITS 31:31
DMA13_CS_RESET_SET 0x80000000
DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
USB_GUSBCFG_PHY_IF_SET 0x00000008
SD_DQLCRC9 0x7ee00170:RO
USB_DSTS_SOF_FN_CLR 0xffc000ff
GROPCTR_FESPMRDY 0x0C
DSI1_TXPKT_PIXD_FIFO_MASK 0xffffffff
DMA11_TI_PERMAP_MSB 20
USB_GPVNDCTL_DIS_ULPI_DRVR_LSB 31
VPU_ARB_CTRL_L2_THRESHOLD_MSB 5
USB_GAHBCFG_H_BST_LEN_CLR 0xffffffe1
DMA_TI_S_32 0
DMA1_NEXTCONBK_ADDR_LSB 5
DMA8_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
USB_GRXSTSP_DEV_BCNT_LSB 4
APERF0_BW2_CTRL_LATHALT_LSB 28
I2C_SPI_SLV_CR_EN_BITS 0:0
AVE_IN_LINE_NUM_INT_LINE_NUM_INT_CLR 0xfffff000
SMI_DSW0_WWIDTH_SET 0xc0000000
I2C_SPI_SLV_RIS_WIDTH 4
PCM_TXC_A_CH2POS_LSB 4
A2W_SMPS_B_MULTI_RESET 0000000000
I2C_SPI_SLV_DR_WIDTH 32
SH_HSTS_FIFO_ERROR_MSB 3
USB_GRXSTSR 0x7e98001c:RW
HD_CSC_14_13 0x7e808048:RW
DMA3_TXFR_LEN_YLENGTH_MSB 29
MPHI_C1INDFS_DFIFOLVL_SET 0x0000ffff
DMA13_TI 0x7e007d08:RO
USB_DOEPCTL0_SNP_SET 0x00100000
CM_EMMCCTL_RESET 0000000000
USB_GUSBCFG_CORRUPT_TX_MSB 31
CAM0_CAMIHSTA_RESET 0000000000
A2W_PLLC_CTRL_PDIV_SET 0x00007000
DMA_TI_D_INC (1<<4)
SD_DQLCRC14_FALL_BITS 15:0
SD_SA_POWSAVE_SET 0x00000001
I2CA_1 0x7e804000 + 0x0C:RW
DMA3_CS_PANIC_PRIORITY_CLR 0xff0fffff
USB_GUSBCFG_DDR_SEL_MSB 7
DMA9_TI_DEST_WIDTH_MSB 5
FPGA_MB_XC0_BUILD_NUM_MASK 0xffffffff
CCP2TX_TBA_ADDR_BITS 29:0
CCP2TX_TC_MEN_MSB 1
DMA8_TI_DEST_DREQ_SET 0x00000040
USB_GUSBCFG_IND_COMP_RESET 0x0
HDMI_READ_POINTERS_DRFT_OVERFLOW_CLR 0xfff7ffff
ASB_V3D_S_CTRL_RCOUNT_SET 0x00003ff0
TB_BOOT_OPT_SDC_BEHAV_PHY_BITS 5:5
MS_SEMA_10_MASK_SET 0x00000001
GP_LEN2_LENn64_MSB 5
MS_MBOX_4_MBOX_CLR 0x00000000
USB_DIEPTXF9_WIDTH 32
DMA6_TXFR_LEN_MASK 0x3fffffff
SCALER_DISP_LIST_STATUS 0x7e400000 + 0x2C:RW
PCM_CS_A_RXERR_CLR 0xfffeffff
USB_HCTSIZ3_MASK 0xffffffff
ASB_V3D_M_CTRL_WCOUNT_LSB 14
AVE_OUT_CB_COEFF_GREEN_COEFF_MSB 19
PM_PROC_POWUP_CLR 0xfffffffe
CM_GP0CTL_MASH_MSB 10
HDMI_VERTB1_MANUAL_VSPO1_SET 0x003ffe00
CM_INTEN_GAINC_LSB 2
USB_GUSBCFG_PHY_IF_CLR 0xfffffff7
SD_DQRCRC3_RISE_BITS 31:16
PM_PADS0_HYST_MSB 3
SD_LAC_RESET 0000000000
MS_SEMA_6_MASK_SET 0x00000001
DSI1_TXPKT_CMD_FIFO_WIDTH 8
CM_PLLC_LOADCORE0_SET 0x00000001
SD_RWC_MAXCNT_CLR 0xe0ffffff
IC0_MASK2_RESET 0000000000
SDRDC 0x7ee00024:RO
IC1_MASK3 0x7e00281c:RW
HDMI_CRP_CFG 0x7e9020a8:RW
CM_PLLA_DIGRST_MSB 9
PWM_CTL_USEF3_MSB 21
DMA8_TI_PERMAP_LSB 16
A2W_PLLC_ANA_SSCS_STEP_BITS 15:0
L1_D_PRIORITY_c1_uc_priority_BITS 23:20
DMA0_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
DMA12_DEBUG_DMA_ID_MSB 15
APERF0_BW2_CTRL_RESET_BITS 31:31
CAM0_CAMIBLS_RESET 0000000000
A2W_PLLB_ANA_SSCL_LIMIT_CLR 0xffc00000
DMA0_CS_ERROR_LSB 8
DMA15_DEBUG_DMA_STATE_BITS 24:16
CM_EMMCCTL_FRAC_CLR 0xfffffdff
GP_PUD_PUD_SET 0x00000003
SMI_DSR1_MODE68_BITS 23:23
DMA1_DEBUG_READ_ERROR_SET 0x00000004
FPGA_DCM_WR_DATA_ADDRESS_SET 0x00ff0000
GP_FSEL3_FSEL36_LSB 18
GROIDC 0x1A005000 + 8:RW
CM_PCMCTL_WIDTH 11
HDMI_CEC_CNTRL_4_WIDTH 32
IC1_WAKEUP 0x7e002834:RW
DMA5_TXFR_LEN 0x7e007514:RO
DMA7_TI_SRC_IGNORE_CLR 0xfffff7ff
USB_GI2CCTL_RW_DATA_CLR 0xffffff00
A2W_PLLC_CTRL_NDIV_CLR 0xfffffc00
EMMC_IRPT_EN_RETUNE_SET 0x00001000
L2_L2_ALIAS_EXCEPTION_RESET 0000000000
DMA12_TI_DEST_WIDTH_MSB 5
USB_GHWCFG1_MASK 0xffffffff
EMMC_STATUS_CMD_LEVEL_LSB 24
MPHI_C0INDCF_MTERM_RESET 0x0
SMI_DSR1_RPACEALL_LSB 15
SMI_DSR3_RSETUP_BITS 29:24
TXP_CTRL_POWERDOWN_SET 0x00200000
PCM_CS_A_TXCLR_CLR 0xfffffff7
DMA6_TI_WAIT_RESP_BITS 3:3
APERF1_BW1_CTRL_EN_BITS 30:30
SMI_APB_ID 0x534d4958
AVE_IN_CURRENT_LINE_NUM_INTERLACED_MSB 30
AVE_IN_SYNC_CTRL_WIDTH 8
TS_TSENSCTL_CTRL_BITS 4:2
HDMI_RAM_PACKET_13_1 0x7e9025d8:RW
USB_GAHBCFG_DMA_EN_LSB 5
HDMI_RAM_PACKET_13_3 0x7e9025e0:RW
HDMI_RAM_PACKET_13_4 0x7e9025e4:RW
HDMI_RAM_PACKET_13_5 0x7e9025e8:RW
HDMI_RAM_PACKET_13_6 0x7e9025ec:RW
HDMI_RAM_PACKET_13_7 0x7e9025f0:RW
SD_VAD_MASK 0xffffffff
JCTRL_STUFF (1 << 1)
DMA13_CS_ERROR_BITS 8:8
SD_SA_PGEHLD_IDL_LSB 15
EMMC_CONTROL2_EN_PSV_BITS 31:31
USB_GUSBCFG_ULPI_EXT_VBUS_DRV_RESET 0x0
DMA9_DEBUG_VERSION_BITS 27:25
CAM1_CAMDBSA0_WIDTH 32
DMA1_DEBUG_WIDTH 29
DMA13_TI_WAITS_CLR 0xfc1fffff
IC1_VADDR_MASK 0xfffffe00
SYSAC_HOST_PRIORITY_MASK 0x0000000f
GPFSEL0 0x7e200000 + 0x00:RW
GPFSEL1 0x7e200000 + 0x04:RW
GPFSEL2 0x7e200000 + 0x08:RW
GPFSEL3 0x7e200000 + 0x0c:RW
GPFSEL4 0x7e200000 + 0x10:RW
GPFSEL5 0x7e200000 + 0x14:RW
GPFSEL6 0x7e200000 + 0x18:RW
UART_LCR_DLAB_SET 0x00000080
A2W_PLLD_ANA_SSCS_MASK 0x0001ffff
GPSET0 0x7e200000 + 0x1C:RW
GPSET1 0x7e200000 + 0x20:RW
GPSET2 0x7e200000 + 0x24:RW
USB_DIEPINT0_IN_TKN_TXFEMP_LSB 4
DMA9_CS_DREQ_LSB 3
TE_0C_MASK 0xffffffff
ASB_H264_S_CTRL_MASK 0x00ffffff
L1_D_CONTROL_DC_EN_STATS_BITS 3:3
ASB_ISP_M_CTRL_RCOUNT_MSB 13
USB_DTXFSTS4_WIDTH 32
APERF1_BW0_ATWAIT_WIDTH 32
OTP_CODE_SIGNING_PARITY_SIZE_IN_ROWS 1
CAM0_CAMCMP0_MASK 0xffffffff
A2W_PLLD_ANA_SSCS_STEP_MSB 15
A2W_HDMI_CTL1_WIDTH 24
CCP2TX_TC_TEN_SET 0x00000001
APERF0_BW0_CTRL_LATHALT_BITS 28:28
CM_TDCLKEN_MPHIWDFT_MSB 9
CM_DPICTL_ENAB_SET 0x00000010
DMA13_TXFR_LEN 0x7e007d14:RO
L1_IC1_RD_MISSES_WIDTH 0
A2W_PLLH_ANA0R_WIDTH 24
EMMC_TUNE_STEPS_STD_STEPS_MSB 5
AUX_SPI_STAT_RXFILL 0x000F0000
PIXELVALVE2_INTEN_MASK 0x000003ff
HDMI_HORZA_RESET 0x00000280
CM_INTEN_LOSSD_MSB 8
PCM_DREQ_A 0x7e203014:RW
DPHY_CSR_DQ_PVT_COMP_STATUS 0x7ee0705c:RW
SYSAC_L2_ARBITER_CONTROL_LIMIT_CLR 0xfffffffc
CAM0_CAMDBEA0_MASK 0xffffffff
SH_RSP1_CID_CSD_LSB 0
PCM_RXC_A_CH1WEX_LSB 31
CPG_IntStatus 0x7e211004:RW
VEC_SCHPH_WIDTH 32
PM_IMAGE_ENAB_LSB 12
TS_TSENSSTAT_DATA_SET 0x000003ff
USB_GOTGINT_HST_NEG_DET_RESET 0x0
DMA2_TI_SRC_DREQ_SET 0x00000400
DMA8_CS_INT_LSB 2
UNICAM_IBLS(x) MACRO
CAM1_CAMDBG0 0x7e8010f0:RW
CAM1_CAMDBG1 0x7e8010f4:RW
DMA10_TI_SRC_IGNORE_CLR 0xfffff7ff
CAM1_CAMDBG3 0x7e8010fc:RW
EMMC_IRPT_MASK_DMA_LSB 3
UART_LCR_SBC_SET 0x00000040
APERF0_BW0_WTRANS_RESET 0000000000
SPI_CS_CSPOL_BITS 6:6
TS_TSENSCTL_REGULEN_CLR 0xfbffffff
A2W_PLLC_CORE2_DIV_BITS 7:0
DMA6_TI_BURST_LENGTH_MSB 15
PIXELVALVE0_HORZB_WIDTH 32
DMA2_TI_TDMODE_LSB 1
MS_IREQ_1_IREQ_1_BITS 31:0
SH_CMD_COMMAND_BITS 5:0
SYSAC_UC_ARBITER_CONTROL_MASK 0x0000ffff
A2W_PLLD_ANA_VCOR_RESET 0000000000
SLIM_DCC2_PA1_WIDTH 24
DMA7_TI_WAITS_BITS 25:21
SD_DMRCRC1_LOW_BITS 15:0
HDMI_RAM_PACKET_5_8_WIDTH 32
ASB_H264_S_CTRL_FULL_BITS 3:3
EMMC_IRPT_EN_BLOCK_GAP_CLR 0xfffffffb
USB_DOEPINT11 0x7e980c68:RW
MPHI_TXAXICFG_TXPPRIO_LSB 4
USB_GPVNDCTL_REG_WR_RESET 0x0
A2W_PLLD_DSI1_WIDTH 10
DMA15_DEBUG_DMA_STATE_MSB 24
I2C_SPI_SLV_DR_RXDMABREQ_CLR 0xffffdfff
A2W_PLLD_ANA2_RESET 0000000000
CCP2TX_TPC_TPT_LSB 8
A2W_PLLB_ANA_SCTL_SEL_LSB 0
CAM0_CAMDBSA0_RESET 0000000000
TXP_CTRL_FORMAT_LSB 8
SDCDIV SDCARD_BASE + 0x0C:RW
A2W_HDMI_CTL2_RESET 0x0018048e
MPHI_C1INDDA_START_LSB 0
SMI_DC_REQR_MSB 11
A2W_HDMI_CTL_HFEN_RESET 0000000000
SH_RSP0_CARD_STATUS_BITS 31:0
EMMC_CONTROL1_CLK_GENSEL_LSB 5
HDMI_RAM_PACKET_9_6_MASK 0xffffffff
A2W_SMPS_LDO1_WIDTH 24
SD_DQRCRC3_FALL_SET 0x0000ffff
USB_DIEPDMAB1 0x7e980938:RW
PM_AVS_RSTDR_H264_I_SET 0x00000004
USB_DIEPINT0_IN_TKN_EP_MIS_LSB 5
PCM_CS_A_RXSYNC_SET 0x00004000
CM_EVENT_GAINH_LSB 4
DMA4_DEBUG_DMA_ID_CLR 0xffff00ff
HDMI_RAM_PACKET_13_1_WIDTH 32
USB_GUSBCFG_ULPI_EXT_VBUS_DRV_MSB 20
A2W_XOSC_BIAS 0x7e102390:RW
HDMI_PERT_INSERT_ERR_RESET 0000000000
L1_L1_SANDBOX_START6_CTRL_LSB 0
A2W_PLLC_ANA_KAIP_KA_BITS 10:8
PWM_CTL_RPTL2_BITS 10:10
USB_DOEPINT15 0x7e980ce8:RW
SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_LSB 2
PWMSTA_EMPT1 1
AVE_OUT_CTRL_MODE_CLR 0xffffffcf
USB_VBUS_DRV_AVALID (1<<3)
DMA15_CS_ERROR_CLR 0xfffffeff
A2W_XOSC_BIASR_WIDTH 5
USB_VBUS_DRV_CHRGVBUS (1<<5)
SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_MSB 15
DMA7_TI_WAITS_MSB 25
TB_BOOT_OPT_TCL_SIM_MSB 3
PM_RSTC_SRCFG_MSB 9
OTP_PRIVATE_PARITY_ROW (((((((((((((((((((8 +4)+4)+1)+1)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+4)+4)+1)+4)+4)
CSI2_THSCKTO CSI2_BASE_ADDRESS + 0x1C:RW
GP_AFEN2_MASK 0x0000003f
CAM1_CAMICTL_MASK 0xffffffff
CM_EVENT_FLOSSC_CLR 0xfffeffff
SMI_DSR2_RPACE_BITS 14:8
AVE_IN_STATUS_LINE_NUM_HIT_BITS 4:4
USB_GINTMSK_RXF_LVL_RESET 0x0
SD_DMRCRC1_LOW_LSB 0
DMA0_CS_DISDEBUG_CLR 0xdfffffff
MS_SEMA_25_MASK_BITS 0:0
EMMC_IRPT_MASK_BOOTACK_SET 0x00002000
GPAREN0 0x7e200000 + 0x7C:RW
GPAREN1 0x7e200000 + 0x80:RW
GPAREN2 0x7e200000 + 0x84:RW
A2W_PLLA_ANA_STAT_DATA_BITS 11:0
MPHI_C1INDDB_WIDTH 32
SD_MR_WDATA_CLR 0xffff00ff
EMMC_IRPT_MASK_ACMD_ERR_MSB 24
MS_SEMA_17_MASK_SET 0x00000001
MPHI_MOUTFS 0x7e00603c:RW
ASB_H264_S_CTRL_CLR_REQ_MSB 0
ASB_H264_M_CTRL_WCOUNT_LSB 14
DMA12_SOURCE_AD_S_ADDR_LSB 0
USB_DIEPDMA1_MASK 0xffffffff
CM_TIMERCTL_ENAB_CLR 0xffffffef
L2_L2_ALIAS_EXCEPTION_ADDR 0x7ee01088:RO
GP_FSEL0_FSEL09_CLR 0xc7ffffff
DMA10_CS_END_SET 0x00000002
DMA6_TXFR_LEN_YLENGTH_MSB 29
GPPUDCLK0 0x7e200000 + 0x98:RW
GPPUDCLK2 0x7e200000 + 0xA0:RW
USB_GHWCFG4_EN_PWROPT_BITS 4:4
PIXELVALVE1_VERTB_WIDTH 32
HDMI_POSTING_MASTER_WIDTH 8
AVE_IN_STATUS_EVEN_FIELD_BITS 11:11
AVE_IN_MAX_TRANSFER_WIDTH 32
ISP_RC 0x7ea00000:RW
DMA2_TI_WAIT_RESP_LSB 3
DMA12_TI 0x7e007c08:RO
SD_PRE_WIDTH 28
USB_DOEPINT0_AHB_ERR_RESET 0x0
GR_FBC_DEBUG_ADDR_MASK 0x7F
CAM1_CAMIDPO_WIDTH 32
DMA2_CS_DISDEBUG_CLR 0xdfffffff
HDMI_RAM_PACKET_11_0_RESET 0000000000
SCALER_DISPECTRL_CB_BUSY_LSB 10
A2W_SMPS_CTLA2_RESET 0000000000
PCM_CS_A_TXON_SET 0x00000004
AUX_SPI_CNTL0_SERENBL 0x00000800
DMA11_CS_RESET_LSB 31
UART_LCR_PEN_SET 0x00000008
CM_DSI1ECTL_BUSYD_SET 0x00000100
SD_RWC_WRTOVR_BITS 15:15
SD_SECSRT1_ADDR_LS_CLR 0xffffe001
PM_PADS0 0x7e100028:RW
DMA7_CS_PANIC_PRIORITY_CLR 0xff0fffff
PM_PADS2 0x7e10002c:RW
PM_PADS3 0x7e100030:RW
PM_PADS4 0x7e100034:RW
PM_PADS5 0x7e100038:RW
PM_PADS6 0x7e10003c:RW
DMA6_TXFR_LEN_XLENGTH_LSB 0
MPHI_AXIPRIV_HSPECEN_LSB 8
IC0_MASK0_WIDTH 31
USB_DIEPINT15_WIDTH 32
ASB_V3D_M_CTRL_FULL_CLR 0xfffffff7
DMA9_CS_END_SET 0x00000002
HDMI_RAM_PACKET_3_5_MASK 0xffffffff
VEC_SOFT_RESET_WIDTH 32
USB_DOEPCTL0_EO_FR_NUM_SET 0x00010000
SMI_DSR0_RSTROBE_SET 0x0000007f
DMA14_DEBUG 0x7e007e20:RW
A2W_PLLH_PIX_DIV_SET 0x000000ff
GP_EDS0_EDSn0_CLR 0x00000000
DMA1_DEBUG_READ_ERROR_BITS 2:2
SMIDD 0x7e600000 + 0x3C:RW
SH_CMD_NO_RESPONSE_CLR 0xfffffbff
USB_HCFG_LS_PHY_CLK_SEL_MSB 1
A2W_PLLD_PER_CHENB_BITS 8:8
SD_SECEND1_ADDR_LS_RESET 0xfff
A2W_XOSC1R_WIDTH 24
USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_CLR 0xff3fffff
DPHY_CSR_GLBL_DQ_DLL_RECALIBRATE 0x7ee07008:RW
MS_STATUS_STATUS_BITS 31:0
APERF1_BW2_RPEND_RESET 0000000000
GP_FSEL6_FSEL67_LSB 21
CM_PULSECTL_SRC_LSB 0
VEC_CPS32_CPC_MASK 0xffffffff
MPHI_OUTDDB_TENDINT_SET 0x20000000
DMA15_TI_DEST_INC_SET 0x00000010
A2W_PLLD_FRACR_MASK 0x000fffff
DMA15_DEBUG_READ_ERROR_MSB 2
A2W_PLLH_ANA_STAT_CNTLENB_SET 0x00100000
SYSAC_V3D_LIMITER_HOLDOFF_MSB 0
SYSAC_SRC_ARBITER_CONTROL_DELAY_CLR 0xfffffff3
CM_LOCK_FLOCKC_CLR 0xfffffbff
SLIM_DCC8_STAT 0x7e21030c:RW
IFORCE1_0 0x7e002044:RW
MPHI_HSINDS_WIDTH 32
SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_CLR 0xffff00ff
MPHI_INTSTAT_RX0DISC_BITS 20:20
CM_GP0CTL_KILL_LSB 5
DMA4_DEBUG_VERSION_LSB 25
DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
AVE_IN_CTRL_RESET 0x08000080
CM_ARMCTL_SRC_CLR 0xfffffff0
CM_V3DCTL_ENAB_SET 0x00000010
USB_DTHRCTL_TX_THR_LEN_MSB 10
DMA7_CS_RESET_SET 0x80000000
SYSAC_HVSM_PRIORITY_P_PRIORITY_SET 0x000000f0
CM_PLLD_LOADDSI0_LSB 0
DMA1_TI_PERMAP_SET 0x001f0000
CM_CCP2DIV_DIV_BITS 12:12
AVE_OUT_STATUS_HBACK_PORCH_LSB 5
I2C_SPI_SLV_DR_TXDMABREQ_CLR 0xfffff7ff
EMMC_CONTROL2_NOTC12_ERR_SET 0x00000080
SD_DQRCRC13_FALL_BITS 15:0
SMI_CS_DONE_BITS 1:1
HDCP_KEY_ADR 0x7e809004:RW
APERF0_GEN_CTRL_ENABLE_SET 0x00000001
MPHI_CTRL_DIRECT_SET 0x00000010
EMMC_INTERRUPT_DATA_DONE_SET 0x00000002
EMMC_INTERRUPT_INT_C_CLR 0xfffff7ff
CM_SMICTL_FRAC_BITS 9:9
L1_D_CONTROL_DC1_FLUSH_SET 0x00000004
DMA3_CS_DISDEBUG_CLR 0xdfffffff
A2W_PLLH_DIG2_MASK 0x00ffffff
SD_DQLCRC11_RISE_SET 0xffff0000
PWM_CTL_MSEN4_MSB 31
UNICAM_DBSA0(x) MACRO
JHWDATA 0x7e005000 + 0x2C:RW
SD_DQLCRC8_FALL_SET 0x0000ffff
CM_PERIACTL_GATE_LSB 6
DMA1_TI_INTEN_MSB 0
AVE_IN_STATUS_VFORM_FIELD_CLR 0xffffefff
FPGA_BASE 0x7e20b600
DMA1_TXFR_LEN_WIDTH 30
DMA14_TI_DEST_WIDTH_MSB 5
MPHI_C0INDCF_LENERR_LSB 30
SCALER_DISPSTAT1_MASK 0xffffffff
PCM_CS_A_RXON_CLR 0xfffffffd
ASB_CPR_CTRL_RCOUNT_CLR 0xffffc00f
SD_SE_T_RTP_CLR 0xfffff8ff
EMMC_IRPT_EN_CBAD_ERR_SET 0x00080000
USB_GRXSTSP_HST_BCNT_RESET 0x0
USB_GAHBCFG 0x7e980008:RW
SD_SC_T_WTR_RESET 0x3
PM_XOSC_MASK 0x00000001
SD_RWC 0x7ee00080:RW
HDMI_AUDIO_PACKET_CONFIG_RESET 0x21000403
CM_DFTCTL_KILL_SET 0x00000020
MS_SEMA_23_RESET 0000000000
SD_CARCRC_MASK 0xffffffff
SMI_DSR1_MODE68_LSB 23
I2C_SPI_SLV_ICR_TXIC_BITS 1:1
PWM_CTL_RPTL2_LSB 10
SMI_DSR0_RWIDTH_LSB 30
CAM1_CAMDAT3_WIDTH 32
DMA15_DEBUG_LITE_BITS 28:28
GP_FEN0_FENn0_MSB 31
USB_HCCHAR0_EP_DIR_LSB 15
AVE_IN_FRAME_NUM_MASK 0x00000fff
HD_MAI_THR_PANICLOW_MSB 21
HDMI_FIFO_CTL_CAPTURE_POINTER_BITS 2:2
L1_IC0_RD_HITS_MASK 0000000000
USB_DIEPINT0_TIMEOUT_MSB 3
SLIM_DMA_MC_RX_WIDTH 32
SCALER_DISPSTAT_DSP1_STATUS_BITS 21:16
SPI_CS_CPHA_SET 0x00000004
SD_DQLCRC11_FALL_RESET 0x0
DMA15_DEBUG_FIFO_ERROR_CLR 0xfffffffd
V3D_BFC_MASK 0x000000ff
DMA14_DEBUG_DMA_ID_CLR 0xffff00ff
SMI_CS_ACTIVE_RESET 0x0
SH_CMD_READ_CMD_MSB 6
CM_VECDIV_RESET 0000000000
SLIM_DCC7_STAT 0x7e2102ec:RW
FPGA_CTRL0_LV_SPARE_OUT_SET 0x000c0000
CM_DFTCTL_BUSY_BITS 7:7
USB_HCCHAR0_EP_DIR_BITS 15:15
SD_SECSRT0_ADDR_MS_RESET 0x0
SH_HCFG_WIDE_INT_BUS_CLR 0xfffffffd
SMI_DSR3_FSETUP_LSB 22
AUX_MU_STAT_TXDONE 0x00000200
I2C_SPI_SLV_SLV_ADDR_CLR 0xffffff80
EMMC_CONTROL0_READWAIT_EN_CLR 0xfffbffff
A2W_PLLD_ANA_KAIP_KA_CLR 0xfffff8ff
DMA10_TI_DEST_INC_SET 0x00000010
PM_RSTS_HADSRH_CLR 0xfffffbff
HD_MAI_CTL_DLATE_BITS 15:15
EMMC_SLOTISR_VER_SLOT_STATUS_MSB 7
PM_PADS4_DRIVE_SET 0x00000007
DMA3_TI_PERMAP_CLR 0xffe0ffff
CCP2TX_TS_TXB_MSB 0
CAM1_CAMCLT_MASK 0xffffffff
CAM0_CAMDAT1 0x7e80001c:RW
CAM0_CAMDAT2 0x7e800020:RW
CAM0_CAMDAT3 0x7e800024:RW
EMMC_FORCE_IRPT_CARD_OUT_SET 0x00000080
TIMER_CTRL_DIV256 (2 << 2)
CM_PLLC_HOLDCORE1_SET 0x00000008
L1_L1_SANDBOX_START7_START_ADDR_CLR 0xc000001f
DMA9_TI_BURST_LENGTH_CLR 0xffff0fff
SH_HCFG_BLOCK_IRPT_EN_MSB 8
DMA10_DEBUG_VERSION_BITS 27:25
USB_DOEPINT0_TXF_EMPTY_SET 0x00000080
A2W_PLLD_CORE_DIV_SET 0x000000ff
DMA10_DEBUG_DMA_STATE_CLR 0xfe00ffff
PIXELVALVE0_VERTA_EVEN 0x7e20601c:RW
SD_VIN_MULT_MSB 24
AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_MSB 11
DMA5_NEXTCONBK_WIDTH 32
PCM_CS_A_RXF_MSB 22
DMA5_TI_SRC_INC_BITS 8:8
CM_SLIMCTL_ENAB_SET 0x00000010
CM_PASSWORD 0x5a000000
DMA4_DEBUG_OUTSTANDING_WRITES_BITS 7:4
DSI0_PHYC_forcehsstop_sync_CLR 0xfffffffb
PCM_MODE_A_MASK 0x1fffffff
ARM_C0_JTAGGPIO 0x00000C00
USB_DOEPINT6_WIDTH 32
DSI1_STAT_MASK 0xffffffff
SMI_DSR3_RWIDTH_BITS 31:30
CCP2TX_TTC_FSP_SET 0x00001000
HDMI_RAM_PACKET_10_5_WIDTH 32
PM_GRAFX_MEMREP_MSB 3
USB_DIEPDMA13_MASK 0xffffffff
FPGA_SCRATCH 0x7e20b604:RW
CCP2TX_TS_IEB_CLR 0xfffffffd
DMA12_TI_WAIT_RESP_LSB 3
IMASKx_0(x) MACRO
IMASKx_1(x) MACRO
CAM1_CAMDAT1_MASK 0xffffffff
USB_GHWCFG4_EN_DED_TX_FIFO_MSB 25
ASB_ISP_S_CTRL_RCOUNT_CLR 0xffffc00f
MPHI_RXAXICFG_RXNPRIO_CLR 0xfffffff0
AUX_SPI_CNTL0_CS2_N 0x00060000
CAM0_CAMIVSTA_RESET 0000000000
DMA6_TI_DEST_INC_BITS 4:4
EMMC_IRPT_EN_SDOFF_ERR_CLR 0xff7fffff
VCE_REASON_STOPPED 0x10
A2W_SMPS_C_CLK_WIDTH 4
A2W_PLLC_FRAC 0x7e102220:RW
AVE_OUT_CTRL_INVERT_CSYNC_CLR 0xfffdffff
DMA9_NEXTCONBK 0x7e00791c:RO
CM_DSI1PCTL_BUSY_MSB 7
CAM1_CAMCTL_MASK 0xffffffff
CDP_PHYTSTDAT 0x1C00E000 + 0x08:RW
DMA7_TI_WAITS_CLR 0xfc1fffff
RNG_FF_THRESHOLD_MASK 0xffffffff
OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS 4
PM_DFT 0x7e100068:RW
SH_TOUT_MASK 0xffffffff
CM_CCP2DIV_DIV_CLR 0xffffefff
ASB_H264_S_CTRL_FULL_CLR 0xfffffff7
HDMI_RAM_PACKET_CONFIG_WIDTH 17
I2C_SPI_SLV_DR_TXBUSY_SET 0x00010000
CM_DSI1ECTL_BUSY_LSB 7
A2W_PLLA_ANA_KAIPR_MASK 0x0000077f
SD_DQLCRC3_RISE_MSB 31
CM_INTEN_FGAINC_SET 0x00001000
A2W_PLLH_ANA_SCTLR_RESET 0000000000
INTERRUPT_EXCEPTION_NUM 32
DMA1_TI_DEST_IGNORE_MSB 7
A2W_PLLA_DSI0_BYPEN_BITS 9:9
DMA15_CS_RESET_BITS 31:31
HD_MAI_CTL_BUSY_SET 0x00004000
CM_HSMCTL_BUSY_BITS 7:7
HD_VID_CTL_CLRSYNC_CLR 0xfeffffff
AVE_IN_BLOCK_ID_MASK 0xffffffff
ASB_ISP_S_CTRL_CLR_ACK_MSB 1
PCM_CS_A_TXERR_LSB 15
PWM_RNG1_RESET 0x00000020
DMA6_CS_END_SET 0x00000002
SD_MR_WDATA_LSB 8
CPG_Debug0_WIDTH 32
L1_D_PRIORITY_c0_per_priority_LSB 8
USB_HCINT0_STALL_LSB 3
EMMC_EXRDFIFO_EN 0x7e300084:RW
MS_IREQ_1_IREQ_1_SET 0xffffffff
APERF1_BW2_CTRL_EN_MSB 30
ALIAS_DIRECT(x) MACRO
CM_GP1CTL_BUSYD_BITS 8:8
DMA0_DEBUG_LITE_SET 0x10000000
DMA13_TI_DEST_IGNORE_MSB 7
USB_DOEPCTL0_NAK_STS_MSB 17
GP_REN2_RENn64_SET 0x0000003f
SYSAC_V3D_LIMITER_WIDTH 12
TS_TSENSCTL_DIRECT_SET 0x00000040
SD_SB_EIGHTBANK_SET 0x00000010
PWM_CTL_MODE1_LSB 1
AVE_OUT_CTRL_PRIV_ACCESS_CLR 0xfffffeff
HDMI_DETECTED_VERTA1_MANUAL_VFP1_MSB 19
MPHI_OUTDDB_WIDTH 30
USB_DOEPCTL0_SNP_CLR 0xffefffff
A2W_PLLA_FRACR_MASK 0x000fffff
DMA13_CS_ACTIVE_CLR 0xfffffffe
DMA14_CS_DREQ_STOPS_DMA_SET 0x00000020
L1_D0_RD_HITS 0x7ee02140:RW
A2W_PLLC_FRACR_RESET 0000000000
SDRTC 0x7ee0001c:RW
SMI_DSR1_RSTROBE_BITS 6:0
PM_PXLDO_RSTOSCDR_LSB 16
DMA3_TI_SRC_DREQ_SET 0x00000400
IC1_FORCE1_CLR_WIDTH 32
DMA_ENABLE_EN11_BITS 11:11
HDMI_DETECTED_VERTA0_MANUAL_VSP0_BITS 24:20
EMMC_CONTROL1_SRST_DATA_CLR 0xfbffffff
USB_GHWCFG4_EN_A_VALID_FILTER_CLR 0xffbfffff
GP_FEN1_RESET 0000000000
ASB_V3D_M_CTRL_CLR_ACK_BITS 1:1
A2W_PLLC_ANA_VCOR 0x7e102e30:RW
USB_DIEPINT10 0x7e980a48:RW
USB_DIEPINT11 0x7e980a68:RW
USB_DIEPINT12 0x7e980a88:RW
USB_DIEPINT13 0x7e980aa8:RW
USB_DIEPINT14 0x7e980ac8:RW
USB_DIEPINT15 0x7e980ae8:RW
MPHI_INTCTRL_OMFUFLW_RESET 0x0
APERF0_BW1_WTRANS_WIDTH 32
VEC_CPS45_CPS67_MASK 0xffffffff
DSI0_PR_TO_CNT_MASK 0xffffffff
SMI_DSR0_RDREQ_SET 0x00000080
PM_PADS2_SLEW_BITS 4:4
SD_RWC_WRTVAL_SET 0x00001f00
DMA10_DEBUG_READ_ERROR_BITS 2:2
CM_DSI1ECTL_ENAB_CLR 0xffffffef
DMA2_DEBUG_DMA_STATE_BITS 24:16
USB_DIEPDMA14_MASK 0xffffffff
SLIM_DCC8_STAT_WIDTH 32
EMMC_IRPT_EN_WRITE_RDY_BITS 4:4
A2W_PLLA_ANA0R_RESET 0000000000
ST_C3_MASK 0xffffffff
A2W_XOSC_BIAS_HIGHP_SET 0x00000010
HD_HDM_CTL_RFSTBY_LSB 6
I2C_SPI_SLV_RIS_TXRIS_LSB 1
HDMI_SCHEDULER_CONTROL 0x7e9020c0:RW
SD_SECEND2_ADDR_MS_RESET 0x0
DMA_CS_END (1<<1)
CM_PCMDIV_DIV_MSB 23
SD_DQRCRC5_RISE_MSB 31
PM_RSTC_HRCFG_CLR 0xffcfffff
A2W_SMPS_L_SIV_WIDTH 5
DMA8_CS_ERROR_MSB 8
CM_CKSM_STATE_MSB 7
MPHI_C0INDFS_DFIFOLVL_RESET 0x0
DMA3_CS_DREQ_MSB 3
SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_MSB 3
APHY_CSR_ADDR_SPR1_RO 0x7ee0608c:RW
SD_PT1_T_INIT1_SET 0x000000ff
DSI0_CMD_PKTC 0x7e209004:RW
CAM1_CAMICTL_RESET 0000000000
HD_CSC_CTL_ENABLE_SET 0x00000001
USB_GRXFSIZ_GRXF_DEP_LSB 0
A2W_PLLA_ANA1_MASK 0x00ffffff
SLIM_DCC0_PA0_RESET 0000000000
DMA4_CS_MASK 0xf0ff017f
DMA1_TI_TDMODE_MSB 1
SH_CMD_WRITE_CMD_MSB 8
SMI_DSW2_WSETUP_BITS 29:24
DMA4_TI_DEST_WIDTH_CLR 0xffffffdf
EMMC_HWCAP1_SPI_MODE_BITS 24:24
SLIM_DCC0_CON 0x7e210208:RW
D0CACHE_BASE (0x7ee02000 +0x100)
DPI_C_RESET 0x00003000
V3D_IDENT1_MASK 0xffffffff
PM_CCP2TX_WIDTH 19
A2W_PLLC_CORE0_DIV_BITS 7:0
HDMI_V_WIDTH 32
SH_HCFG_WIDE_EXT_BUS_LSB 2
DMA4_CS_PRIORITY_SET 0x000f0000
DMA1_STRIDE_S_STRIDE_LSB 0
PM_AVS_INTEN_RESET 0000000000
EMMC_CONTROL0_PWCTL_HWRST_LSB 12
A2W_PLLC_CTRL_PWRDN_CLR 0xfffeffff
EMMC_DBG_SEL_WIDTH 1
VEC_CPS2021_CPS2223_MASK 0xffffffff
HDMI_TX_PHY_TX_PHY_CTL_2_WIDTH 32
MS_SEMA_25_WIDTH 1
DMA11_CONBLK_AD 0x7e007b04:RW
DMA5_SOURCE_AD_S_ADDR_SET 0xffffffff
USB_HCINT0_FRM_OVRUN_BITS 9:9
MPHI_CTRL_SOFT_RST_DNE_LSB 17
DMA0_TXFR_LEN_XLENGTH_BITS 15:0
GP_FSEL2_FSEL23_MSB 11
MPHI_INTSTAT_RX0TEND_RESET 0x0
AVE_OUT_CB_COEFF_BLUE_COEFF_LSB 0
A2W_PLLH_ANA0R_MASK 0x00ffffff
SD_VIN_ID_SET 0x0000ffff
SD_DQRCRC0 0x7ee0010c:RO
PM_GRAFX_ENAB_LSB 12
USB_DIEPINT0_BACK2BACK_SETUP_BITS 6:6
GP_FSEL4_FSEL44_CLR 0xffff8fff
USB_DPTXFSIZ10_WIDTH 32
DMA11_TI_INTEN_CLR 0xfffffffe
CM_TD1CTL_STEP_BITS 12:12
PM_RSTS_HADDRQ_BITS 0:0
HDMI_RAM_PACKET_9_6_WIDTH 32
L1_IC0_FLUSH_S_RESET 0000000000
DMA9_NEXTCONBK_ADDR_CLR 0x0000001f
MPHI_INTSTAT_RX1MEND_MSB 8
USB_DIEPTSIZ6_WIDTH 32
APERF0_BW2_CTRL_ID_EN_RESET 0x0
MPHI_C0INDCF_LENGTH_SET 0x000fffff
I2C_SPI_SLV_VCSTAT_MASK 0x0000000f
MPHI_OUTDS_HANDLE_MSB 28
DSI0_CTRL_CTRL2_SET 0x00000004
A2W_PLLH_ANA_VCOR_RESET 0000000000
SH_CMD_COMMAND_MSB 5
USB_GHWCFG3_PACKET_COUNT_WIDTH_CLR 0xffffff8f
CAM0_CAMIBLS 0x7e800118:RW
V3D_DBGE_WIDTH 32
A2W_PLLH_FRAC_FRAC_BITS 19:0
DMA7_DEST_AD_D_ADDR_CLR 0x00000000
DMA15_CONBLK_AD 0x7ee05004:RW
CM_H264CTL_BUSYD_BITS 8:8
GP_AFEN2_RESET 0000000000
PM_PADS5_HYST_MSB 3
CM_GP0CTL_SRC_CLR 0xfffffff0
I2C_SPI_SLV_IMSC_TXIM_SET 0x00000002
DMA5_CS_RESET_LSB 31
DMA3_DEBUG_VERSION_MSB 27
USB_GUSBCFG_USB_TRD_TIM_SET 0x00003c00
DMA5_CONBLK_AD 0x7e007504:RW
USB_DOEPCTL0_DIS_LSB 30
PWMCTL_SBIT(n) MACRO
DMA6_DEBUG_READ_ERROR_CLR 0xfffffffb
EMMC_IRPT_MASK_ATA_ERR_SET 0x20000000
TS_TSENSCTL_PRWDW_SET 0x00000001
DMA0_TXFR_LEN_XLENGTH_LSB 0
PM_AVS_INTEN_ALERT_SYSTEM_A_SET 0x00000002
USB_GNPTXFSIZ_NP_TXF_DEP_CLR 0x0000ffff
DMA6_CS_PRIORITY_BITS 19:16
CM_DSI1ECTL_KILL_MSB 5
DMA4_TI_DEST_IGNORE_SET 0x00000080
USB_DVBUSPULSE_PULSE_SET 0x00000fff
CAM1_CAMDBWP 0x7e80120c:RW
DMA8_TI_WAIT_RESP_LSB 3
A2W_SMPS_C_CTL_WIDTH 2
CM_PLLTCNT1_MASK 0x00ffffff
EMMC_INTERRUPT_TUNE_ERR_LSB 26
USB_DOEPCTL0_SET_D1_PID_MSB 29
APERF0_BW0_RMAX_WIDTH 24
HDMI_DETECTED_HORZB_MANUAL_HSP_LSB 10
I2C_SPI_SLV_DEBUG1_RESET 0x0000000e
USB_DIEPINT0_AHB_ERR_SET 0x00000004
EMMC_IRPT_MASK_DATA_DONE_MSB 1
HD_VID_CTL_VPOL_MSB 28
EMMC_BLKSIZECNT_BLKSIZE_MS1_MSB 15
A2W_PLLC_ANA1_WIDTH 24
USB_HPRT_TST_CTL_SET 0x0001e000
USB_GHWCFG3_VENDOR_CTL_INTERFACE_CLR 0xfffffdff
GP_FSEL3_FSEL33_SET 0x00000e00
CM_TSENSCTL_BUSY_SET 0x00000080
L1_IC1_CONTROL_DISABLE_BITS 0:0
A2W_PLLD_ANA_SCTL_UPDATE_SET 0x00000008
HDMI_RAM_PACKET_11_0_MASK 0xffffffff
SCALER_APB_ID 0x64647276
DMA1_TI_BURST_LENGTH_SET 0x0000f000
DMA2_NEXTCONBK_ADDR_SET 0xffffffe0
CM_TIMERCTL_FRAC_SET 0x00000200
HDMI_RAM_PACKET_7_5_RESET 0000000000
CM_GNRICCTL_MASH_SET 0x00000600
CM_OTPCTL_SRC_CLR 0xfffffffc
CM_PLLH_LOADAUX_BITS 1:1
L1_D_FLUSH_E 0x7ee02108:RW
I2C1_C_WIDTH 16
DMA0_DEST_AD_D_ADDR_SET 0xffffffff
INTERRUPT_SOFTINT_NUM 32
SLIM_DCC4_PROT 0x7e210290:RW
A2W_PLLD_ANA_MULTI_MASK 0000000000
L1_D_FLUSH_S 0x7ee02104:RW
I2C_SPI_SLV_DR_RXDMABREQ_SET 0x00002000
DMA14_DEBUG_WIDTH 29
DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
SD_TMC_IPSEL_BITS 6:4
HDMI_RAM_PACKET_10_1_RESET 0000000000
USB_GI2CCTL_EN_BITS 23:23
DMA14_NEXTCONBK_ADDR_SET 0xffffffe0
HDMI_RAM_PACKET_3_7_RESET 0000000000
CM_ISPCTL_KILL_LSB 5
PM_IMAGE_H264RSTN_MSB 7
DMA12_TI_SRC_INC_CLR 0xfffffeff
USB_DIEPCTL0_TYPE_RESET 0x0
AM_VP_L2_PRI 0x1800d000:RW
A2W_SMPS_CTLB0R_MASK 0x00ffffff
DMA_ENABLE_EN12_MSB 12
DMA3_CS_END_SET 0x00000002
A2W_PLLH_ANA_SCTL_RESET 0000000000
USB_GINTMSK_SOF_MSB 3
USB_GRSTCTL_TXF_FLSH_BITS 5:5
SMI_DCS_START_LSB 1
DMA12_DEST_AD_D_ADDR_SET 0xffffffff
I2C_SPI_SLV_IMSC_RXIM_CLR 0xfffffffe
DMA3_DEBUG_LITE_LSB 28
SMI_CS_RXD_SET 0x20000000
GROPCTR_FBC_CZ_PBE_REQS 0x24
TB_BOOT_ADDR 0x7e20b500:RW
DMA4_CS_ABORT_SET 0x40000000
A2W_PLLC_DIG1R_WIDTH 24
CM_SLIMCTL_SRC_SET 0x0000000f
AVE_OUT_CB_COEFF_MASK 0x3fffffff
A2W_SMPS_L_SIA_RESET 0000000000
PIARBCTL_CAM_LIMIT_LSB 0
USB_HCCHAR0_CH_ENA_CLR 0x7fffffff
CCP2TTC 0x7e001018:RW
A2W_PLLB_SP1_BYPEN_BITS 9:9
AUX_SPI0_IO_REG (0x7E215000 +0x0A0)
HDMI_READ_POINTERS_DRFT_FULL_MINUS_MSB 20
SMICS_AFERR 25
SD_CS_ASHDN_T_CLR 0xff87ffff
CSI2_RDSA0 CSI2_BASE_ADDRESS + 0x120:RW
HDMI_READ_POINTERS_DOMAIN_WR_ADDR_SET 0x38000000
CCP2TX_TAC_ARST_BITS 0:0
SH_RSP3_CID_CSD_BITS 31:0
A2W_XOSC_CTRL_DDROK_MSB 16
SD_SECEND1_ADDR_MS_SET 0xffffe000
DMA13_DEST_AD 0x7e007d10:RO
SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_BITS 7:6
USB_DFIFO1_MASK 0xffffffff
CM_PLLD_MASK 0x000003ff
EMMC_CONTROL0_HCTL_8BIT_SET 0x00000020
A2W_PLLC_DIG2_RESET 0x00100401
USB_GPVNDCTL_STS_DONE_SET 0x08000000
CM_SDCCTL_RESET 0x00004000
MS_SEMA_10_MASK_BITS 0:0
PWM_CTL_SBIT4_CLR 0xf7ffffff
EMMC_TUNE_STEPS_DDR_STEPS_CLR 0xffffffc0
DMA11_TI_WAITS_CLR 0xfc1fffff
SLIM_DCC5_STAT_WIDTH 32
FPGA_CTRL0_SD_PSU_EN_SET 0x00000010
USB_GOTGINT_HST_NEG_DET_LSB 17
PM_CCP2TX_LDOEN_MSB 1
HDCP_KEY_KY1_WIDTH 24
GP_GPTEST_SPARE_MSB 3
EMMC_FORCE_IRPT_CMD_DONE_CLR 0xfffffffe
MPHI_INTSTAT_RX1TEND_LSB 12
USB_HCCHAR7_MASK 0xffffffff
EMMC_CONTROL0_HCTL_8BIT_BITS 5:5
APERF0_BW0_RTWAIT_RESET 0000000000
SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_RESET 0x0
DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
HDMI_VERTA0_MANUAL_VAL0_MSB 12
EMMC_INTERRUPT_BOOTACK_LSB 13
HD_MAI_THR_DREQHIGH_BITS 13:8
DSI0_TST_SEL_WIDTH 8
USB_DIEPEMPMSK_EP_TXF_EMP_MSK_CLR 0xffff0000
EMMC_INTERRUPT_ERR_CLR 0xffff7fff
DMA3_DEBUG_VERSION_BITS 27:25
A2W_PLLC_ANA_STAT_DATA_SET 0x00000fff
DMA10_TI_WAITS_BITS 25:21
MPHI_BASE 0x7e006000
GP_PUDCLK0_PUDCLKn0_SET 0xffffffff
CM_TD0CTL_FLIP_LSB 11
SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_CLR 0xffffff3f
DMA11_TI_DEST_INC_SET 0x00000010
CM_DFTDIV_DIV_CLR 0xfffe0fff
EMMC_CMDTM_TM_DAT_DIR_BITS 4:4
SD_SA_RFSH_T_MSB 31
PM_HDMI 0x7e100058:RW
SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_MSB 5
A2W_PLLC_ANA2R_MASK 0x00ffffff
USB_VBUS_DRV_DRVVBUS (1<<4)
SPI_CS_CLEAR_MSB 5
USB_GINTMSK_I2C_INT_MSB 9
VPU_ARB_CTRL_L2_ALGORITHM_MSB 7
DSI1_HSTX_TO_CNT_WIDTH 24
A2W_PLLH_ANA_STATR_RESET 0000000000
PCM_CS_A_DMAEN_SET 0x00000200
DMA0_DEBUG_FIFO_ERROR_SET 0x00000002
USB_GAHBCFG_H_BST_LEN_LSB 1
DMA15_TI_INTEN_LSB 0
DMA15_DEBUG_VERSION_BITS 27:25
SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_CLR 0xffffffcf
DMA5_TI_SRC_INC_CLR 0xfffffeff
GP_FSEL0_FSEL07_SET 0x00e00000
MS_ICCLR_1_ICCLR_1_SET 0x00000001
CM_LOCK_FLOCKH_BITS 12:12
MULTICORE_SYNC_MBOX_MASK(num) MACRO
CM_ARMCTL_BUSYD_CLR 0xfffffeff
A2W_PLLA_CCP2_CHENB_BITS 8:8
USB_HCCHAR0_ODD_FRM_BITS 29:29
GP_FSEL0_FSEL07_MSB 23
DMA0_TI_SRC_IGNORE_BITS 11:11
SD_SECEND3_ADDR_MS_CLR 0x00001fff
CAM1_CAMIBSA1_WIDTH 32
V3D_PCTRS0_MASK 0x0000001f
USB_GOTGINT_HST_NEG_DET_CLR 0xfffdffff
AVE_OUT_OFFSET_BLUE_OFFSET_LSB 0
PWMCTL_USEF(n) MACRO
DMA6_TI_SRC_IGNORE_BITS 11:11
CM_PLLTCNT3_CNT_BITS 23:0
MS_SEMA_1 0x7e000004:RW
SPI_LTOH_WIDTH 4
UART_LSR_DR_LSB 0
USB_HCINT0_CH_HLTD_BITS 1:1
SDRSP2 SDCARD_BASE + 0x18:RW
DMA_TI_S_DREQ (1<<10)
CM_PLLB_ANARST_BITS 8:8
HDMI_RAM_PACKET_13_4_MASK 0xffffffff
USB_DTKNQR3_MASK 0xffffffff
PCM_RXC_A_WIDTH 32
HDMI_DETECTED_VERTB1_MANUAL_VSPO1_SET 0x003ffe00
MPHI_INTCTRL_IMFOFLW_MSB 8
I2C_SPI_SLV_DEBUG2_DATA_SET 0x00ffffff
DMA9_CS_PAUSED_MSB 4
DMA12_TI_SRC_IGNORE_BITS 11:11
SYSAC_ISP_PRIORITY_RESET 0000000000
SD_DQRCRC9_FALL_BITS 15:0
USB_HCINT0_MASK 0xffffffff
TXP_PROGRESS_LINES_MSB 11
CCP2TX_TDL_LEN_MSB 29
A2W_PLLB_ANA_MULTI_RESET 0000000000
USB_DOEPCTL9_MASK 0xffffffff
USB_GINTMSK_USB_SUSP_RESET 0x0
V3D_DBSDR2_MASK 0xffffffff
GR_FBC_ADDR_MASK 0x0000007F
DMA0_TI_DEST_IGNORE_LSB 7
PIXELVALVE1_HORZA 0x7e20700c:RW
PIXELVALVE1_HORZB 0x7e207010:RW
GP_FSEL5_FSEL59_BITS 29:27
SCALER_DISPBASE1 0x7e40005c:RW
SCALER_DISPBASE2 0x7e40006c:RW
SD_PHYC_CRC_CLR_LSB 24
USB_GHWCFG2_TOKEN_QUEUE_DEPTH_CLR 0x83ffffff
USB_HCCHAR0_MPS_BITS 10:0
MS_SEMA_10_MASK_CLR 0xfffffffe
ASB_V3D_S_CTRL_FULL_MSB 3
VEC_SECAM_GAIN_VAL 0x7e80619c:RW
SD_CARCRC_WIDTH 32
DMA11_CS_ERROR_CLR 0xfffffeff
SMI_DA_ADDR_LSB 0
USB_GGPIO_GPO_MSB 31
DMA5_TI_WAIT_RESP_SET 0x00000008
CCP2TX_TC_SWR_LSB 31
TB_TASK_PARAM1_MASK 0xffffffff
CM_H264CTL_GATE_BITS 6:6
CM_VECDIV_DIV_SET 0x0000f000
DMA14_TI_SRC_INC_MSB 8
SD_RDC_MASK 0x0fffffff
SD_SF 0x7ee000b4:RW
USB_DOEPCTL0_STALL_CLR 0xffdfffff
CM_INTEN_GAINH_CLR 0xffffffef
SMI_CS_RXF_RESET 0x0
HD_MAI_CTL_FLUSH_SET 0x00000200
A2W_SMPS_CTLA2R_RESET 0000000000
USB_GHWCFG4_EN_IDDIG_FILTER_LSB 20
GP_AFEN0_WIDTH 32
CAM1_CAMIDI0_RESET 0000000000
A2W_PLLC_ANA_VCO_MASK 0x00000001
CMPLL2 0x7C:RW
A2W_PLLC_ANA_SSCL_MASK 0x003fffff
AVE_OUT_CR_COEFF_RED_COEFF_BITS 29:20
SD_SE_WIDTH 29
APERF0_BW0_WTRANS_MASK 0xffffffff
V3D_VPMBASE_WIDTH 32
MPHI_INTSTAT_RX0MEND_BITS 0:0
SD_SECEND2_ADDR_MS_BITS 31:13
DMA9_TI_DEST_WIDTH_CLR 0xffffffdf
CM_PLLC_HOLDPER_SET 0x00000080
PWM_APB_ID 0x70776d30
CM_PLLC_HOLDCORE2_LSB 5
OTP_BOOT_SIGNING_KEY_ROW_REDUNDANT ((((((8 +4)+4)+1)+1)+1)+4)
DMA4_TI_SRC_DREQ_SET 0x00000400
I2C_SPI_SLV_ICR_BEIC_SET 0x00000004
DMA15_TXFR_LEN_YLENGTH_BITS 29:16
CM_EVENT_WIDTH 24
A2W_PLLA_CORER_MASK 0x000003ff
DMA_DEBUG_OUTSTANDING_WRITES (1<<4)
GP_AFEN0_AFENn0_CLR 0x00000000
HDMI_DVO_TIMING_ADJUST_A 0x7e902128:RW
HDMI_DVO_TIMING_ADJUST_B 0x7e90212c:RW
HDMI_DVO_TIMING_ADJUST_C 0x7e902130:RW
DMA0_CS_END_SET 0x00000002
HDMI_SCHEDULER_CONTROL_POSTLN_AVOID_CLR 0xffffc0ff
USB_DTHRCTL_RX_THR_EN_LSB 16
CM_ISPCTL_SRC_MSB 3
DMA1_TI_SRC_INC_LSB 8
USB_HCDMA7_MASK 0xffffffff
AVE_OUT_OFFSET_GREEN_OFFSET_BITS 15:8
DMA10_TI_DEST_INC_BITS 4:4
SCALER_DISPECTRL_CR_NE_CTRL_LSB 30
CM_TCNTCTL_SRC1_MSB 13
DMA9_CS_ACTIVE_SET 0x00000001
HDMI_RAM_PACKET_7_3_WIDTH 32
CM_H264CTL_FRAC_MSB 9
EMMC_INTERRUPT_ENDBOOT_MSB 14
A2W_PLLH_RCALR 0x7e102c60:RW
DMA12_NEXTCONBK_ADDR_CLR 0x0000001f
USB_GPVNDCTL_STS_BSY_RESET 0x0
SLIM_DCC0_STAT_MASK 0xc0ff00c7
CM_TD1CTL_BUSYD_LSB 8
CM_PLLTCTL_MASK 0x000000a7
ASB_CPR_CTRL_EMPTY_LSB 2
DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL 0x7ee0704c:RW
CM_PLLA_HOLDCORE_LSB 5
L1_IC1_CONTROL_ENABLE_STATS_LSB 2
EMMC_TUNE_STEPS_STD_MASK 0x0000003f
HDMI_FIFO_CTL_MASTER_SLAVE_N_SET 0x00000001
A2W_SMPS_CTLA1_MASK 0x00ffffff
DMA1_CS_END_MSB 1
CSI2_RPC_x(x) MACRO
HDMI_RAM_PACKET_3_5_WIDTH 32
UNUSED_DMA_12 (12*(1<<16))
UNUSED_DMA_14 (14*(1<<16))
A2W_PLLH_ANA_STAT_RCALDONE_LSB 12
SET_GPIO_ALT(g,a) MACRO
I2C_SPI_SLV_ICR_BEIC_BITS 2:2
USB_HPRT_RST_RESET 0x0
CAM0_CAMIBWP 0x7e80011c:RW
L1_D_PRIORITY_c0_uc_priority_SET 0x000000f0
CCP2TX_TS_ARE_SET 0x00000004
EMMC_TUNE_STEPS_STD_STEPS_BITS 5:0
DMA5_CS_PRIORITY_SET 0x000f0000
CM_INTEN_FGAIND_LSB 13
FPGA_MB_CORE_CLK_FREQ 0x7e20b724:RO
SLIM_DCC2_STAT_WIDTH 32
HDMI_CORE_REV_MASK 0x0000ffff
AVE_IN_BUF1_ADDRESS_MASK 0xffffffff
HDMI_RAM_PACKET_9_0_RESET 0000000000
DMA7_TI_SRC_INC_MSB 8
MPHI_C0INDCF_ORUN_LSB 29
FPGA_CTRL0_DIS_SW_SPI_LSB 5
SD_PT2_T_INIT5_CLR 0xffff0000
DMA14_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
CM_TD1CTL_FLIP_CLR 0xfffff7ff
EMMC_HWMAXAMP0_AMP_18V_SET 0x00ff0000
DMA2_TI_SRC_WIDTH_BITS 9:9
HDMI_CPU_STATUS_WIDTH 32
SD_DQLCRC15_MASK 0xffffffff
DSI0_HS_DLT5_WIDTH 10
SD_DQLCRC11_FALL_SET 0x0000ffff
EMMC_IRPT_EN_DMA_BITS 3:3
USB_GUSBCFG_ULPI_IF_PROT_DIS_BITS 25:25
EMMC_IRPT_EN_DCRC_ERR_LSB 21
DSI_AFEC0 0x7e209000 + 0x64:RW
DSI_AFEC1 0x7e209000 + 0x68:RW
DMA9_TI_PERMAP_MSB 20
VPU_ARB_CTRL_L2_MASK 0x0000ffff
USB_GUSBCFG_ULPI_EXT_VBUS_IND_LSB 21
A2W_SMPS_L_MULTI_WIDTH 0
SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_RESET 0x0
FPGA_MB_XSLC2_BUILD_NUM_MASK 0xffffffff
CSI2_RPC0 CSI2_BASE_ADDRESS + 0x104:RW
CAM0_CAMIDS_WIDTH 32
V3D_SQRSV0_MASK 0xffffffff
HDMI_RAM_PACKET_5_2_RESET 0000000000
PM_PADS5_POWOK_LSB 5
DSI0_PHY_AFEC0_MASK 0x000000ff
DMA0_CS_DREQ_STOPS_DMA_MSB 5
ARM_1_MAIL1_CNF (0x7E00B000 +0x900)+0xBC:RW
SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_BITS 7:6
DMA6_TI_SRC_IGNORE_SET 0x00000800
MPHI_C1INDCF_LENGTH_SET 0x000fffff
CM_SDCCTL_CTRL_MSB 15
A2W_PLLC_DIG0_WIDTH 24
APERF0_BW0_WTRANS 0x7e009850:RO
CAM1_CAMICTL 0x7e801100:RW
CM_INTEN_LOSSA_MSB 5
CM_PLLC_DIGRST_BITS 9:9
PCM_INTSTC_A_RXERR_BITS 3:3
USB_DIEPTSIZ11_WIDTH 32
AVE_IN_CTRL_FRAME_RATE_IRQ_EN_SET 0x00000040
GP_FSEL3_FSEL38_MSB 26
HDMI_RAM_PACKET_1_4_RESET 0000000000
SD_MR_RW_MSB 28
APERF1_GEN_CTRL_ENABLE_BITS 0:0
DMA_ENABLE_EN5_BITS 5:5
USB_DIEPCTL0_MPS_MSB 10
DMA4_TI_SRC_DREQ_BITS 10:10
GP_FSEL5_FSEL59_CLR 0xc7ffffff
MS_SEMA_19_MASK 0x00000001
HDMI_READ_POINTERS_DRFT_HOLD_WR_BITS 23:23
CM_ISPDIV 0x7e101034:RW
A2W_PLLC_PERR_WIDTH 10
DSI_HS_CLT1 0x7e209000 + 0x48:RW
USB_DOEPCTL15_MASK 0xffffffff
DMA4_CS_DISDEBUG_CLR 0xdfffffff
PCM_CS_A_STBY_BITS 25:25
USB_DCTL_IGN_FRM_NUM_BITS 15:15
SD_VIN_CLEAR_BITS 31:31
GP_FSEL6_FSEL62_SET 0x000001c0
DMA8_TI_DEST_IGNORE_LSB 7
AVE_IN_CTRL_BUF_SER_IRQ_EN_MSB 3
APERF1_BW1_CTRL_LATHALT_SET 0x10000000
DMA2_CS_ABORT_LSB 30
SD_TMC_TSTCLK_SET 0x00000001
DMA13_CS_PAUSED_LSB 4
SCALER_DISPSTAT_DSP1_IRQ_BITS 31:2
USB_PCGCR_WIDTH 4
PM_IMAGE_PERIRSTN_MSB 6
HDMI_RAM_PACKET_4_4_MASK 0xffffffff
A2W_PLLA_ANA_VCOR_RESET 0000000000
HD_CSC_CTL_MODE_LSB 2
V3D_PCTR11_WIDTH 32
CMI_CAM1_MASK 0x000003ff
GRSFSF 0x1A005800 + 0x3C:RW
DMA14_DEBUG_FIFO_ERROR_MSB 1
SMI_DSR1_RDREQ_CLR 0xffffff7f
GP_FSEL3_FSEL38_LSB 24
DMA15_TI_WAIT_RESP_SET 0x00000008
EMMC_CONTROL0_WIDTH 27
DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
A2W_PLLC_ANA2R_WIDTH 24
CCP2TX_TS_TFE_MSB 4
I2C_SPI_SLV_DR_TXDMAPREQ_MSB 10
VEC_MASK0_WIDTH 32
APERF0_GEN_CTRL_ENABLE_RESET 0x0
DMA6_NEXTCONBK_ADDR_LSB 5
SCALER_GAM_ADDRESS 0x7e400000 + 0x78:RW
USB_GUSBCFG_SRP_CAP_RESET 0x0
UART_LSR_DR_MSB 0
HDMI_SCHEDULER_CONTROL_VSYNC_RESET_VAL_SET 0x003c0000
SLIM_DCC5_CON_RESET 0000000000
MS_SEMA_24_MASK 0x00000001
A2W_PLLH_AUX_BYPEN_BITS 9:9
A2W_PLLH_DIG1R_RESET 0000000000
DMA10_TI_DEST_WIDTH_BITS 5:5
CM_DPICTL 0x7e101068:RW
DMA_CS_WAIT_FOR_LAST_WRITE (1<<28)
I2C_SPI_SLV_FR_RXFF_SET 0x00000008
HD_MAI_THR 0x7e808018:RW
DMA4_DEST_AD_D_ADDR_LSB 0
I2C_SPI_SLV_DMACR_WIDTH 3
A2W_PLLB_ANA_SSCS_MODE_CLR 0xfffeffff
SMI_DSR1_RSTROBE_SET 0x0000007f
USB_DIEPINT0_IN_EP_NAK_EFF_CLR 0xffffffbf
A2W_XOSC_CTRL_DDREN_CLR 0xffffffef
DMA12_DEBUG_READ_ERROR_MSB 2
SMI_DC_PANICR_BITS 23:18
L2_RD_HITS 0x7ee01100:RW
CM_PLLD_HOLDDSI1_CLR 0xfffffff7
A2W_PLLH_CTRLR_RESET 0x00010000
DMA2_TI_WIDTH 27
VEC_DAC_TEST_MASK 0xffffffff
DMA6_TI_PERMAP_LSB 16
A2W_PLLB_ANA_STATR_MASK 0x00000fff
DMA8_DEBUG_DMA_ID_LSB 8
EMMC_IRPT_EN_DEND_ERR_MSB 22
EMMC_FORCE_IRPT_DEND_ERR_LSB 22
A2W_PLLB_CTRL_NDIV_SET 0x000003ff
CM_TIMERCTL_BUSY_SET 0x00000080
PIXELVALVE1_INTEN 0x7e207024:RW
CAM0_CAMPRI_RESET 0000000000
AVE_IN_STATUS_FRAME_RATE_SET 0x00000300
GP_FSEL0_FSEL00_BITS 2:0
TB_BOOT_OPT_BOOT_HALT_SET 0x00000080
CM_H264CTL_ENAB_LSB 4
USB_GRXSTSP_DEV_DPID_RESET 0x0
A2W_PLLB_ANA_SCTL_UPDATE_LSB 3
MS_ICSET_0_ICSET_0_CLR 0xfffffffe
DMA15_TI_TDMODE_SET 0x00000002
A2W_PLLH_RCAL_RESET 0x00000100
ADC_DMA (15*(1<<16))
HDMI_FIFO_CTL_ON_VB_SET 0x00000080
DMA9_CS_ABORT_CLR 0xbfffffff
GP_CLR0_CLRn0_SET 0xffffffff
SD_DQLCRC7_MASK 0xffffffff
CM_UARTCTL_BUSYD_BITS 8:8
SD_DQLCRC3_FALL_MSB 15
GP_SET1_MASK 0xffffffff
HDMI_RAM_GCP_2_MASK 0xffffffff
USB_DPTXFSIZ8_WIDTH 32
PWM_CTL_USEF1_MSB 5
A2W_PLLC_ANA_KAIP_RESET 0x0000033a
USB_HPTXSTS_HPTXQTOP_CLR 0x00ffffff
MPHI_C0INDS_VALID_RESET 0x0
AVE_OUT_CR_COEFF_GREEN_COEFF_MSB 19
AVE_IN_CTRL_LOW_PRIORITY_SET 0x000f0000
USB_HPTXSTS_HPTXQSPCAVAIL_LSB 16
PCM_INTEN_A_RXERR_LSB 3
USB_GOTGINT_DBNCE_DONE_BITS 19:19
DMA14_CS_ABORT_BITS 30:30
DMA7_CONBLK_AD_SCB_ADDR_MSB 31
A2W_XOSC_CTRL_PLLAEN_BITS 6:6
PWMCTL_MODE(n) MACRO
USB_HCDMA0 0x7e980514:RW
USB_HCDMA1 0x7e980534:RW
USB_HCDMA2 0x7e980554:RW
USB_HCDMA3 0x7e980574:RW
USB_HCDMA4 0x7e980594:RW
USB_HCDMA5 0x7e9805b4:RW
DMA10_TI_WIDTH 26
DMA9_TI_WAIT_RESP_MSB 3
I2C_SPI_SLV_RIS_BERIS_LSB 2
PM_CAM0_LDOLPEN_SET 0x00000002
DMA6_TI_NO_WIDE_BURSTS_MSB 26
USB_GOTGINT_A_DEV_TOUT_CHG_BITS 18:18
A2W_SMPS_L_SIVR_MASK 0x0000001f
USB_DOEPTSIZ4_MASK 0xffffffff
USB_GUSBCFG_SRP_CAP_SET 0x00000100
GP_FSEL3_FSEL34_LSB 12
I2C_SPI_SLV_CR_ENSTAT_SET 0x00000020
CM_SMICTL_ENAB_SET 0x00000010
SYSAC_DBG_PRIORITY_PRIORITY_SET 0x0000000f
I2C_SPI_SLV_CR_INV_TXF_LSB 13
IC1_MASK7_RESET 0000000000
I2C_SPI_SLV_RIS_RXRIS_BITS 0:0
DMA1_TI_DEST_DREQ_SET 0x00000040
SD_SC_WL_CLR 0xfffffff8
L1_L1_SANDBOX_START0_START_ADDR_LSB 5
GP_LEV2_LEVn64_MSB 5
CM_AVEOCTL_ENAB_SET 0x00000010
DMA12_TI_DEST_INC_SET 0x00000010
DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
DMA9_TI_INTEN_LSB 0
PIXELVALVE2_HORZB_WIDTH 32
EMMC_SLOTISR_VER_VENDOR_SET 0xff000000
I2C_SPI_SLV_DR_OE_BITS 8:8
L2_FLUSH_END_RESET 0x0fffffe0
MULTICORE_SYNC_ICSET_1 MULTICORE_SYNC_BASE_ADDRESS + 0x94:RW
DMA6_TI_MASK 0x07fffffb
A2W_SMPS_A_MODE_BSTPWMB_CLR 0xfffffffe
FPGA_B0_BASE 0x7e214000
CM_TDCLKEN_USBDFT_CLR 0xfffff7ff
AVE_OUT_CTRL_ENABLE_SET 0x80000000
A2W_PLLB_ANA0R 0x7e1028f0:RW
USB_DOEPINT0_IN_EP_NAK_EFF_LSB 6
SDDAT 0x7ee00038:RO
DMA15_CS_ABORT_LSB 30
SD_DQLCRC4_RISE_CLR 0x0000ffff
MPHI_INTSTAT_HSDCFOFLW_BITS 27:27
DMA13_TI_PERMAP_LSB 16
PM_PXBG_WIDTH 16
PM_GNRIC_RSTN_MSB 11
EMMC_INTERRUPT_ATA_ERR_LSB 29
DMA7_NEXTCONBK_WIDTH 32
EMMC_INTERRUPT_CEND_ERR_SET 0x00040000
SMI_DSR3_RDREQ_MSB 7
USB_DIEPCTL0_SNP_BITS 20:20
SH_HSTS_REW_TIME_OUT_CLR 0xffffff7f
APERF0_BW1_CTRL_ID_LSB 8
GPFEN0 0x7e200000 + 0x58:RW
USB_DIEPDMA7_WIDTH 32
USB_GUSBCFG_ULPI_CLK_SUS_M_LSB 19
USB_GOTGCTL_HST_SET_HNP_EN_LSB 10
FPGA_CTRL0_SW_SPI_CS_BITS 8:8
HDMI_CEC_TX_DATA_4_RESET 0000000000
JCTRL_FLUSH (1 << 2)
DMA13_TI_WAITS_BITS 25:21
USB_HPTXSTS_HPTXQSPCAVAIL_RESET 0x0
DMA2_CS_PANIC_PRIORITY_BITS 23:20
SD_REORD_RESET 0000000000
HDMI_RAM_PACKET_6_8_MASK 0xffffffff
USB_HCCHAR0_CH_DIS_SET 0x40000000
CAM1_CAMCMP1_MASK 0xffffffff
HDMI_SCHEDULER_CONTROL_USE_PREDICTS_LSB 2
CM_DSI1PCTL_FRAC_SET 0x00000200
USB_DOEPINT0_EP_DISBLD_CLR 0xfffffffd
DMA3_STRIDE_D_STRIDE_SET 0xffff0000
PCM_CS_A_TXSYNC_MSB 13
USB_DOEPDMAB13_WIDTH 32
PM_CAM0_CTRLEN_SET 0x00000001
TS_TSENSSTAT_INTERUPT_BITS 11:11
SCALER_DISPGAMADR_WIDTH 32
GP_FEN1_MASK 0xffffffff
SCALER_DISPCTRL1_MASK 0xffffffff
PM_RSTS_HADSRQ_MSB 8
UART_LCR_WIDTH 8
EMMC_IRPT_EN_ACMD_ERR_MSB 24
USB_GRSTCTL_FRM_CNTR_RST_BITS 2:2
AVE_IN_STATUS_BUF_NOT_SERV_LSB 3
SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_LSB 8
PWMSTA_RERR1 3
A2W_PLLD_DIG2R_WIDTH 24
APERF1_GEN_CTRL_RESET 0000000000
DMA5_CS_ERROR_CLR 0xfffffeff
PM_WDOG_TIME_SET 0x000fffff
DMA6_DEBUG_DMA_STATE_CLR 0xfe00ffff
HD_VID_CTL_EMPSYNC_MSB 20
A2W_PLLC_ANA_MULTI_RESET 0000000000
USB_DCFG_DEV_SPD_BITS 1:0
DMA12_TXFR_LEN_XLENGTH_LSB 0
SMI_DSR0_RPACEALL_BITS 15:15
SLIM_DCC7_PROT_MASK 0xc001ffff
AVE_IN_CTRL_PRIORITY_LIMIT_BITS 26:24
MPHI_OUTDS_VALID_LSB 30
CM_TDCLKEN_IMAGETD_MSB 13
APERF0_BW1_CTRL_BUS_BITS 4:0
DMA12_DEBUG_OUTSTANDING_WRITES_MSB 7
SMI_CS_WIDTH 32
CM_GP1CTL_BUSYD_CLR 0xfffffeff
CM_GP2CTL_ENAB_CLR 0xffffffef
A2W_PLLD_DIG2_WIDTH 24
APERF1_BW2_CTRL_BUS_LSB 0
L1_L1_SANDBOX_START4_CTRL_SET 0x00000001
PWM_STA_FULL1_CLR 0xfffffffe
USB_GOTGINT_SES_END_DET_CLR 0xfffffffb
HDMI_RAM_PACKET_5_0_WIDTH 32
SD_CS_STALLING_SET 0x01000000
MS_SEMA_19_MASK_MSB 0
DMA1_CS_RESET_MSB 31
A2W_PLLC_PERR 0x7e102d20:RW
DMA7_TI_BURST_LENGTH_BITS 15:12
CAM1_CAMIDS_RESET 0000000000
MPHI_CTRL_ENABLE_SET 0x80000000
USB_GINTMSK_INCOMPL_ISO_OUT_SET 0x00200000
A2W_PLLA_CORE_CHENB_SET 0x00000100
MPHI_C0INDDB_TENDINT_SET 0x20000000
USB_GUSBCFG_FORCE_DEV_MODE_SET 0x40000000
MS_SEMA_25_MASK_LSB 0
SD_PT1_T_INIT3_RESET 0x13880
USB_GOTGCTL_SES_REQ_SET 0x00000002
DMA_TI_PERMAP (1<<16)
USB_GUSBCFG_ULPI_AUTO_RES_SET 0x00040000
USB_DIEPINT0_IN_TKN_EP_MIS_BITS 5:5
SD_DQRCRC6_RISE_CLR 0x0000ffff
CM_LOCK_FLOCKH_LSB 12
HDMI_RAM_PACKET_1_2_WIDTH 32
PM_GRAFX_ISPOW_CLR 0xfffffffb
A2W_SMPS_C_CLK_USEOSC_CLR 0xfffffffb
APERF0_BW0_CTRL_BUS_CLR 0xffffffe0
MPHI_MINFS_WPTR_CLR 0xfff003ff
USB_DIEPCTL9_MASK 0xffffffff
SCALER_DISPDITHER_WIDTH 32
DMA4_CS_DREQ_STOPS_DMA_MSB 5
HDMI_VERTB1_MANUAL_VSPO1_BITS 21:9
OTP_BOOT_ROM_ROW_REDUNDANT ((((8 +4)+4)+1)+1)
SCALER_DISPCTRL_DSP3_MUX_LSB 18
CM_VPUCTL 0x7e101008:RW
IDCLVWMC 0x10002020:RW
SLIM_DCC1_PROT_WIDTH 32
DMA5_TI_SRC_DREQ_SET 0x00000400
DMA2_CS_PAUSED_SET 0x00000010
PM_DSI1_CTRLEN_MSB 0
CM_BURSTCTL_ENAB_SET 0x00000010
BOOTROM_ROM_START ( 0x10000000 + 0x0 )
CAM0_CAMICS_WIDTH 32
L1_L1_SANDBOX_START4_START_ADDR_CLR 0xc000001f
USB_DOEPCTL0_SET_EVEN_FR_RESET 0x0
MPHI_HSINDS_DISCARD_MSB 31
HD_CSC_22_21_RESET 0000000000
SLIM_DCC5_PA1_RESET 0000000000
SMI_DCS_WRITE_BITS 3:3
A2W_SMPS_CTLC3_WIDTH 24
A2W_PLLD_PER_BYPEN_BITS 9:9
AVE_OUT_OFFSET_BLUE_OFFSET_BITS 7:0
EMMC_HWMAXAMP0_AMP_33V_CLR 0xffffff00
AUX_SPI_CNTL0_SPEEDSHFT 20
HDMI_ASYNC_RM_BASE (HDMI_BASE_ADDRESS + 0x300)
PWM_DMAC_RESET 0x00000707
PM_IMAGE_ISFUNC_CLR 0xffffffdf
PM_DSI0_LDOCTRL_CLR 0xffe00007
MPHI_HSINDDB_HANDLE_BITS 27:20
USB_DTXFSTS6_WIDTH 32
USB_DCTL_GMC_LSB 13
DMA9_TI_WIDTH 26
I2C_SPI_SLV_RSR_UE_BITS 1:1
VPU_ARB_CTRL_UC_DELAY_MSB 3
PWM_CTL_RPTL4_MSB 26
SLIM_DMA_DC9_RESET 0000000000
A2W_PLLC_ANA3 0x7e10203c:RW
CM_PLLH_LOADAUX_SET 0x00000002
SCALER_DISPECTRL_TWOD_SINGLE_LSB 25
L1_D_CONTROL_RESET 0000000000
APERF0_BW2_ATWAIT_WIDTH 32
DMA1_DEBUG_FIFO_ERROR_BITS 1:1
PM_AUDIO_RSTN_SET 0x00200000
CM_VECCTL_SRC_LSB 0
CM_TIMERCTL_BUSYD_CLR 0xfffffeff
ASB_V3D_S_CTRL_EMPTY_LSB 2
GRPCBS 0x1A005600 + 0x5C:RW
CM_SMIDIV_DIV_CLR 0xffff000f
CAM1_CAMDBG1_RESET 0000000000
USB_HCSPLT0_PRT_ADDR_RESET 0x0
GP_FEN2_MASK 0x0000003f
GP_PUDCLK0_PUDCLKn0_CLR 0x00000000
DMA6_SOURCE_AD_S_ADDR_MSB 31
GP_FSEL0_FSEL07_CLR 0xff1fffff
USB_GUSBCFG_ULPI_EXT_VBUS_DRV_BITS 20:20
MPHI_INTSTAT_HSTEND_SET 0x80000000
CM_INTEN_RESUS_CLR 0xffbfffff
A2W_PLLA_CCP2_CHENB_CLR 0xfffffeff
L1_D_PRIORITY_c1_uc_priority_SET 0x00f00000
PCM_TXC_A_CH1POS_LSB 20
DMA11_TI_DEST_DREQ_SET 0x00000040
V3D_INTCTL 0x7ec00000 +0x0030:RW
DMA6_CS_PRIORITY_SET 0x000f0000
VEC_STATUS0 0x7e806200:RW
CCP2TX_TS_ARE_CLR 0xfffffffb
MPHI_C0INDDB_HANDLE_LSB 20
SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_RESET 0x0
RSC0ADDR RS_BASE + 0x10:RW
SD_DQLCRC13_RISE_MSB 31
PWM_STA_FULL1_BITS 0:0
CM_TECCTL_ENAB_MSB 4
PM_AVS_EVENT_ALERT_ARM_P_SET 0x00000010
USB_DIEPDMA8_WIDTH 32
DMA13_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
HDMI_SCHEDULER_CONTROL_WIDTH 22
HDMI_READ_POINTERS_DRFT_HOLD_WR_SET 0x00800000
DMA8_NEXTCONBK_MASK 0xffffffe0
TB_BOOT_OPT 0x7e20b504:RW
CM_EVENT_FGAIND_MSB 13
SD_LAC 0x7ee000ac:RO
USB_GRXSTSP_DEV_PKT_STS_RESET 0x0
UART_LSR_TEMT_LSB 6
A2W_PLLA_CORE_CHENB_BITS 8:8
FPGA_STATUS0_OFFSET 0x0C
AVE_IN_STATUS_LINE_NUM_HIT_CLR 0xffffffef
USB_GINTMSK_EOPF_RESET 0x0
AVE_IN_FRAME_NUM_RESET 0000000000
SMI_DSW3_WHOLD_CLR 0xffc0ffff
AUX_MU_LSR_DR 0x01
DMA0_CONBLK_AD_SCB_ADDR_BITS 31:5
DMA_ENABLE_EN5_CLR 0xffffffdf
AUX_MU_LCR_BREAK 0x40
USB_DCFG_DESC_DMA_MSB 23
CM_UARTCTL_KILL_LSB 5
I2C0_S_WIDTH 32
SMI_CS_INTD_MSB 9
ASB_H264_M_CTRL_EMPTY_SET 0x00000004
PCM_INTEN_A_RESET 0000000000
USB_DIEPCTL0_NEXT_EP_LSB 11
DMA5_DEBUG_FIFO_ERROR_CLR 0xfffffffd
CM_DSI1PCTL_BUSY_SET 0x00000080
SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_SET 0x00000008
HDMI_READ_POINTERS_DRFT_RD_ADDR_CLR 0xffffff7f
SMIFD 0x7e600000 + 0x40:RW
DMA9_CS_PRIORITY_CLR 0xfff0ffff
USB_DIEPCTL0_NEXT_EP_CLR 0xffff87ff
A2W_SMPS_L_SIA_ANA_MSB 9
DMA1_TI_NO_WIDE_BURSTS_MSB 26
VPU_ARB_CTRL_UC_MASK 0x0000ffff
USB_PCGCR_RST_PDWN_MODULE_CLR 0xfffffff7
APERF0_BW0_CTRL_EN_RESET 0x0
CM_LOCK_FLOCKA_CLR 0xfffffeff
CM_EMMCCTL_ENAB_BITS 4:4
HDMI_RAM_PACKET_11_1_WIDTH 32
USB_DTHRCTL_TX_THR_LEN_RESET 0x0
USB_DTHRCTL_ISO_THR_EN_SET 0x00000002
PM_GRAFX_WIDTH 23
CM_EVENT_A2WDONE_BITS 20:20
CSI2_RWP_x(x) MACRO
IC1_MASK5_WIDTH 31
DMA11_TI_INTEN_MSB 0
HDMI_HORZA_MANUAL_HPOL_MSB 13
SD_SB_STBY_T_BITS 31:20
TE_2TIMER_WIDTH 32
DSI0_PHYC_txulps_clk_sync_LSB 9
V3D_SRQCS 0x7ec00000 +0x043c:RW
PM_GNRIC_MEMREP_CLR 0xfffffff7
APERF1_BW1_WTWAIT_WIDTH 32
HDMI_DVO_TIMING_ADJUST_B_WIDTH 32
AVE_IN_CTRL_FRAME_MODE_LSB 9
I2C_SPI_SLV_RIS_RESET 0x00000002
AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_SET 0x80000000
USB_GHWCFG2_SINGLE_POINT_MSB 5
USB_GRXSTSP_DEV_DPID_CLR 0xfffe7fff
SMI_CS_CLEAR_LSB 4
CM_HSMCTL_FRAC_CLR 0xfffffdff
TB_BOOT_OPT_SDC_BEHAV_PHY_LSB 5
DMA2_TI_PERMAP_SET 0x001f0000
USB_DSTS_ENUM_SPD_LSB 1
DMA12_NEXTCONBK_ADDR_BITS 31:5
L1_IC0_CONTROL_DISABLE_LSB 0
V3D_PCTR7_MASK 0xffffffff
A2W_PLLD_DSI0_DIV_BITS 7:0
GR_VCM_CI_BASE 0x1A005C80
PWM_CTL_POLA3_CLR 0xffefffff
CM_SDCCTL_SRC_SET 0x0000000f
AVE_OUT_OFFSET_RED_OFFSET_CLR 0xff00ffff
GP_SEN0 0x7e2000a4:RW
GP_SEN1 0x7e2000a8:RW
MPHI_HSINDDB_TENDINT_CLR 0xdfffffff
USB_HFNUM_NUM_CLR 0xffff0000
MPHI_INTSTAT_HSTEND_CLR 0x7fffffff
DMA5_TI_DEST_DREQ_MSB 6
GRPCFG 0x1A005600 + 0x04:RW
CM_CAM1DIV_MASK 0x0000fff0
CMI_CAMTEST_WIDTH 5
CM_ISPCTL_GATE_LSB 6
HDMI_TEST_RESET 0000000000
DMA12_CS_PAUSED_MSB 4
SMI_DSW2_WFORMAT_SET 0x00800000
ARM_CONTROL0 0x7E00B000 +0x000:RW
ARM_CONTROL1 0x7E00B000 +0x440:RW
A2W_PLLC_ANA_VCO 0x7e102630:RW
DMA3_CONBLK_AD_SCB_ADDR_MSB 31
L1_L1_SANDBOX_START6_START_ADDR_MSB 29
CM_TD1CTL_FRAC_MSB 9
PWM_CTL_MODE3_MSB 17
EMMC_HWCAP1_RETUNE_TMR_SET 0x00000f00
CCP2TSPARE 0x7e001028:RW
L1_IC0_CONTROL 0x7ee02000:RW
SD_DQLCRC4_FALL_BITS 15:0
SH_RSP3_MASK 0xffffffff
A2W_XOSC_CTRL_PLLDEN_MSB 5
USB_GNPTXSTS_WIDTH 31
DMA13_TI_SRC_WIDTH_LSB 9
DMA15_TI_WAIT_RESP_MSB 3
DPHY_CSR_BYTE1_SLAVE_DLL_OFFSET 0x7ee07020:RW
SMI_DSW3_WPACEALL_SET 0x00008000
EMMC_CMDTM_CMD_RSPNS_TYPE_CLR 0xfffcffff
FPGA_SCRATCH_WIDTH 32
DMA14_TI_DEST_WIDTH_LSB 5
MPHI_MOUTFS_RPTR_LSB 20
SD_CS_EN_MSB 1
A2W_PLLD_ANA_VCO_RANGE_SET 0x00000001
A2W_PLLB_ARM_CHENB_CLR 0xfffffeff
AUX_MU_IIR_REG (0x7E215000 +0x048)
CM_INTEN_GAINB_BITS 1:1
APERF0_BW0_CTRL_EN_SET 0x40000000
SMI_DSR1_RPACE_BITS 14:8
USB_HAINT 0x7e980414:RW
MPHI_HSINDS 0x7e006060:RW
MPHI_HSINDCF_LENGTH_CLR 0xfff00000
A2W_PLLH_PIX_BYPEN_SET 0x00000200
DMA12_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
CM_TECCTL_KILL_CLR 0xffffffdf
PM_RSTS_HADSRF_CLR 0xfffffdff
UART_LSR_RFE_CLR 0xffffff7f
ARM_2_SEM0 (0x7E00B000 +0xA00)+0x00:RW
ARM_2_SEM1 (0x7E00B000 +0xA00)+0x04:RW
ARM_2_SEM2 (0x7E00B000 +0xA00)+0x08:RW
ARM_2_SEM3 (0x7E00B000 +0xA00)+0x0C:RW
ARM_2_SEM4 (0x7E00B000 +0xA00)+0x10:RW
ARM_2_SEM5 (0x7E00B000 +0xA00)+0x14:RW
ARM_2_SEM6 (0x7E00B000 +0xA00)+0x18:RW
ARM_2_SEM7 (0x7E00B000 +0xA00)+0x1C:RW
PM_PROC_MRDONE_LSB 4
SD_SD_T_RCD_LSB 0
GP_AREN2_ARENn64_LSB 0
SYSAC_UC_ARBITER_CONTROL_DELAY_CLR 0xfffffff3
EMMC_STATUS_RETUNING_REQ_LSB 3
DMA3_TI_DEST_WIDTH_SET 0x00000020
I2C_SPI_SLV_DR_UE_LSB 9
EMMC_FORCE_IRPT_DTO_ERR_MSB 20
USB_GOTGCTL_CON_ID_STS_SET 0x00010000
TB_JTB_CONFIG_BUSY_BITS 31:31
MPHI_C1INDS_VALID_RESET 0x0
HDMI_SCHEDULER_CONTROL_ENC_ONLY_WHEN_AUTH_SET 0x00000040
SMI_DSR3_MODE68_CLR 0xff7fffff
ARM_2_SEMS (0x7E00B000 +0xA00)+0x00:RW
PM_HDMI_RSTDR_LSB 19
ARM_C0_JTAGBASH 0x00000800
CM_GNRICCTL_FLIP_SET 0x00000800
USB_HFIR_IN_RESET 0x0
SYSAC_USB_PRIORITY_RESET 0000000000
CM_TECCTL_SRC_BITS 1:0
GRTDBG0 0x1A005300 + 0x00:RW
ASB_V3D_S_CTRL_CLR_ACK_CLR 0xfffffffd
PM_GNRIC_POWUP_CLR 0xfffffffe
GP_FSEL5_FSEL51_BITS 5:3
CCP2TX_TAC_ARST_MSB 0
TB_TASK_NUM_BITS 15:0
DSI0_PHYC_dsi_esc_lpdt_MSB 17
USB_HCTSIZ5_WIDTH 32
USB_DIEPCTL0_SNAK_SET 0x08000000
USB_GINTMSK_INCOMPL_ISO_IN_SET 0x00100000
PWM_CTL_MSEN1_CLR 0xffffff7f
DMA3_TXFR_LEN_YLENGTH_CLR 0xc000ffff
USB_HFNUM_REM_BITS 31:16
A2W_XOSC_CTRL_HDMIEN_SET 0x00000002
AVE_IN_BUF1_ADDRESS_BUF1_ADDR_BITS 31:0
I2C_SPI_SLV_RSR_RXDMAPREQ_BITS 4:4
APERF1_BW2_CTRL_EN_RESET 0x0
DMA1_DEBUG_FIFO_ERROR_MSB 1
GP_FSEL4_FSEL43_BITS 11:9
V3D_PCTR12_WIDTH 32
CAM1_CAMSTA_MASK 0xffffffff
DSI0_CTRL_CTRL1_CLR 0xfffffffd
DMA13_TI_DEST_INC_SET 0x00000010
USB_DIEPINT4 0x7e980988:RW
MS_VPUSEMA_0_VPUSEMA_0_SET 0x00000001
DMA11_SOURCE_AD_S_ADDR_SET 0xffffffff
DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
A2W_SMPS_L_SIAR_RESET 0000000000
EMMC_CMDTM_CMD_ISDATA_LSB 21
GP_FSEL3_FSEL35_BITS 17:15
SMI_DSW1_WSWAP_BITS 22:22
A2W_SMPS_L_SCA_WIDTH 12
MS_MBOX_4_MASK 0xffffffff
CM_PERIADIV_MASK 0x00001000
CM_AVEODIV_DIV_CLR 0xffff0fff
DMA8_CS_DREQ_STOPS_DMA_MSB 5
TB_JTB_CONFIG_ENABLE_CLR 0xfffff7ff
L2_L2_ALIAS_EXCEPTION 0x7ee01080:RW
DMA3_DEST_AD_WIDTH 32
MPHI_C0INDS_VALID_CLR 0xbfffffff
USB_DIEPTXF1_FIFO_STADDR_LSB 0
MPHI_TXAXICFG_WIDTH 17
JCTRL_DCTEN (1 << 4)
A2W_PLLD_ANA_KAIP_KI_BITS 6:4
GP_FSEL4_FSEL49_LSB 27
DMA13_TI_SRC_IGNORE_LSB 11
PWM_CTL_MODE3_CLR 0xfffdffff
A2W_PLLA_ANA_MULTI_MASK 0000000000
UNICAM_DBEA0(x) MACRO
UNICAM_DBEA1(x) MACRO
SMI_DSW3_WSETUP_LSB 24
HDMI_RAM_PACKET_10_8_RESET 0000000000
TXP_CTRL_ABORT_CLR 0xffffbfff
SLIM_DMA_DC7_WIDTH 32
DSI1_HS_CLT2_MASK 0xffffffff
APERF1_BW1_CTRL_ID_LSB 8
CM_INTEN_FGAINA_SET 0x00000400
HDMI_READ_POINTERS_DRFT_RD_ADDR_BITS 7:7
TS_TSENSSTAT_VALID_CLR 0xfffffbff
DMA8_CONBLK_AD_RESET 0000000000
GPCLR0 0x7e200000 + 0x28:RW
GPCLR1 0x7e200000 + 0x2C:RW
A2W_PLLB_SP2_CHENB_LSB 8
GP_FSEL1_FSEL19_BITS 29:27
A2W_PLLC_CORE0_CHENB_SET 0x00000100
EMMC_HWCAP1_SDR50_BITS 0:0
USB_DIEPTXF1_FIFO_SIZE_SET 0xffff0000
USB_GAHBCFG_H_BST_LEN_RESET 0x0
CM_PERIICTL_GATE_MSB 6
A2W_PLLB_ANA_SSCL_LIMIT_BITS 21:0
CM_GP1CTL_SRC_SET 0x0000000f
DMA12_TI_WAIT_RESP_SET 0x00000008
USB_DIEPINT9 0x7e980a28:RW
DMA5_TXFR_LEN_XLENGTH_SET 0x0000ffff
CM_DSI0ECTL_SRC_SET 0x0000000f
A2W_PLLD_ANA_SSCS 0x7e102150:RW
V3D_DBQGHG_MASK 0xffffffff
SMI_DSW3_WFORMAT_BITS 23:23
DMA12_DEBUG_READ_ERROR_CLR 0xfffffffb
USB_VBUS_DRV_DISCHRGVBUS (1<<6)
EMMC_CONTROL1_SRST_CMD_CLR 0xfdffffff
DMA12_TI_PERMAP_MSB 20
MPHI_MOUTFS_WIDTH 32
HD_VID_CTL_EMPRGB_SET 0x00080000
DMA5_DEBUG_FIFO_ERROR_BITS 1:1
DMA7_DEBUG 0x7e007720:RW
ASB_CPR_CTRL_RCOUNT_LSB 4
CMPRE1 0x7C:RW
A2W_PLLH_ANA3R_MASK 0x00ffffff
SCALER_DISPCTRL_DSP2_PANIC_MSB 29
A2W_PLLD_ANA_MULTI_RESET 0000000000
TXP_CTRL_ALPHA_INVERT_MSB 12
DMA5_TI_PERMAP_LSB 16
EMMC_INTERRUPT_OEM_ERR_LSB 30
AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_BITS 14:14
USB_GRXSTSP_HST_DPID_SET 0x00018000
EMMC_CONTROL2_TUNED_SET 0x00800000
SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_MSB 7
DMA14_DEBUG_DMA_STATE_CLR 0xfe00ffff
SD_DQRCRC12_RISE_SET 0xffff0000
CMI_USBCTL_GATE_LSB 6
CAM0_CAMCMP1_WIDTH 32
A2W_SMPS_L_SPA_ANA_MSB 9
PM_WDOG_TIME_MSB 19
A2W_PLLD_CTRL_PDIV_SET 0x00007000
DSI1_LP_DLT6 0x7e700068:RW
DSI1_LP_DLT7 0x7e70006c:RW
DMA15_TI_DEST_DREQ_MSB 6
USB_DSTS_SOF_FN_MSB 21
MS_MBOX_6_MBOX_LSB 0
JSBO 0x7e005000 + 0x20:RW
STC 0x7e003004:RO
A2W_PLLB_CTRL_PWRDN_MSB 16
USB_DOEPCTL6_WIDTH 32
TB_JTB_CONFIG_MASK 0xbfffffff
CM_TD1CTL_ENAB_LSB 4
VCE_SIM_DEBUG_OPTIONS_OFFSET 0x40100
ARM_2_ALL_IRQS (0x7E00B000 +0xA00)+0xF8:RW
DMA1_STRIDE_D_STRIDE_LSB 16
A2W_BASE 0x7e102000
SCALER_DISPCTRL_DSP1_PANIC_LSB 26
DMA7_TXFR_LEN_MASK 0x0000ffff
APERF1_BW1_RPEND_WIDTH 8
MS_MBOX_3_MBOX_BITS 31:0
MPHI_HSINDCF 0x7e00605c:RW
HDMI_FIFO_CTL_ON_VB_DONE_CLR 0xffff7fff
CM_TIMERCTL_SRC_SET 0x00000003
SMI_DSR3_FSETUP_BITS 22:22
MS_SEMA_1_MASK_SET 0x00000001
CM_PWMCTL 0x7e1010a0:RW
SMI_DSW3_WDREQ_CLR 0xffffff7f
SMI_CS_WRITE_CLR 0xffffffdf
USB_DOEPDMAB14_WIDTH 32
CM_H264DIV_DIV_LSB 4
CM_PLLB_LOADARM_MSB 0
PM_PADS6_RESET 0000000000
IC1_FORCE0 0x7e002840:RW
IC1_FORCE0_MASK 0xffffffff
SD_DQRCRC6_MASK 0xffffffff
ACIS_DMA (0*(1<<16))
INTERRUPT_TIMER1 ((64) + 1 )
HD_MAI_CTL_CHALIGN_SET 0x00002000
EMMC_FORCE_IRPT_CTO_ERR_LSB 16
PM_RSTC_DRCFG_BITS 1:0
CM_V3DCTL 0x7e101038:RW
DMA_ENABLE_EN10_SET 0x00000400
CM_BURSTCNT_CNT_CLR 0xff000000
SD_DQRCRC9_RISE_RESET 0x0
TB_JTB_CONFIG_D_HOLD_LSB 12
DMA5_TI_NO_WIDE_BURSTS_MSB 26
MPHI_HSINDDA 0x7e006064:RW
CM_GP2CTL_FRAC_SET 0x00000200
CAM1_CAMIBLS_RESET 0000000000
CM_TD0CTL_SRC_LSB 0
EMMC_FORCE_IRPT_DMA_ERR_CLR 0xefffffff
DMA2_TI_SRC_INC_CLR 0xfffffeff
USB_HPRT_CONN_STS_BITS 0:0
USB_DOEPINT0_TXF_EMPTY_LSB 7
GROPCTR_FOVCLIPPEDPRIMS 0x02
I2C_SPI_SLV_DMACR_MASK 0x00000007
JSDA 0x7e005000 + 0x18:RW
DMA3_TI_WAITS_SET 0x03e00000
USB_DIEPINT8_WIDTH 32
HDMI_RAM_PACKET_13_4_WIDTH 32
USB_GUSBCFG_FORCE_DEV_MODE_RESET 0x0
SLIM_EA1_RESET 0000000000
A2W_XOSC_BIAS_HIGHP_LSB 4
SCALER_DISPBKGND0 0x7e400044:RW
SCALER_DISPBKGND2 0x7e400064:RW
PCM_DREQ_A_RX_PANIC_CLR 0xff80ffff
USB_DOEPINT5_MASK 0xffffffff
DMA7_DEBUG_WIDTH 29
EMMC_HWCAP0_RESET 0000000000
CM_GNRICCTL_MASH_LSB 9
DMA3_TXFR_LEN_XLENGTH_BITS 15:0
SLIM_DMA_DC6_RESET 0000000000
CM_DSI1PDIV_DIV_BITS 12:12
GP_FSEL4_FSEL42_CLR 0xfffffe3f
A2W_PLLD_CTRL_NDIV_CLR 0xfffffc00
SMI_CS_PRDY_RESET 0x0
CM_OSCFREQI_INT_CLR 0xffffff00
USB_HCINTMSK5_MASK 0xffffffff
USB_DCTL_MASK 0x0000efff
USB_DOEPDMA14_WIDTH 32
DMA15_CS_RESET_LSB 31
MS_SEMA_17_RESET 0000000000
MS_SEMA_8_WIDTH 1
USB_HCSPLT5_WIDTH 32
VEC_CFG 0x7e806208:RW
USB_GAHBCFG_H_BST_LEN_MSB 4
PCM_CS_A_RXTHR_MSB 8
USB_DOEPTSIZ0_RX_DPID_CLR 0x9fffffff
USB_DPTXFSIZ2_MASK 0xffffffff
MS_SEMA_13_MASK_CLR 0xfffffffe
APERF1_BW1_ATWAIT_WIDTH 32
CM_DSI1ECTL_KILL_BITS 5:5
SMI_DSR0_MODE68_CLR 0xff7fffff
MPHI_C1INDDB_HANDLE_LSB 20
DMA14_CS_ERROR_BITS 8:8
HDMI_FIFO_CTL_RECENTER_DONE_BITS 14:14
VEC_REVID 0x7e806100:RW
FPGA_STATUS0_NAND_RNB_LSB 6
USB_GOTGCTL_CON_ID_STS_RESET 0x0
CM_PLLH_ANARST_LSB 8
HDMI_DETECTED_VERTA1_MANUAL_VAL1_MSB 12
CM_CAM1CTL_BUSYD_SET 0x00000100
PWM_DMAC_DREQ_SET 0x000000ff
HDMI_RAM_PACKET_4_7_MASK 0xffffffff
EMMC_CMDTM 0x7e30000c:RW
AVE_OUT_STATUS_HSYNC_SET 0x00000040
ULCR 0x7e201000 + 0x0C:RW
USB_GUSBCFG_FS_INTF_LSB 5
SLIM_DCC8_CON_WIDTH 32
DMA15_STRIDE_S_STRIDE_SET 0x0000ffff
PCM_CS_A_RXD_MSB 20
PIXELVALVE_VC_0 0x7e206004:RW
MPHI_HSINDFS 0x7e00606c:RW
DMA11_TI_SRC_INC_MSB 8
EMMC_CMDTM_CMD_IXCHK_EN_MSB 20
PM_GNRIC_ISPOW_LSB 2
USB_DOEPCTL13_WIDTH 32
SH_HSTS_BUSY_IRPT_SET 0x00000400
DMA_CB_NEXT(n) MACRO
CMI_CAMTEST_ENAB_BITS 4:4
SMI_DSR2_FSETUP_CLR 0xffbfffff
GP_FSEL3_FSEL31_SET 0x00000038
HD_VID_CTL_RST_FRAMEC_RESET 0x0
MPHI_C1INDFS_CFIFOLVL_CLR 0x0000ffff
APERF0_BW2_CTRL_ID_EN_LSB 29
HD_VID_CTL_CLRSYNC_RESET 0x0
CCP2TX_TTC_LEC_CLR 0xfffff0ff
VCE_STATUS_INTERRUPT_POS 31
HD_VID_CTL_HPOL_SET 0x08000000
PIXELVALVE_C_0 0x7e206000:RW
PIXELVALVE_C_1 0x7e207000:RW
SH_HCFG_BUSY_IRPT_EN_CLR 0xfffffbff
GP_LEN0_WIDTH 32
USB_DIEPINT0_OUT_PKT_ERR_CLR 0xfffffeff
PIXELVALVE_VC_x(x) MACRO
ASB_H264_M_CTRL_CLR_ACK_LSB 1
USB_GINTMSK_WK_UP_INT_LSB 31
CM_H264CTL_GATE_CLR 0xffffffbf
PM_RSTC_WRCFG_CLR 0xffffffcf
DMA7_TI_DEST_DREQ_CLR 0xffffffbf
SD_RWC_WRTOVR_SET 0x00008000
DMA6_CS_DISDEBUG_CLR 0xdfffffff
DMA_INT_STATUS_INT0_MSB 0
A2W_PLLH_ANA3_MASK 0x00ffffff
DMA14_CS_ABORT_SET 0x40000000
DMA3_TI_TDMODE_LSB 1
CM_PWMCTL_BUSY_CLR 0xffffff7f
DMA5_TI_SRC_WIDTH_LSB 9
HDMI_RAM_PACKET_13_5_MASK 0xffffffff
CM_PLLC_DIGRST_SET 0x00000200
EMMC_INTERRUPT_INT_B_CLR 0xfffffbff
DMA8_TI_SRC_IGNORE_CLR 0xfffff7ff
HD_MAI_CTL_EMPTY_RESET 0x0
DMA8_TI_WAITS_BITS 25:21
L1_L1_SANDBOX_START0_CTRL_BITS 0:0
CM_HSMDIV_MASK 0x0000fff0
UART_BASE_ADDRESS 0x7e201000
DMA13_TI_DEST_WIDTH_MSB 5
A2W_PLLB_SP0_CHENB_BITS 8:8
USB_DOEPCTL0_SET_EVEN_FR_MSB 28
PIXELVALVE_C_x(x) MACRO
EMMC_INTERRUPT_WRITE_RDY_CLR 0xffffffef
A2W_PLLB_ANA3R_RESET 0x00000180
MPHI_C0INDS_WORDS_LSB 0
V3D_SRQPC 0x7ec00000 +0x0430:RW
CAM0_CAMDCS_MASK 0xffffffff
DMA7_TI_WAIT_RESP_BITS 3:3
A2W_PLLC_ANA_SCTL_UPDATE_BITS 3:3
PCM_CS_A_RXSEX_CLR 0xff7fffff
USB_HCCHAR0_MPS_CLR 0xfffff800
AVE_IN_LINE_NUM_INT_LINE_NUM_INT_MSB 11
SLIM_FS 0x7e21000c:RW
AVE_IN_CTRL_EN_OVERRUN_ABORT_SET 0x00008000
MPHI_INTSTAT_RX0MEND_CLR 0xfffffffe
FPGA_CTRL0_SW_SPI_CS_SET 0x00000100
HDMI_RAM_PACKET_10_6_WIDTH 32
PM_AVS_RSTDR_ARM_P_LSB 4
DMA0_NEXTCONBK_ADDR_BITS 31:5
CM_EVENT_A2WDONE_CLR 0xffefffff
SD_DQLCRC4_FALL_CLR 0xffff0000
SMI_DSR2_RDREQ_LSB 7
USB_GINTMSK_PRT_INT_CLR 0xfeffffff
AVE_IN_STATUS_HSYNC_DET_BITS 5:5
RNG_INT_MASK 0x7e104010:RW
I2C_SPI_SLV_DEBUG2_RESET 0x00400000
USB_GUSBCFG_IND_COMP_SET 0x00800000
USB_DOEPCTL0_EO_FR_NUM_LSB 16
A2W_PLLB_SP0_DIV_BITS 7:0
CM_PLLTCNT2_CNT_LSB 0
DMA_ENABLE_EN9_SET 0x00000200
EMMC_IRPT_MASK_ADMA_ERR_LSB 25
I2C_SPI_SLV_ICR 0x7e214024:RW
HD_HDM_CTL_ENABLE_MSB 0
SD_CS_CLKOFF_RESET 0x1
PWM_CTL_SBIT2_CLR 0xfffff7ff
HDMI_CORE_REV 0x7e902000:RW
APERF0_BW2_CTRL_BUS_RESET 0x0
DMA4_TI_SRC_INC_MSB 8
I2C_SPI_SLV_FR_TXBUSY_CLR 0xfffffffe
SCALER_DISPCTRL_DSP1_IRQ_CTRL_SET 0x00000600
EMMC_HWCAP1_MULTIPLIER_LSB 16
L1_IC1_RD_HITS 0x7ee020c0:RW
PCM_RXC_A_CH2POS_CLR 0xffffc00f
A2W_PLLB_ANA1R 0x7e1028f4:RW
EMMC_CMDTM_TM_DAT_DIR_CLR 0xffffffef
DMA0_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
V3D_DBQHLT_MASK 0xffffffff
SD_SB_INHIBIT_LA_SET 0x00000100
A2W_PLLC_CORE2R_WIDTH 10
USB_DFIFO10_MASK 0xffffffff
IC0_SRC1_WIDTH 32
I2C_SPI_SLV_CR_EN_LSB 0
UART_LCR_STB_MSB 2
HDMI_READ_POINTERS_DRFT_HOLD_WR_LSB 23
DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
MPHI_TXAXICFG_TXNPRIO_RESET 0x0
MS_SEMA_10_MASK 0x00000001
A2W_SMPS_L_SCA_ANA_CLR 0xfffff000
MPHI_C0INDDB_MTERM_RESET 0x0
SD_CS_STBY_BITS 3:3
DMA5_TI_BURST_LENGTH_SET 0x0000f000
V3D_BPOA_WIDTH 32
APERF1_BW0_CTRL_EN_SET 0x40000000
DMA11_TI_SRC_IGNORE_CLR 0xfffff7ff
PCM_CS_A_RXF_BITS 22:22
DMA12_CS_ABORT_BITS 30:30
CM_INTEN_FLOSSC_CLR 0xfffeffff
MS_SEMA_8_MASK_SET 0x00000001
SD_DQRCRC6_RISE_RESET 0x0
SD_PHYC_MDLL_TMODE_LSB 16
A2W_PLLB_ANA2R 0x7e1028f8:RW
CM_EVENT_RESUS_LSB 22
USB_DIEPCTL0_EO_FR_NUM_LSB 16
SD_SECSRT1_MASK 0xffffffff
SMI_DSR3_RSETUP_SET 0x3f000000
CCP2TX_TTC_BI_SET 0x00ff0000
DMA6_CONBLK_AD_SCB_ADDR_LSB 5
DMA4_CS_PAUSED_CLR 0xffffffef
VEC_CGMSAE_TOP_DATA 0x7e806054:RW
GP_LEN1_WIDTH 32
SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_BITS 15:8
CCP2RDSA1 CCP2_BASE_ADDRESS + 0x220:RW
GRTMPM_MASK 0xFFFFFF00
USB_DFIFO4_WIDTH 32
AVE_OUT_STATUS_VBACK_PORCH_LSB 8
EMMC_SPI_INT_SPT 0x7e3000f0:RW
PCMCS_RXSEX (1 << 23)
CM_ARMDIV_WIDTH 13
A2W_PLLC_CORE2_DIV_LSB 0
I2C_SPI_SLV_DR_TXFF_CLR 0xfffbffff
USB_DOEPCTL0_DIS_RESET 0x0
USB_GUSBCFG_ULPI_AUTO_RES_RESET 0x0
DMA14_CS_INT_LSB 2
L2_CONT_OFF_l2_flush_core_limit_BITS 23:20
HD_HDM_CTL_CECRXD_CLR 0xfffffdff
PCM_INTSTC_A_TXERR_LSB 2
EMMC_CONTROL0_HCTL_HS_EN_LSB 2
UART_LSR_PE_MSB 2
PM_PADS4_WIDTH 6
A2W_PLLD_CORER_MASK 0x000003ff
CM_PCMCTL_SRC_BITS 3:0
USB_DIEPTXF3_WIDTH 32
GP_FSEL2_RESET 0000000000
HD_MAI_THR_DREQHIGH_RESET 0x1
HDMI_PCI_MASK_SET (HDMI_BASE_ADDRESS + 0x340) + 0x28:RW
PM_PADS2_DRIVE_CLR 0xfffffff8
DMA15_TI_DEST_IGNORE_CLR 0xffffff7f
A2W_PLLA_ANA_KAIP_KA_SET 0x00000700
I2C0_FIFO_MASK 0x000000ff
AVE_IN_STATUS_FRAME_RATE_LSB 8
HDMI_TX_PHY_TX_PHY_PLL_CFG_MASK 0xc3fbffff
CM_PULSECTL_MASK 0x000003b3
SMICS_CLEARFIFO 4
ASB_H264_M_CTRL_FULL_BITS 3:3
A2W_PLLH_ANA_KAIP_KA_CLR 0xfffff8ff
DMA14_TI_DEST_INC_SET 0x00000010
DMA_ENABLE_MASK 0x00007fff
SD_SECEND2_ADDR_LS_RESET 0xfff
DMA2_DEST_AD_D_ADDR_BITS 31:0
GP_EDS1_RESET 0000000000
EMMC_HWCAP0_TCLKUNIT_LSB 7
L2_CONT_OFF_l2_flush_flush_limit_LSB 16
MPHI_C0INDDB_MTERM_SET 0x10000000
DMA0_CS_END_BITS 1:1
L1_D0_RD_HITS_MASK 0000000000
PIXELVALVE2_VC_MASK 0x007fffff
ARM_BD_OWN0 0x00000003
ARM_BD_OWN1 0x0000000C
ARM_BD_OWN2 0x00000030
ARM_BD_OWN3 0x000000C0
DMA1_CS_DREQ_SET 0x00000008
SMI_CS_SETERR_RESET 0x0
OTP_MACROVISION_START_BIT 18
USB_DOEPCTL0_SET_D1_PID_BITS 29:29
GP_GPTEST_SPARE_LSB 1
DMA9_NEXTCONBK_WIDTH 32
HD_MAI_CTL_WHOLSMP_RESET 0x0
HDMI_MISC_CONTROL 0x7e9020e4:RW
SH_HCFG_WIDE_EXT_BUS_CLR 0xfffffffb
USB_GINTMSK_P_TXF_EMP_BITS 26:26
UART_MSR_CTS_SET 0x00000010
DMA11_DEST_AD_D_ADDR_CLR 0x00000000
L1_D0_RD_SNOOPS 0x7ee02144:RO
MS_SEMA_15_WIDTH 1
USB_DOEPDMAB6_WIDTH 32
V3D_SRQUA 0x7ec00000 +0x0434:RW
CSI2_RDEA1 CSI2_BASE_ADDRESS + 0x224:RW
ARM_2_MAIL1_STA (0x7E00B000 +0xA00)+0xB8:RW
EMMC_IRPT_MASK_CEND_ERR_BITS 18:18
CM_SMICTL_FRAC_MSB 9
V3D_SRQUL 0x7ec00000 +0x0438:RW
USB_DTXFSTS0_SPC_AVAIL_SET 0xffff0000
SD_SECSRT3_EN_RESET 0x0
HD_MAI_THR_RESET 0x01010101
SCALER_DISPLIST1_WIDTH 32
CM_DSI0EDIV_MASK 0x0000fff0
CM_PLLTCNT3_CNT_MSB 23
L1_IC1_PRIORITY_IC1_APRIORITY0_LSB 0
CM_PLLC_LOADCORE0_BITS 0:0
GP_EDS1_EDSn32_BITS 31:0
DSI0_TST_MON_MASK 0x000000ff
SH_EDM_READ_THRESHOLD_BITS 18:14
OTP_BOOT_SIGNING_KEY_ROW (((((8 +4)+4)+1)+1)+1)
VEC_CGMSAE_TOP_DATA_WIDTH 32
HDMI_RAM_GCP_5_RESET 0000000000
SD_DQRCRC13_MASK 0xffffffff
DC_MAXCTABLE_OFFSET(t) MACRO
HDMI_RAM_PACKET_7_8 0x7e90251c:RW
I2C_SPI_SLV_RSR_UE_MSB 1
SCALER_DISPECTRL_CB_NE_CTRL_BITS 31:29
USB_HPRT_CONN_STS_MSB 0
CM_TD0CTL_GATE_SET 0x00000040
A2W_PLLB_DIG3_RESET 0x00000004
SLIM_DCC6_PA1_MASK 0x00ffff3f
SCALER_DISPSTAT_DMA_ERR_BIT2_CLR 0x0000007f
I2C_SPI_SLV_CR_WIDTH 17
SD_DQLCRC13_FALL_MSB 15
CM_PLLC_HOLDCORE0_LSB 1
PM_RSTC_QRCFG_LSB 12
EMMC_SLOTISR_VER_SDVERSION_BITS 23:16
USB_DOEPCTL0_ENA_RESET 0x0
L1_L1_SANDBOX_START0 0x7ee02800:RW
L1_L1_SANDBOX_START1 0x7ee02808:RW
L1_L1_SANDBOX_START2 0x7ee02810:RW
L1_L1_SANDBOX_START3 0x7ee02818:RW
L1_L1_SANDBOX_START4 0x7ee02820:RW
L1_L1_SANDBOX_START5 0x7ee02828:RW
L1_L1_SANDBOX_START6 0x7ee02830:RW
MPHI_VERSION 0x7e006054:RO
CM_CCP2CTL_FRAC_LSB 9
EMMC_IRPT_MASK_SDOFF_ERR_SET 0x00800000
INTERRUPT_SOFTINT_OFFSET 32
USB_GPVNDCTL_DIS_ULPI_DRVR_MSB 31
SMI_DSW0_WPACE_MSB 14
TB_TASK_TEXT_FLAG_MSB 16
USB_DIEPCTL0_NAK_STS_SET 0x00020000
USB_GRXSTSP_DEV_BCNT_MSB 14
APERF0_BW2_CTRL_LATHALT_MSB 28
SLIM_DCC1_CON_WIDTH 32
MS_SEMA_9_MASK 0x00000001
SH_CMD_BUSY_CMD_LSB 11
PCM_TXC_A_CH2POS_MSB 13
HDMI_DVO_TIMING_ADJUST_D_MASK 0xffffffff
V3D_RFC_MASK 0x000000ff
SMI_DSR2_RSETUP_BITS 29:24
V3D_PCTR15_WIDTH 32
SMI_CS_INTT_CLR 0xfffffbff
HDMI_CPU_MASK_SET_WIDTH 32
USB_GNPTXFSIZ_IN_EP_TXF0_DEP_SET 0xffff0000
HDMI_RAM_GCP_5_MASK 0xffffffff
APERF1_BW1_CTRL_LATHALT_RESET 0x0
MS_ICSET_0_MASK 0x00000001
HDMI_RAM_PACKET_10_0_MASK 0xffffffff
DMA4_TI_PERMAP_CLR 0xffe0ffff
DMA5_DEBUG_VERSION_LSB 25
DMA7_TI_SRC_DREQ_SET 0x00000400
CCP2TX_TSC_TSM_SET 0x0000000f
USB_DOEPINT0_BACK2BACK_SETUP_MSB 6
SLIM_DMA_DC_STAT_1_RESET 0000000000
AVE_IN_BUF0_ADDRESS_BUF0_ADDR_CLR 0x00000000
EMMC_FORCE_IRPT_WRITE_RDY_LSB 4
FPGA_DCM_CTRL_PERI_EN_SET 0x0f000000
SD_DQLCRC14_RISE_CLR 0x0000ffff
HDCP_KEY_CTL_RESET 0000000000
CM_INTEN_FGAINB_LSB 11
CAM0_CAMDBG0 0x7e8000f0:RW
SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_LSB 0
CAM0_CAMDBG2 0x7e8000f8:RW
CAM0_CAMDBG3 0x7e8000fc:RW
HDMI_PERT_LFSR_PRELOAD_RESET 0000000000
SMICS_PVMODE 12
SD_PHYC_WIDTH 25
EMMC_FORCE_IRPT_CARD_OUT_BITS 7:7
ASB_V3D_M_CTRL_WCOUNT_MSB 23
MS_SEMA_2_RESET 0000000000
RNG_DATA_MASK 0xffffffff
ASB_H264_M_CTRL_RCOUNT_BITS 13:4
DMA9_CS_RESET_LSB 31
PM_PADS4_SPARE_SET 0x00000010
SH_CMD_FAIL_FLAG_SET 0x00004000
L2_FLUSH_STA_RESET 0000000000
USB_DIEPINT0_TX_FIFO_UNDRN_RESET 0x0
SD_DQLCRC13_FALL_BITS 15:0
DMA1_CS_RESET 0000000000
PCM_INTEN_A_RXERR_BITS 3:3
PWMCTL_RPTL(n) MACRO
HDMI_PERT_INSERT_ERR_SEP 0x7e902084:RW
MS_SEMA_27_MASK 0x00000001
MS_IREQ_1_MASK 0xffffffff
HDMI_RAM_PACKET_6_2_RESET 0000000000
AVE_IN_CTRL_EN_OVERRUN_ABORT_BITS 15:15
HDMI_CP_INTEGRITY_CFG 0x7e902050:RW
MS_SEMA_1_MASK_CLR 0xfffffffe
NIOREQ 0x7e008000 + 0x0:RW
DMA4_SOURCE_AD 0x7e00740c:RO
ASB_ISP_S_CTRL_EMPTY_BITS 2:2
HDMI_RAM_GCP_3_WIDTH 32
HDMI_MBIST_TM_WIDTH 24
CM_CCP2CTL_BUSY_MSB 7
SD_DQRCRC3_RISE_RESET 0x0
USB_HPRT_LN_STS_RESET 0x0
PCM_CS_A_WIDTH 26
DMA6_SOURCE_AD 0x7e00760c:RO
USB_DCFG_DEV_ADDR_CLR 0xfffff80f
USB_GGPIO_GPI_LSB 0
DMA14_CONBLK_AD_RESET 0000000000
SMI_DSR0_RSETUP_SET 0x3f000000
SD_SD_T_RCD_RESET 0x8
DMA8_CS_PRIORITY_SET 0x000f0000
DMA12_CS_ABORT_LSB 30
SD_DQRCRC2_RISE_BITS 31:16
GP_FSEL3_FSEL36_MSB 20
CAM0_CAMDBG3_MASK 0xffffffff
USB_GHWCFG4_EN_VBUSVALID_FILTER_RESET 0x0
USB_DIEPCTL0_DIS_CLR 0xbfffffff
USB_DIEPDMAB10 0x7e980a58:RW
USB_DIEPDMAB11 0x7e980a78:RW
USB_DIEPDMAB12 0x7e980a98:RW
USB_DIEPDMAB13 0x7e980ab8:RW
HDMI_PCI_MASK_STATUS (HDMI_BASE_ADDRESS + 0x340) + 0x24:RW
USB_DIEPDMAB15 0x7e980af8:RW
SD_SB_COLBITS_LSB 0
DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
GP_FSEL5_FSEL57_CLR 0xff1fffff
HDMI_RAM_PACKET_12_1_WIDTH 32
DMA11_CS_INT_LSB 2
SMI_DSR3_RSTROBE_LSB 0
PM_XOSC_WIDTH 1
IS_ALIAS_L1L2_NONALLOCATING(x) MACRO
GP_SEN1_WIDTH 22
FPGA_STATUS0_NAND_RNB_BITS 6:6
SD_MR_HI_Z_CLR 0xdfffffff
AVE_IN_CTRL_BUF1_IRQ_EN_BITS 2:2
USB_GINTMSK_CUR_MOD_MSB 0
SH_VDD_WIDTH 1
SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_SET 0x0000000c
AVE_OUT_Y_COEFF_BLUE_COEFF_SET 0x000003ff
EMMC_IRPT_EN_INT_A_BITS 9:9
EMMC_DATA 0x7e300020:RW
CAM0_CAMCLK_WIDTH 32
PM_GRAFX_V3DRSTN_LSB 6
CM_GP2CTL_BUSYD_BITS 8:8
DMA4_TI_PERMAP_LSB 16
CM_SMICTL_ENAB_LSB 4
USB_DOEPDMA14_MASK 0xffffffff
CM_OSCCOUNT_NUM_SET 0x00ffffff
I2C_SPI_SLV_CR_BRK_MSB 7
USB_GAHBCFG_DMA_EN_MSB 5
SD_DMRCRC0_LOW_LSB 0
SMI_DSW0_WSETUP_SET 0x3f000000
GP_FSEL1_RESET 0000000000
I2C_SPI_SLV_DR_RXFLEVEL_CLR 0x07ffffff
SD_SA_PGEHLD_IDL_MSB 15
DMA14_CS_ACTIVE_CLR 0xfffffffe
HD_MAI_CTL_DLATE_LSB 15
APERF0_BW1_CTRL_ID_EN_MSB 29
DMA_ENABLE_EN11_LSB 11
DMA8_CS_ABORT_SET 0x40000000
FPGA_MB_BASE 0x7e20b700
L1_L1_SANDBOX_START3_MASK 0x3fffffff
PWM_CTL_PWEN2_MSB 8
CM_PLLB_ANARST_LSB 8
HD_MAI_THR_DREQHIGH_LSB 8
FPGA_MB_SDC_ISP_FREQ 0x7e20b734:RO
DMA0_CS_DISDEBUG_SET 0x20000000
HDMI_HORZA_MASK 0x00007fff
CM_SYSDIV_RESET 0x00001000
DMA9_CS_DREQ_MSB 3
CM_OTPCTL_ENAB_BITS 4:4
DMA5_DEBUG_DMA_ID_CLR 0xffff00ff
L1_L1_SANDBOX_START1_START_ADDR_CLR 0xc000001f
USB_DIEPCTL0_USB_ACT_EP_BITS 15:15
USB_GINTMSK_OTG_INT_SET 0x00000004
GP_FSEL0_WIDTH 30
GP_FEN1_FENn32_LSB 0
A2W_PLLA_PER_BYPEN_BITS 9:9
USB_HCINT0 0x7e980508:RW
DMA10_CS_PANIC_PRIORITY_MSB 23
USB_HCINT2 0x7e980548:RW
USB_HCINT3 0x7e980568:RW
USB_HCINT4 0x7e980588:RW
USB_HCINT5 0x7e9805a8:RW
USB_HCINT6 0x7e9805c8:RW
USB_HCINT7 0x7e9805e8:RW
USB_HPTXFSIZ_MASK 0xffffffff
USB_GOTGCTL_HNP_REQ_CLR 0xfffffdff
DMA12_CS_DREQ_STOPS_DMA_SET 0x00000020
HDMI_RAM_PACKET_10_0_RESET 0000000000
SMI_A_DEVICE_MSB 9
I2C_SPI_SLV_IFLS_TXIFPSEL_SET 0x000001c0
A2W_PLLD_ANA_SCTL_SEL_LSB 0
A2W_PLLD_DSI0R_MASK 0x000003ff
I2C_SPI_SLV_TDR_DATA_SET 0x000000ff
SH_RSP1_CID_CSD_MSB 31
PCM_RXC_A_CH1WEX_MSB 31
DMA2_TI_SRC_WIDTH_LSB 9
CM_GP0CTL_BUSY_LSB 7
SD_SECEND3_ADDR_MS_RESET 0x0
PM_IMAGE_ENAB_MSB 12
DMA1_TI_DEST_WIDTH_LSB 5
DMA12_TI_DEST_DREQ_BITS 6:6
SMI_DSR1_MODE68_MSB 23
EMMC_INTERRUPT_CTO_ERR_MSB 16
CM_PCMDIV_WIDTH 24
HDMI_RAM_PACKET_12_4_MASK 0xffffffff
SYSAC_JPEG_PRIORITY_N_PRIORITY_BITS 3:0
USB_DIEPTSIZ0_PKT_CNT_CLR 0xe007ffff
A2W_XOSC_CTRL_PLLCEN_SET 0x00000001
EMMC_INTERRUPT_INT_C_LSB 11
DMA2_TI_TDMODE_MSB 1
DMA12_CS_END_MSB 1
CAM0_CAMIDC_WIDTH 32
PCM_MODE_A_FRXP_MSB 25
AVE_OUT_STATUS_VSYNC_CLR 0xfffffdff
ASB_ISP_M_CTRL_CLR_REQ_SET 0x00000001
SYSAC_DUMMY_STATUS_IDLE_CLR 0xfffffffe
AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_BITS 11:0
SD_SE_RL_BITS 25:20
CSI2_RBC0 CSI2_BASE_ADDRESS + 0x118:RW
CSI2_RBC1 CSI2_BASE_ADDRESS + 0x218:RW
SMI_DSW0_WSTROBE_MSB 6
USB_HAINTMSK 0x7e980418:RW
DSI0_HS_CLT1_RESET 0000000000
SH_RSP1_RESET 0000000000
HDMI_HBR_AUDIO_PACKET_HEADER_RESET 0x00000009
DMA0_CS_ACTIVE_LSB 0
CM_INTEN_BADPASS_SET 0x00040000
USB_GPVNDCTL_REG_WR_BITS 22:22
DMA0_DEBUG_RESET 0000000000
ULSR 0x7e201000 + 0x14:RW
CCP2TX_TPC_TPT_MSB 15
A2W_PLLB_ANA_SCTL_SEL_MSB 2
USB_GUSBCFG_OTG_I2C_SEL_RESET 0x0
TXP_CTRL_FORMAT_MSB 11
HDCP_KEY_CTL_DISHDCP_MSB 2
USB_GRXSTSP_DEV_FN_CLR 0xfe1fffff
DMA4_CS_PANIC_PRIORITY_CLR 0xff0fffff
MPHI_OUTDS_WORDS_RESET 0x0
MPHI_C1INDDA_START_MSB 31
USB_GINTMSK_USB_SUSP_BITS 11:11
DMA8_NEXTCONBK_ADDR_BITS 31:5
DMA4_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
FPGA_CTRL0_SPARE_OUT_MSB 31
A2W_PLLB_DIG1_WIDTH 24
HDMI_RAM_PACKET_7_1_MASK 0xffffffff
V3D_PCTRS5 0x7ec006ac:RW
USB_DIEPINT0_IN_TKN_EP_MIS_MSB 5
L1_IC1_FLUSH_S_RESET 0000000000
SD_CS_RESTRT_LSB 0
HDMI_RAM_PACKET_1_0_MASK 0xffffffff
CM_TDCLKEN_PLLBDIV2_BITS 5:5
DMA1_DEBUG_DMA_ID_LSB 8
MS_APB_ID 0x4d554c54
USB_DOEPCTL0_EO_FR_NUM_MSB 16
A2W_PLLD_ANA0 0x7e102050:RW
L1_L1_SANDBOX_START6_CTRL_MSB 0
A2W_PLLD_ANA2 0x7e102058:RW
A2W_PLLD_ANA3 0x7e10205c:RW
DPHY_CSR_BYTE0_MASTER_DLL_OUTPUT 0x7ee0702c:RW
AVE_OUT_CTRL_INVERT_VSYNC_LSB 15
DMA10_TXFR_LEN_MASK 0x0000ffff
SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_MSB 3
ASB_H264_S_CTRL 0x7e00a018:RW
A2W_PLLC_CORE0_CHENB_BITS 8:8
DMA14_TI_MASK 0x03fffff9
USB_GHWCFG4_EN_VBUSVALID_FILTER_BITS 21:21
USB_DIEPDMAB3_MASK 0xffffffff
EMMC_HWCAP1_DATA_RETUNE_SET 0x0000c000
DMA13_TI_BURST_LENGTH_SET 0x0000f000
SD_DQRCRC12_FALL_SET 0x0000ffff
MS_ICSET_0_RESET 0000000000
SCALER_DISPSTAT0_MASK 0xffffffff
SD_SF_MDLL_CAL_BITS 8:0
PIXELVALVE0_DSI_HACT_ACT_MASK 0x0000ffff
SYSAC_JPEG_PRIORITY_N_PRIORITY_SET 0x0000000f
SYSAC_V3D_LIMITER_ENABLE_BITS 0:0
DMA_TI_D_DREQ (1<<6)
PM_GRAFX_ISPOW_BITS 2:2
DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
I2C_SPI_SLV_FR_RXFLEVEL_BITS 15:11
SPI_CS_INTR_MSB 10
GP_HEN0_RESET 0000000000
HDMI_RAM_PACKET_8_8_RESET 0000000000
USB_DOEPINT6_MASK 0xffffffff
SD_DMRCRC1_LOW_MSB 15
EMMC_IRPT_MASK_DATA_DONE_BITS 1:1
EMMC_INTERRUPT_CARD_IN_BITS 6:6
CM_ISPCTL_ENAB_BITS 4:4
SLIM_DCC2_PA1_RESET 0000000000
SMI_DSR0_MASK 0xffffffff
A2W_PLLH_AUX_MASK 0x000003ff
L2_WR_BACKS_MASK 0xffffffff
ASB_H264_M_CTRL_WCOUNT_MSB 23
DMA12_SOURCE_AD_S_ADDR_MSB 31
V3D_PCTRS15_WIDTH 5
USB_DTXFSTS15_WIDTH 32
ARM_AIS0_OPPEMPTY 0x00000040
MS_SEMA_23_MASK_SET 0x00000001
USB_DIEPINT0_WIDTH 32
ASB_V3D_S_CTRL_WCOUNT_LSB 14
USB_GNPTXSTS_TX_Q_TOP_RESET 0x0
V3D_CT00RA0_WIDTH 32
A2W_PLLB_ANA_KAIP_KA_SET 0x00000700
SLIM_DCC5_PA0_MASK 0x00ffff1f
CM_DSI0HSCK_WIDTH 1
DMA15_CS_ABORT_BITS 30:30
DMA5_TI_DEST_WIDTH_CLR 0xffffffdf
DMA3_TI_BURST_LENGTH_LSB 12
DMA2_TI_WAIT_RESP_MSB 3
DMA8_CS_RESET 0000000000
SMI_DSR3_RHOLD_CLR 0xffc0ffff
A2W_PLLD_CORER_RESET 0x00000100
EMMC_BLKSIZECNT_BLKSIZE_MS1_BITS 15:15
EMMC_IRPT_EN_INT_B_SET 0x00000400
MS_SEMA_24_MASK_BITS 0:0
USB_DIEPDMAB15_MASK 0xffffffff
DMA10_DEST_AD_D_ADDR_BITS 31:0
MS_SEMA_0_WIDTH 1
DMA11_CS_RESET_MSB 31
APERF1_BW0_WTRANS_MASK 0xffffffff
VCE_STATUS_BUSYBITS_MASK 0xffff
DMA5_CS_DREQ_STOPS_DMA_SET 0x00000020
DMA_INT_STATUS_INT12_BITS 12:12
VCE_REGISTERS_OFFSET 0x20000
DMA6_TXFR_LEN_XLENGTH_MSB 15
MPHI_AXIPRIV_HSPECEN_MSB 8
CM_DSI1PDIV_MASK 0x00001000
USB_DIEPCTL13_MASK 0xffffffff
USB_GINTMSK_SESS_REQ_INT_SET 0x40000000
MPHI_CTRL_REQ_SOFT_RST_BITS 16:16
CAM0_CAMCTL_WIDTH 32
DMA11_DEBUG_FIFO_ERROR_CLR 0xfffffffd
MPHI_INTCTRL_OMFUFLW_BITS 12:12
DMA10_CS_PAUSED_CLR 0xffffffef
L1_L1_SANDBOX_START3_START_ADDR_MSB 29
EMMC_FORCE_IRPT_OEM_ERR_SET 0xc0000000
DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
A2W_PLLA_DSI0_CHENB_LSB 8
VEC_CONFIG1_MASK 0xffffffff
PM_PXLDO_CTRL_LSB 0
PM_PADS3_HYST_LSB 3
EMMC_FORCE_IRPT_DTO_ERR_CLR 0xffefffff
CM_UARTDIV_DIV_CLR 0xffc00000
SH_HSTS_DATA_FLAG_SET 0x00000001
EMMC_IRPT_EN_CCRC_ERR_CLR 0xfffdffff
CM_PULSECTL_SRC_MSB 1
SD_DQLCRC14_RISE_LSB 16
DMA8_NEXTCONBK_WIDTH 32
EMMC_IRPT_EN_SDOFF_ERR_BITS 23:23
MPHI_C1INDCF_EMPTY_RESET 0x0
SD_TMC_TS_SET 0x00000002
CM_TSENSDIV_DIV_LSB 12
PWMCTL_SBIT2 11
DMA12_TI_DEST_IGNORE_LSB 7
ASB_ISP_S_CTRL_FULL_SET 0x00000008
SH_EDM_FIFO_COUNT_BITS 8:4
SPI_CS_RESET 0000000000
DMA4_DEBUG_VERSION_MSB 27
STC2 0x7e003014:RW
DMA7_CS_INT_LSB 2
DMA0_STRIDE_S_STRIDE_BITS 15:0
CM_INTEN_BURSTDONE_MSB 23
USB_DCTL_CGNP_IN_NAK_BITS 8:8
EMMC_INTERRUPT_READ_RDY_SET 0x00000020
SCALER_DISPCTRL_DSP3_MUX_BITS 19:18
SLIM_EA0_RESET 0000000000
CCP2TX_TPC_TPP_LSB 4
CM_SLIMCTL_ENAB_BITS 4:4
DMA0_SOURCE_AD_S_ADDR_BITS 31:0
CM_LOCK_FLOCKD_SET 0x00000800
I2C_SPI_SLV_DR_TXFE_LSB 20
CM_PLLA_RESET 0x00000300
DMA2_CS_PANIC_PRIORITY_CLR 0xff0fffff
DMA10_TI_PERMAP_CLR 0xffe0ffff
A2W_PLLB_FRAC_FRAC_BITS 19:0
MS_ICCLR_0_WIDTH 1
DMA10_NEXTCONBK_ADDR_LSB 5
A2W_XOSC0_WIDTH 24
PIXELVALVE1_STAT 0x7e20702c:RW
CM_EVENT_GAIND_LSB 3
USB_GHWCFG4_NUM_PERIO_EPS_SET 0x0000000f
A2W_PLLH_RCAL_BYPEN_LSB 9
CM_PERIACTL_GATE_MSB 6
PM_SMPS_CTRLEN_CLR 0xfffffffe
A2W_SMPS_CTLA1_RESET 0000000000
DMA8_CS_DREQ_STOPS_DMA_BITS 5:5
SD_SC_T_RFC_BITS 30:24
CAM1_CAMCLK_RESET 0x00000002
USB_DIEPDMAB5_WIDTH 32
A2W_PLLA_DSI0R_MASK 0x000003ff
CM_VECCTL_FRAC_MSB 9
PCM_GRAY_FLUSH_BITS 2:2
EMMC_FORCE_IRPT_CBAD_ERR_SET 0x00080000
CM_PULSECTL_BUSYD_SET 0x00000100
HDMI_RAM_PACKET_9_5_MASK 0xffffffff
DSI1_TST_SEL_WIDTH 32
AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_BITS 31:31
SYSAC_V3D_LIMITER_ENABLE_CLR 0xfffffffe
A2W_SMPS_B_STAT_BSTPWMB_CLR 0xfffffeff
A2W_PLLC_CORE0R 0x7e102e20:RW
HDMI_RAM_PACKET_3_4_MASK 0xffffffff
PWM_CTL_RPTL2_MSB 10
SD_DQRCRC12_FALL_BITS 15:0
DMA11_TI_WAITS_BITS 25:21
V3D_PCTRS5_WIDTH 5
A2W_PLLH_FRACR 0x7e102a60:RW
USB_HCCHAR0_EP_DIR_MSB 15
A2W_PLLC_ANA1R_WIDTH 24
CM_BURSTCNT_CNT_MSB 23
MPHI_OUTDDB_LENGTH_SET 0x000fffff
SD_DQRCRC14_WIDTH 32
I2C_SPI_SLV_DR_RXDMAPREQ_SET 0x00001000
SMI_DSW1_WPACEALL_SET 0x00008000
USB_DOEPINT0_IN_TKN_EP_MIS_BITS 5:5
FPGA_CTRL0_DIS_BL_CLR 0xfffffffd
DMA8_TI_SRC_DREQ_SET 0x00000400
ASB_ISP_S_CTRL 0x7e00a010:RW
CM_PLLH_ANARST_BITS 8:8
HDMI_KSV_FIFO_0_WIDTH 32
TB_TASK_NUM_SET 0x0000ffff
CM_EVENT_LOSSB_BITS 6:6
SD_SECEND1_ADDR_LS_LSB 0
A2W_XOSC_PWRR_RESET 0x00000004
A2W_PLLH_DIG0R_RESET 0000000000
DMA11_DEBUG_DMA_ID_LSB 8
PCM_INTEN_A_RXR_CLR 0xfffffffd
L1_L1_SANDBOX_START5_RESET 0000000000
ST_C1_MASK 0xffffffff
USB_GHWCFG2_ARCHITECTURE_RESET 0x0
DMA2_TI_INTEN_CLR 0xfffffffe
EMMC_HWCAP0_SDMA_BITS 22:22
HD_MAI_CTL_WIDTH 16
DSI0_TA_TO_CNT_MASK 0xffffffff
A2W_PLLD_DIG1_MASK 0x00ffffff
SMI_DSR3_FSETUP_MSB 22
PM_PXLDO_MASK 0x0003ffff
DMA1_CS_ERROR_SET 0x00000100
SD_DQRCRC14_FALL_RESET 0x0
AVE_OUT_STATUS_VFRONT_PORCH_CLR 0xffffff7f
HD_MAI_FMT 0x7e80801c:RW
SD_TMC_IPRD_RESET 0x0
INTERRUPT_AUXIO ((64) + 29 )
DMA14_CS_PANIC_PRIORITY_MSB 23
AVE_IN_STATUS_BUF1_COMPL_LSB 2
USB_DIEPTSIZ8_MASK 0xffffffff
EMMC_STATUS_CARD_INSERT_BITS 16:16
CM_EVENT_FGAINB_MSB 11
USB_DIEPDMAB14_MASK 0xffffffff
CM_INTEN_FGAINC_BITS 12:12
A2W_PLLB_ANA_SCTL_RESET 0000000000
EMMC_HWCAP0_V1_8_SET 0x04000000
VCE_SEMA_SET 0x7f000000 + 0x140028:RW
USB_HCINT0_XFER_COMPL_RESET 0x0
EMMC_IRPT_MASK_OEM_ERR_LSB 30
IC1_MASK7_MASK 0x77777777
SD_PHYC_BIST_MODE_BITS 8:8
DMA_ENABLE_EN3_CLR 0xfffffff7
EMMC_IRPT_MASK_READ_RDY_BITS 5:5
GROPCTR_TU0_SAME_BANK_STALL 0x0F
CAM1_CAMIDC_RESET 0000000000
SD_VIN_WRITE_CLR 0xfffeffff
EMMC_HWCAP0_V3_0_BITS 25:25
V3D_BPOS_WIDTH 32
VCE_STATUS_REASON_POS 16
APHY_CSR_DDR_PLL_GLOBAL_RESET 0x7ee06024:RW
FPGA_STATUS0_SW_SPI_SPI_IN_LSB 7
DMA2_DEBUG_OUTSTANDING_WRITES_BITS 7:4
DMA15_TI_SRC_INC_SET 0x00000100
PM_IMAGE_ISPRSTN_SET 0x00000100
DMA9_CS_PRIORITY_SET 0x000f0000
IMASK0_1 0xffffffff:RW
UART_LSR_BI_LSB 4
PIARBCTL_CAM 0x7e80a000:RW
TS_TSENSCTL_CLR_INT_CLR 0xffffff7f
DMA12_TI_WAIT_RESP_MSB 3
USB_GHWCFG4_HSPHY_DWIDTH_CLR 0xffff3fff
PM_SPARER_WIDTH 24
GP_GPTEST 0x7e2000b0:RW
A2W_SMPS_L_SPV_RESET 0000000000
A2W_SMPS_A_MODER_RESET 0000000000
USB_HCCHAR0_LSPD_DEV_CLR 0xfffdffff
USB_DCTL_SFT_DISCON_SET 0x00000002
I2C_SPI_SLV_IFLS 0x7e214014:RW
CM_PERIACTL_MASK 0x00000040
A2W_PLLD_ANA_STAT_DATA_SET 0x00000fff
SD_DQRCRC14_RISE_SET 0xffff0000
VIDEOCORE_NUM_GPIO_PINS 70
SMI_CS_TXD_LSB 28
A2W_HDMI_CTL_RCALR_RESET 0x00010000
GP_SET1_SETn32_BITS 31:0
USB_GOTGCTL_SES_REQ_SCS_CLR 0xfffffffe
USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_CLR 0xfcffffff
SPI_TX_DMA ( 6*(1<<16))
CCP2TX_TAC_BPD_BITS 2:2
APERF1_BW0_CTRL_RESET_MSB 31
TS_TSENSCTL_REGULEN_BITS 26:26
A2W_PLLD_ANA_SSCL_MASK 0x003fffff
EMMC_IRPT_EN_DMA_SET 0x00000008
ASB_H264_S_CTRL_WCOUNT_LSB 14
CM_SYSDIV_DIV_LSB 12
USB_HCCHAR0_EP_NUM_SET 0x00007800
VCE_CONTROL_SINGLE_STEP 3
A2W_PLLD_ANA2_MASK 0x00ffffff
USB_DIEPTXF1_FIFO_SIZE_MSB 31
CM_DSI1ECTL_BUSY_MSB 7
DMA13_CS_END_BITS 1:1
SD_SECSRT3_WIDTH 32
CM_SDCCTL_UPDATE_LSB 17
I2C_SPI_SLV_IMSC_OEIM_CLR 0xfffffff7
CAM1_CAMIDCA 0x7e801140:RW
HDMI_CP_TST_MASK 0x002001ff
CAM1_CAMIDCD 0x7e801144:RW
DMA14_CS_DREQ_SET 0x00000008
PCMCS_TXERR (1 << 15)
PWM_CTL_POLA1_CLR 0xffffffef
EMMC_IRPT_EN_TUNE_ERR_LSB 26
MPHI_INTCTRL_WIDTH 21
DMA11_TXFR_LEN_XLENGTH_SET 0x0000ffff
PCM_CS_A_TXERR_MSB 15
DMA1_CS_DISDEBUG_SET 0x20000000
CM_DSI0HSCK 0x7e101120:RW
SH_HSTS_CRC16_ERROR_LSB 5
DMA8_NEXTCONBK 0x7e00781c:RO
SD_MR_WDATA_MSB 15
PCM_INTSTC_A_TXW_SET 0x00000001
DMA8_CS_DISDEBUG_CLR 0xdfffffff
SPI_CS_RXD_LSB 17
UART_MSR_DCD_LSB 7
GRSCS 0x1A005800 + 0x00:RW
HDMI_RAM_PACKET_4_4_WIDTH 32
DMA10_CS_PANIC_PRIORITY_LSB 20
USB_HCINT0_STALL_MSB 3
GP_FSEL1_FSEL11_BITS 5:3
EMMC_IRPT_EN_ATA_ERR_LSB 29
L1_L1_SANDBOX_END1_MASK 0x3fffffe0
PM_IMAGE_ISPOW_SET 0x00000004
USB_HPRT_ENA_LSB 2
HDMI_CTS_PERIOD_0_WIDTH 32
SD_MR_TIMEOUT_SET 0x40000000
PCMCS_RXTHR_EMPTY (0 << 7)
DMA2_DEBUG_DMA_ID_CLR 0xffff00ff
SLIM_DCC5_PROT_WIDTH 32
MS_VPUSEMA_1_VPUSEMA_1_CLR 0xfffffffe
PWM_CTL_MODE1_MSB 1
TS_TSENSCTL_THOLD_BITS 17:8
MPHI_INTSTAT_RX1MEND_SET 0x00000100
L1_IC0_CONTROL_RAS_DISABLE_CLR 0xffffffef
EMMC_STATUS_CARD_DETECT_MSB 18
V3D_CT01RA0 0x7ec00000 +0x011c:RW
CM_VECCTL_ENAB_LSB 4
USB_DOEPCTL0_SET_D0_PID_MSB 28
CM_EVENT_WRFAIL_CLR 0xfff7ffff
APHY_CSR_DESCRIPTION "SDRAM Adress (pin) control"
HDMI_DETECTED_HORZB_MANUAL_HFP_MSB 9
TH0STPC 0x18011000 + 0x08:RW
HDMI_RAM_PACKET_5_8_MASK 0xffffffff
MAX_GPIO_NUM 2
CM_ISPCTL_BUSY_LSB 7
MPHI_C1INDCF_EMPTY_LSB 31
DMA4_DEBUG_RESET 0000000000
HDMI_DETECTED_VERTA1_MANUAL_VSP1_MSB 24
GROPCTR_FESTALLPREFETCH 0x0B
DMA4_CS_INT_LSB 2
I2C_SPI_SLV_DR_RXFF_CLR 0xfff7ffff
DMA15_TI_SRC_IGNORE_BITS 11:11
HD_VID_CTL_VPOL_BITS 28:28
EMMC_FORCE_IRPT_ATA_ERR_LSB 29
HD_APB_ID 0x48444d49
DMA8_TI_SRC_INC_SET 0x00000100
CCP2TX_TAC_TPC_LSB 3
EMMC_IRPT_MASK_CBAD_ERR_LSB 19
A2W_PLLC_PER_CHENB_CLR 0xfffffeff
DMA4_DEBUG_FIFO_ERROR_LSB 1
CAM1_CAMCTL_RESET 0000000000
PM_RSTS_HADDRF_LSB 1
GP_AFEN1_AFENn32_SET 0xffffffff
GP_FSEL0_FSEL05_CLR 0xfffc7fff
A2W_SMPS_L_SPV_VOLTS_SET 0x0000001f
I2C0_C_WIDTH 16
CAM0_CAMDAT0_RESET 0x00000002
DMA_ENABLE_EN4_MSB 4
CAM0_CAMCTL_MASK 0xffffffff
CCP2TX_BASE 0x7e001000
DSI0_PHYC_txulpshs_0_sync_SET 0x00000002
ARM_MC_ERRNOOWN 0x00000100
MPHI_C1INDCF_ORUN_LSB 29
V3D_PCTRS8_WIDTH 5
PCM_MODE_A_PDME_MSB 26
EMMC_IRPT_EN_INT_C_CLR 0xfffff7ff
SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_SET 0x00000030
PM_RSTS_HADSRH_LSB 10
A2W_PLLD_CTRLR_WIDTH 18
DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
DSI1_HS_DLT5_WIDTH 32
USB_DOEPINT0_TIMEOUT_MSB 3
EMMC_EXRDFIFO_EN_RESET 0000000000
DMA11_NEXTCONBK_ADDR_SET 0xffffffe0
PIXELVALVE0_VERTA_EVEN_MASK 0xffffffff
CAM1_CAMICS_RESET 0000000000
USB_DSTS_SOF_FN_SET 0x003fff00
HD_CSC_14_13_WIDTH 32
USB_GRXFSIZ_GRXF_DEP_MSB 15
USB_GAHBCFG_H_BST_LEN_SET 0x0000001e
AVE_IN_LINE_LENGTH 0x7e910014:RW
DMA8_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
SPI_LTOH_TOH_MSB 3
ASB_V3D_M_CTRL_EMPTY_BITS 2:2
SD_DQRCRC14_RISE_MSB 31
SYSAC_HOST_PRIORITY_PRIORITY_RESET 0x0
DMA1_STRIDE_S_STRIDE_MSB 15
DSI1_TXPKT2_H_RESET 0000000000
VIDEOCORE_NUM_UART_PORTS 1
SLIM_DCC5_PA0 0x7e2102a0:RW
EMMC_IRPT_MASK_WRITE_RDY_CLR 0xffffffef
CM_EVENT_FLOSSB_CLR 0xffff7fff
DMA_ENABLE_EN10_CLR 0xfffffbff
PM_PROC_ENAB_BITS 12:12
GROPCTR_FESPMSTALL 0x0D
DMA4_TI_WAIT_RESP_CLR 0xfffffff7
I2C_SPI_SLV_FR_RXFE_LSB 1
VEC_MASK0 0x7e806204:RW
MPHI_CTRL_SOFT_RST_DNE_MSB 17
DMA4_SOURCE_AD_S_ADDR_BITS 31:0
A2W_PLLC_ANA0_RESET 0000000000
DMA3_CS_PANIC_PRIORITY_SET 0x00f00000
GP_AREN1_ARENn32_LSB 0
SD_DQRCRC1_RISE_LSB 16
SMI_DSR0_FSETUP_MSB 22
MPHI_OUTDS_VALID_MSB 30
PM_GRAFX_ENAB_MSB 12
SD_MR_ADDR_RESET 0x0
CAM0_CAMIHWIN_RESET 0000000000
USB_HCINTMSK5_WIDTH 32
SD_DQRCRC11_FALL_RESET 0x0
HDMI_READ_POINTERS_DRFT_OVERFLOW_SET 0x00080000
MS_SEMA_3_MASK_MSB 0
DMA9_CS_ERROR_CLR 0xfffffeff
GR_PSE_DEBUG_ADDR_MASK 0x00000003
VEC_CGMSAE_BOT_CONTROL 0x7e806048:RW
MS_MBOX_4_MBOX_SET 0xffffffff
DMA14_CS_PAUSED_LSB 4
L1_L1_SANDBOX_END6_RESET 0000000000
INTERRUPT_ADC ((64) + 58 )
USB_GUSBCFG_FS_INTF_BITS 5:5
PM_GNRIC_ENAB_CLR 0xffffefff
SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_BITS 3:3
CSI2_RWP0 CSI2_BASE_ADDRESS + 0x114:RW
VCE_PC_RD0 0x7f000000 + 0x140010:RW
SMI_DCS 0x7e600034:RW
TB_BOOT_OPT_TCL_SIM_BITS 3:3
DMA2_CS_END_SET 0x00000002
DMA13_TI_DEST_DREQ_SET 0x00000040
EMMC_IRPT_EN_DATA_DONE_CLR 0xfffffffd
PM_PADS2_SLEW_SET 0x00000010
CM_SDCDIV_RESET 0000000000
ARM_C1_TIMER 0x00000001
DMA5_CS_RESET_MSB 31
SYSAC_HVSM_PRIORITY_N_PRIORITY_MSB 3
DSI1_TXPKT1_H_MASK 0xffffffff
MS_MBOX_0_MBOX_CLR 0x00000000
PWMRNG(n) MACRO
EMMC_IRPT_MASK_CARD_LSB 8
USB_DOEPCTL0_DIS_MSB 30
DSI0_DISP0_CTR_RESET 0000000000
USB_DOEPINT0_EP_DISBLD_RESET 0x0
DMA0_TI_BURST_LENGTH_BITS 15:12
MS_DMA (0*(1<<16))
EMMC_CONTROL0_HCTL_LED_CLR 0xfffffffe
I2C_SPI_SLV_RSR_MASK 0x0000003f
SD_DQLCRC14_FALL_CLR 0xffff0000
DMA11_TI_BURST_LENGTH_LSB 12
USB_DIEPINT6_MASK 0xffffffff
DMA0_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
DMA9_CS_ACTIVE_BITS 0:0
TH0T3PC 0x18011000 + 0x28:RW
USB_GRSTCTL_TXF_NUM_CLR 0xfffff83f
A2W_PLLB_ANA_SSCL_LIMIT_SET 0x003fffff
FPGA_DCM_RD_DATA_DATA_LSB 0
SCALER_DISPECTRL_POSTED_STATUS_BITS 14:12
CAM1_CAMIDI0 0x7e801108:RW
CAM1_CAMIDI1 0x7e80130c:RW
MPHI_MINFS_WPTR_RESET 0x0
USB_GHWCFG4_EN_IDDIG_FILTER_RESET 0x0
AVE_IN_FRAME_NUM_WIDTH 12
DSI_TST_MON 0x7e209000 + 0x70:RW
HDMI_DETECTED_HORZB_MANUAL_HSP_MSB 19
DMA3_TI_SRC_WIDTH_BITS 9:9
VEC_CGMSAE_TOP_CONTROL 0x7e806044:RW
USB_GHWCFG2_ARCHITECTURE_BITS 4:3
CM_SDCCTL_BUSYD_LSB 8
USB_DOEPDMA5_MASK 0xffffffff
HDMI_ASYNC_RM_RATE_RATIO (HDMI_BASE_ADDRESS + 0x300) + 4:RW
SLIM_DCC1_STAT 0x7e21022c:RW
OTP_VPU_CACHE_PARITY_MASK 0xFF
A2W_PLLC_ANA_KAIP_KA_MSB 10
I2C_SPI_SLV_CR_CPHA_SET 0x00000008
DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
DMA4_CONBLK_AD 0x7e007404:RW
CAM0_CAMDBG0_MASK 0xffffffff
DMA1_TI_SRC_INC_MSB 8
PM_PXLDO_RSTPLLDR_SET 0x00020000
L1_L1_SANDBOX_START0_CTRL_CLR 0xfffffffe
USB_GI2CCTL_RW_DATA_SET 0x000000ff
A2W_PLLC_CTRL_NDIV_SET 0x000003ff
CM_V3DCTL_GATE_BITS 6:6
EMMC_INTERRUPT_WRITE_RDY_LSB 4
USB_GPVNDCTL_REG_WR_CLR 0xffbfffff
A2W_XOSC_CTRL_USBEN_MSB 2
A2W_SMPS_L_SIVR_RESET 0000000000
AUX_MU_CNTL_AUTO_RTR 0x04
EMMC_HWCAP0_ADMA2_BITS 19:19
SCALER_OLEDOFFS_MASK 0xffffffff
USB_DOEPINT11_WIDTH 32
PCMCS_INTE (1 << 12)
SH_EDM_WRITE_THRESHOLD_LSB 9
USB_DIEPCTL0_MPS_RESET 0x0
MPHI_C1INDCF_LENERR_LSB 30
CM_CAM0CTL_KILL_LSB 5
PCMCS_INTR (1 << 11)
PCMCS_INTT (1 << 10)
GP_GPTEST_RESET 0000000000
EMMC_CONTROL2_ACTO_ERR_BITS 1:1
USB_DIEPCTL0_DPID_SET 0x00010000
L1_D_CONTROL_DC_DISABLE_LSB 0
EMMC_CMDTM_TM_DAT_DIR_LSB 4
DMA13_TI_WAITS_SET 0x03e00000
SMI_DCS_START_MSB 1
A2W_PLLB_ARM_RESET 0x00000100
SMI_DSR0_RPACE_BITS 14:8
USB_HCCHAR0_EP_TYPE_BITS 19:18
USB_DOEPCTL0_STALL_BITS 21:21
DMA11_CS_DREQ_LSB 3
L1_L1_SANDBOX_PERI_BR_sandbox_bootrom_MSB 4
HDMI_SCHEDULER_CONTROL_HSYNC_PHYST_EN_BITS 16:16
USB_DOEPMSK_MASK 0xffffffff
A2W_PLLC_PER_CHENB_LSB 8
L1_IC1_CONTROL_START_FLUSH_MSB 1
PM_PADS4_POWOK_BITS 5:5
A2W_PLLC_ANA_SCTL_MASK 0x0000001f
CM_DPIDIV 0x7e10106c:RW
SMI_DSR2_MASK 0xffffffff
USB_DOEPDMA7_WIDTH 32
DMA1_CS_INT_LSB 2
A2W_XOSC_CPR_DIV_CLR 0xfffffffc
HD_MAI_CTL_BUSY_CLR 0xffffbfff
EMMC_INTERRUPT_DMA_CLR 0xfffffff7
GP_SET2_SETn64_LSB 0
GP_FSEL4_FSEL40_CLR 0xfffffff8
DMA15_STRIDE_D_STRIDE_SET 0xffff0000
SD_DQLCRC6_RISE_LSB 16
A2W_PLLC_ANA_SSCS_MODE_CLR 0xfffeffff
SPI_CLK 0x7e204008:RW
GROPCTR10 0x1A005100 + 0x0D0:RW
GROPCTR11 0x1A005100 + 0x0D8:RW
HDMI_FIFO_CTL_MASK 0x0000efff
DMA10_TI_SRC_IGNORE_SET 0x00000800
MPHI_INTCTRL_RX0DISC_BITS 0:0
DSI1_DISP0_CTRL_WIDTH 32
DPHY_CSR_DQ_PVT_COMP_OVERRD_CTRL 0x7ee07058:RW
SD_SECEND1_ADDR_LS_MSB 12
I2C_SPI_SLV_CR_RXE_CLR 0xfffffdff
TS_TSENSCTL_REGULEN_SET 0x04000000
ALIAS_ANY_NONALLOCATING(x) MACRO
SYSAC_TRANS_PRIORITY_WIDTH 8
AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_LSB 0
DMA14_TI_PERMAP_LSB 16
APERF1_BW0_CTRL_LATHALT_CLR 0xefffffff
HDMI_FIFO_CTL_INV_CLK_XFR_BITS 3:3
A2W_PLLB_DIG2R_WIDTH 24
DMA13_DEBUG_RESET 0000000000
USB_DOEPCTL0_ENA_LSB 31
EMMC_INTERRUPT_BOOTACK_MSB 13
JP_QWDATA 0x7e005044:RW
A2W_PLLD_ANA_SSCS_MODE_BITS 16:16
USB_DCTL_GOUT_NAK_STS_CLR 0xfffffff7
HD_MAI_CTL_BUSY_BITS 14:14
DMA14_TI_WAIT_RESP_CLR 0xfffffff7
USB_HCSPLT0_XACT_POS_RESET 0x0
CM_TD0CTL_FLIP_MSB 11
EMMC_IRPT_EN_BLOCK_GAP_SET 0x00000004
TB_JTB_CONFIG_TDI_RISE_CLR 0xfffffdff
AVE_OUT_CTRL_INVERT_EVEN_FIELD_LSB 16
USB_HCDMA1_WIDTH 32
PIXELVALVE0_VERTB_EVEN_WIDTH 32
I2C_SPI_SLV_RSR_RXDMABREQ_MSB 5
CM_PCMCTL_BUSYD_BITS 8:8
TXP_DST_PTR_MASK 0xfffffffe
CCP2TX_TTC_FSP_BITS 12:12
DMA5_STRIDE_D_STRIDE_LSB 16
SD_DQLCRC14_WIDTH 32
HDMI_RAM_PACKET_6_3_WIDTH 32
SD_SD_T_RAS_SET 0x00001f00
APERF1_BW1_AMAX_RESET 0000000000
AVE_OUT_CTRL_ERROR_IRQ_EN_SET 0x00000001
DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
USB_HCFG_WIDTH 3
ASB_H264_M_CTRL_EMPTY_BITS 2:2
DMA_ENABLE_EN0_CLR 0xfffffffe
DMA4_DEBUG_DMA_ID_SET 0x0000ff00
USB_GINTMSK_IEP_INT_CLR 0xfffbffff
SD_SB_REORDER_BITS 7:7
OTP_PRIVATE_PARITY_SIZE_IN_ROWS 1
DMA4_TI_SRC_INC_BITS 8:8
EMMC_INTERRUPT_SDOFF_ERR_LSB 23
HDMI_RAM_PACKET_2_5_WIDTH 32
PM_PXLDO 0x7e100060:RW
AVE_OUT_CTRL_MODE_SET 0x00000030
CCP2TX_TAC_CTATADJ_LSB 28
DMA7_TI_DEST_WIDTH_SET 0x00000020
TXP_CTRL_ALPHA_ENABLE_LSB 20
IC1_MASK1_RESET 0000000000
AVE_OUT_OFFSET_BLUE_OFFSET_MSB 7
SH_CDIV_CLOCKDIV_LSB 0
A2W_PLLB_SP2_DIV_CLR 0xffffff00
EMMC_DMA_STATUS_LEN_NOMATCH_SET 0x00000004
USB_DCTL_GMC_RESET 0x0
SMI_DSR1_RSTROBE_CLR 0xffffff80
DMA4_TXFR_LEN_YLENGTH_LSB 16
CM_EVENT_FLOSSC_SET 0x00010000
VEC_CPS01_CPS23 0x7e806120:RW
SD_DQRCRC8_RISE_LSB 16
HDMI_RAM_PACKET_8_0_RESET 0000000000
SMI_DC_REQW_MSB 5
UART_EN 0x7e201020:RW
CM_DPICTL_KILL_MSB 5
SH_DATA_MASK 0xffffffff
USB_HCINT1_MASK 0xffffffff
TB_BOOT_OPT_NO_PRINT_CLR 0xffffffbf
TIMER_CTRL_DIV1 (0 << 2)
USB_GUSBCFG_MASK 0xe3ffbfff
APERF1_BW2_CTRL_ID_EN_BITS 29:29
A2W_PLLA_DSI0_MASK 0x000003ff
SD_SF_MDLL_CAL_RESET 0x12c
CM_TIMERCTL_ENAB_SET 0x00000010
SYSAC_SRC_ARBITER_CONTROL_LIMIT_LSB 0
DMA15_TI_BURST_LENGTH_SET 0x0000f000
GP_FSEL0_FSEL09_SET 0x38000000
CM_EMMCCTL_WIDTH 10
SMI_CS_ACTIVE_CLR 0xfffffffb
A2W_PLLC_CTRL_PRSTN_SET 0x00020000
A2W_SMPS_B_STAT_POK_LSB 12
FPGA_DCM_CTRL_PERI_RST_BITS 19:16
HDMI_RAM_PACKET_4_2_RESET 0000000000
SD_PHYC_CRC_CLR_MSB 24
USB_DIEPTSIZ13_MASK 0xffffffff
EMMC_HWMAXAMP0_AMP_18V_BITS 23:16
PCM_DREQ_A_RX_PANIC_MSB 22
CM_GP0CTL_BUSY_BITS 7:7
VEC_CGMSAE_BOT_FORMAT 0x7e806050:RW
MPHI_C1INDS_HANDLE_MSB 28
USB_HCTSIZ7_MASK 0xffffffff
CCP2TX_TC_SWR_MSB 31
CAM0_CAMICTL 0x7e800100:RW
DMA3_CS_PAUSED_SET 0x00000010
I2C_SPI_SLV_IFLS_WIDTH 12
DMA9_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
DMA2_CS_DISDEBUG_SET 0x20000000
L1_L1_SANDBOX_END4_WIDTH 30
PIXELVALVE0_INTSTAT_WIDTH 10
UART_LSR_OE_CLR 0xfffffffd
MPHI_HSINDCF_MTERM_RESET 0x0
DMA9_CS_DISDEBUG_CLR 0xdfffffff
SYSAC_USB_PRIORITY_WIDTH 4
SD_DQRCRC8_FALL_BITS 15:0
USB_GHWCFG4_EN_IDDIG_FILTER_MSB 20
SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_MSB 1
DMA8_SOURCE_AD_S_ADDR_BITS 31:0
CAM1_CAMIDPO 0x7e80113c:RW
CAM1_CAMIDC_MASK 0xffffffff
SD_SECSRT1_ADDR_LS_SET 0x00001ffe
SMI_DSW2_WSETUP_CLR 0xc0ffffff
DMA7_CS_PANIC_PRIORITY_SET 0x00f00000
CM_PLLD_LOADDSI0_SET 0x00000001
DMA_ENABLE_EN7_SET 0x00000080
SCALER_DISPBASE2_WIDTH 32
PM_PROC_CFG_LSB 16
USB_GINTMSK_FET_SUSP_RESET 0x0
PM_DUMMY_ONE_LSB 0
ASB_V3D_M_CTRL_FULL_SET 0x00000008
IC 0x7e002000:RW
CCP2TX_TS_IS_MSB 16
DMA10_BASE 0x7e007a00
SD_SECSRT3_ADDR_LS_BITS 12:1
DMA13_DEBUG_READ_ERROR_LSB 2
USB_GINTMSK_INCOMPL_P_BITS 21:21
PWMSTA_WERR1 2
DMA3_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
SCALER_DISPLACT1_MASK 0xffffffff
IS 0x7e002004:RO
APERF0_BW0_CTRL_ID_BITS 12:8
EMMC_CONTROL0_BOOT_EN_MSB 21
CM_PLLC_HOLDCORE2_MSB 5
GR_VCD_ADDR_MASK 0x0000007f
MPHI_C1INDS_HANDLE_LSB 21
USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_SET 0x00c00000
GP_FSEL0_FSEL08_CLR 0xf8ffffff
L1_L1_SANDBOX_START7_CTRL_CLR 0xfffffffe
DMA3_BASE 0x7e007300
A2W_PLLC_CORE1R 0x7e102c20:RW
USB_DOEPINT0_OUT_TKN_EP_DIS_CLR 0xffffffef
DMA13_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
DMA10_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0
DMA8_CS_END_MSB 1
USB_DTHRCTL_RX_THR_EN_MSB 16
SYSAC_SRC_ARBITER_CONTROL_DELAY_SET 0x0000000c
CM_LOCK_FLOCKC_SET 0x00000400
USB_DOEPINT0_TXF_EMPTY_RESET 0x0
PM_PXBG 0x7e100064:RW
AVE_IN_CTRL_FRAME_MODE_MSB 10
SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_SET 0x0000ff00
CM_TD0CTL_ENAB_BITS 4:4
I2C_SPI_SLV_FR_TXBUSY_BITS 0:0
APERF0_GEN_CTRL_ENABLE_CLR 0xfffffffe
CM_INTEN_FLOSSA_CLR 0xffffbfff
CM_ARMCTL_SRC_SET 0x0000000f
CM_PWMDIV_DIV_BITS 23:0
SMI_DMA ( 4*(1<<16))
SLIM_DMA_DC4_MASK 0xffffffff
GRMOCT 0x1A005C00 + 0x18:RW
SD_RWC_MARGIN_BITS 23:22
TB_BOOT_OPT_BOOT_HALT_BITS 7:7
CM_OTPCTL_FRAC_BITS 9:9
DMA2_TXFR_LEN_YLENGTH_LSB 16
CM_TSENSCTL_FRAC_CLR 0xfffffdff
CM_OSCCOUNT_RESET 0000000000
CM_TD1CTL_BUSYD_MSB 8
HD_MAI_CTL_ERRORF_BITS 1:1
ASB_CPR_CTRL_EMPTY_MSB 2
CM_PLLA_HOLDCORE_MSB 5
L1_IC1_CONTROL_ENABLE_STATS_MSB 2
PM_IMAGE_MRDONE_BITS 4:4
GP_FSEL4_FSEL43_CLR 0xfffff1ff
CM_EVENT_GAINA_SET 0x00000001
I2C2_DEL_RESET 0x00300030
DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
CM_VPUDIV 0x7e10100c:RW
PWM_CTL_SBIT2_BITS 11:11
A2W_PLLB_SP2_BYPEN_LSB 9
I2C_SPI_SLV_FR_RXFLEVEL_LSB 11
SD_SD_T_RPab_LSB 28
DMA2_DEST_AD_MASK 0xffffffff
ASB_CPR_CTRL_RCOUNT_SET 0x00003ff0
USB_GRXSTSP_HST_CH_NUM_LSB 0
AVE_IN_OUTSTANDING_BUFF0_WIDTH 8
A2W_PLLC_ANA_SSCS_RESET 0000000000
SMI_DSW2_WSTROBE_BITS 6:0
APERF0_BW0_CTRL_EN_MSB 30
SD_SF_PGEHLD_T_SET 0x1ff80000
HDMI_PCI_MASK_CLEAR (HDMI_BASE_ADDRESS + 0x340) + 0x2c:RW
CAM0_CAMIDI1_WIDTH 32
CM_INTEN_FGAIND_MSB 13
AVE_OUT_CTRL_PRIV_ACCESS_BITS 8:8
DMA9_CS_DREQ_STOPS_DMA_MSB 5
PM_SPARER_SPARE_BITS 23:0
EMMC_FORCE_IRPT_CARD_IN_MSB 6
SCALER_DISPECTRL_Y_BUSY_CLR 0x000001ff
MPHI_C0INDCF_ORUN_MSB 29
USB_DOEPDMAB13_MASK 0xffffffff
PM_SMPS_MASK 0x00000007
APERF1_BW1_CTRL_RESET_BITS 31:31
IC0_FORCE0 0x7e002040:RW
IC0_FORCE1 0x7e002044:RW
GP_AJBTDO_RESET 0000000000
DMA_INT_STATUS_INT9_BITS 9:9
PM_PADS4_MASK 0x0000003f
EMMC_IRPT_EN_DCRC_ERR_MSB 21
EMMC_FORCE_IRPT_DCRC_ERR_LSB 21
USB_GUSBCFG_ULPI_EXT_VBUS_IND_MSB 21
DMA14_DEBUG_DMA_ID_SET 0x0000ff00
MS_SEMA_9 0x7e000024:RW
PCM_CH2WEX (1 << 15)
TB_BOOT_OPT_ELPIDA_CLR 0xffffffef
SYSAC_V3D_PRIORITY_PRIORITY_LSB 0
PM_PADS5_POWOK_MSB 5
EMMC_CONTROL2_RESET 0x00080000
UART_MSR_RI_MSB 6
PWM_STA_STA3_CLR 0xfffff7ff
I2C_SPI_SLV_CR_CPHA_BITS 3:3
MPHI_C0INDDA_WIDTH 32
SYSAC_HVSM_PRIORITY_RESET 0000000000
USB_DOEPTSIZ0_XFERSIZE_BITS 18:0
PCM_RXC_A_CH2EN_CLR 0xffffbfff
EMMC_HWCAP1_SPI_BLOCKMODE_SET 0x02000000
I2C_SPI_SLV_SLV_ADDR_SET 0x0000007f
MPHI_INTCTRL_HSDISC_RESET 0x0
CAM0_CAMISTA 0x7e800104:RW
V3D_INTDIS 0x7ec00000 +0x0038:RW
HDMI_VERTA0_WIDTH 25
PM_RSTS_HADSRH_SET 0x00000400
APERF0_BW2_WTRANS_RESET 0000000000
DMA3_TI_PERMAP_SET 0x001f0000
DMA0_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
AUX_SPI_CNTL0_OUTRISE 0x00000100
EMMC_IRPT_EN_CEND_ERR_SET 0x00040000
HDMI_RAM_PACKET_11_5_WIDTH 32
L1_L1_SANDBOX_START5_CTRL_MSB 0
L1_L1_SANDBOX_START7_START_ADDR_SET 0x3fffffe0
DMA10_CS_DREQ_STOPS_DMA_LSB 5
SD_SECEND0_WIDTH 32
DMA9_TI_BURST_LENGTH_SET 0x0000f000
DMA13_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
DMA11_TI_WAITS_LSB 21
DMA10_DEBUG_DMA_STATE_SET 0x01ff0000
USB_DIEPCTL0_TYPE_LSB 18
USB_PCGCR_RST_PDWN_MODULE_BITS 3:3
USB_DOEPTSIZ2_WIDTH 32
PM_PADS4_POWOK_LSB 5
DMA8_TI_DEST_IGNORE_MSB 7
PIARBCTL_CAM_WIDTH 16
DMA13_CS_PANIC_PRIORITY_CLR 0xff0fffff
DMA2_DEBUG_OUTSTANDING_WRITES_LSB 4
DMA2_CS_ABORT_MSB 30
GP_FEN2_FENn64_BITS 5:0
DMA13_CS_PAUSED_MSB 4
DMA5_TI_MASK 0x07fffffb
SCALER_DISPSTAT_DMA_ERR_BIT0_CLR 0x00003fff
EMMC_CONTROL0_GAP_IEN_SET 0x00080000
A2W_PLLH_AUX 0x7e102360:RW
GP_CLR0 0x7e200028:RW
GP_CLR1 0x7e20002c:RW
GP_CLR2 0x7e200030:RW
SMI_DSR2_RPACEALL_BITS 15:15
A2W_PLLB_SP1_DIV_SET 0x000000ff
USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_RESET 0x0
HD_CSC_34_33_RESET 0000000000
PWM_CTL_MSEN3_SET 0x00800000
CCP2TX_TS_IEB_SET 0x00000002
DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
USB_GPVNDCTL_CTRL_UTMI_BITS 11:8
A2W_PLLB_SP0_BYPEN_BITS 9:9
USB_DIEPINT0_EP_DISBLD_LSB 1
SMI_DSW1_WHOLD_BITS 21:16
HDMI_INTR2_BASE (HDMI_BASE_ADDRESS + 0x340)
EMMC_INTERRUPT_OEM_ERR_BITS 31:30
CM_ISPCTL_FRAC_BITS 9:9
AUX_MU_STAT_TX_SPACE 0x00000002
INTERRUPT_ARM ((64) + 30 )
CM_OTPCTL 0x7e101090:RW
DMA6_NEXTCONBK_ADDR_MSB 31
CMI_CAM0_RX0SRC_BITS 3:2
VEC_DAC_CONFIG_MASK 0xffffffff
PIXELVALVE1_VSYNCD_EVEN_MASK 0x0001ffff
SD_TMC_TSTPAT_BITS 31:16
DMA_ENABLE_EN13_MSB 13
USB_DOEPINT0_BNA_LSB 9
USB_DCTL_SGOUT_NAK_LSB 9
SH_VDD_POWER_ON_SET 0x00000001
SD_SD_T_RAS_CLR 0xffffe0ff
EMMC_FORCE_IRPT_CEND_ERR_CLR 0xfffbffff
CAM0_CAMIVWIN_RESET 0000000000
DMA4_DEST_AD_D_ADDR_MSB 31
DMA0_DEBUG_DMA_STATE_LSB 16
CM_TECDIV_WIDTH 18
HDMI_CEC_CNTRL_2_MASK 0x7fffffff
DMA7_TI_WAITS_SET 0x03e00000
CCP2RDEA0 CCP2_BASE_ADDRESS + 0x124:RW
CCP2RDEA1 CCP2_BASE_ADDRESS + 0x224:RW
A2W_HDMI_CTL_RCAL_SELDIV_MSB 5
DMA10_TI_DEST_DREQ_CLR 0xffffffbf
ASB_H264_S_CTRL_FULL_SET 0x00000008
DMA6_DEST_AD_D_ADDR_BITS 31:0
MPHI_C0INDFS_DFIFOLVL_BITS 15:0
A2W_PLLH_ANA_MULTI_RESET 0000000000
TB_BOOT_OPT_TCL_SIM_LSB 3
USB_DTHRCTL_NON_ISO_THR_EN_MSB 0
USB_DIEPDMA5_MASK 0xffffffff
SMI_FD_FCNT_RESET 0x0
MPHI_C1INDS_VALID_BITS 30:30
USB_GRXSTSP_DEV_PKT_STS_BITS 20:17
GP_FSEL6_MASK 0x3fffffff
AVE_IN_CURRENT_LINE_BUF0_WIDTH 32
CM_GP0CTL_BUSYD_MSB 8
USB_HCSPLT3_MASK 0xffffffff
SD_SECSRT3_EN_BITS 0:0
MPHI_HSINDS_VALID_MSB 30
GP_PUDCLK1_MASK 0xffffffff
MPHI_INTCTRL_RX1DISC_SET 0x00000010
ARM_C0_SIZ1G 0x00000003
HDMI_DETECTED_VERTA1_WIDTH 25
A2W_PLLB_ANA_SCTL_UPDATE_MSB 3
USB_GPVNDCTL_DIS_ULPI_DRVR_BITS 31:31
EMMC_CONTROL0_RESET 0000000000
USB_HCCHAR0_ODD_FRM_CLR 0xdfffffff
CM_SLIMCTL_WIDTH 11
HDMI_RAM_PACKET_4_0_WIDTH 32
DMA2_TI_DEST_INC_LSB 4
L1_L1_SANDBOX_PERI_BR_RESET 0x00000707
APHY_CSR_DDR_PLL_CONFIG_CNTRL 0x7ee06038:RW
IS_ALIAS_STREAMING(x) MACRO
V3D_PCTRS10 0x7ec006d4:RW
V3D_PCTRS11 0x7ec006dc:RW
L1_IC0_RD_HITS_WIDTH 0
V3D_PCTRS13 0x7ec006ec:RW
V3D_PCTRS14 0x7ec006f4:RW
V3D_PCTRS15 0x7ec006fc:RW
HD_VID_CTL_ERROR_LSB 25
CM_PLLTCNT2_WIDTH 24
HDMI_READ_POINTERS_DRFT_UNDERFLOW_BITS 16:16
DMA9_CS 0x7e007900:RW
AVE_OUT_CTRL_PRIV_ACCESS_SET 0x00000100
DMA13_CS_ACTIVE_SET 0x00000001
IC0_MASK1_MASK 0x77777777
SMI_SCALER_1_DMA (25*(1<<16))
A2W_PLLB_ANA2R_RESET 0000000000
USB_DOEPTSIZ13_WIDTH 32
EMMC_IRPT_EN_ENDBOOT_MSB 14
EMMC_IRPT_MASK_ATA_ERR_MSB 29
OTP_ARM_DISABLE_REDUNDANT_BIT 25
DMA5_CS_DISDEBUG_MSB 29
JICST_INTE (1 << 3)
SYSAC_DBG_PRIORITY_MASK 0x0000000f
USB_GHWCFG4_EN_A_VALID_FILTER_SET 0x00400000
USB_HPTXSTS_HPTXQSPCAVAIL_MSB 23
USB_DPTXFSIZ15_WIDTH 32
DMA_ENABLE_EN7_BITS 7:7
JICST_INTM (1 << 2)
DMA5_CS_DISDEBUG_BITS 29:29
CM_CAM1CTL_KILL_BITS 5:5
DMA4_DEST_AD_WIDTH 32
MPHI_C1INDS_VALID_CLR 0xbfffffff
DMA14_CS_PRIORITY_LSB 16
DMA2_CS_END_BITS 1:1
TB_TASK_STATUS 0x7e20b080:RW
CM_SDCDIV_DIV_SET 0x0003f000
TS_TSENSCTL_PRWDW_MSB 0
USB_GHWCFG4_NUM_CRL_EPS_RESET 0x0
HDMI_TX_PHY_TX_PHY_SPARE_MASK 0xffffffff
CM_GP1DIV_DIV_LSB 0
I2C_SPI_SLV_RIS_BERIS_MSB 2
USB_HPTXSTS_HPTXFSPCAVAIL_LSB 0
CCP2TX_TS_TEI_LSB 18
CM_DSI0EDIV_DIV_LSB 4
L1_D0_WR_MISSES 0x7ee02158:RO
GP_FSEL3_FSEL34_MSB 14
SD_DQRCRC9_WIDTH 32
SH_HBCT_RESET 0x00000400
CSI2_RDSA1 CSI2_BASE_ADDRESS + 0x220:RW
APERF1_BW2_CTRL_ID_SET 0x00001f00
APERF0_BW0_AMAX_RESET 0000000000
USB_GHWCFG4_NUM_CRL_EPS_MSB 19
USB_GINTMSK_EP_MIS_BITS 17:17
GP_FSEL5_FSEL55_CLR 0xfffc7fff
SMI_DSW1_WSWAP_LSB 22
FPGA_CTRL0_CAM_CTL1_CLR 0xfffffffd
L1_L1_SANDBOX_START0_START_ADDR_MSB 29
CMI_USBCTL_RESET 0x00000040
DMA9_TI_INTEN_MSB 0
DMA0_CS_WIDTH 32
DSI1_LP_DLT6_RESET 0000000000
CM_LOCK_FLOCKA_BITS 8:8
V3D_PCTRS0_WIDTH 5
CM_PLLTCNT2_CNT_SET 0x00ffffff
USB_GHWCFG4_EN_DED_TX_FIFO_CLR 0xfdffffff
CM_GP1CTL_MASH_LSB 9
PCM_RXC_A_CH1POS_CLR 0xc00fffff
INTERRUPT_AVE ((64) + 37 )
DMA7_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
USB_DOEPINT0_IN_EP_NAK_EFF_MSB 6
HD_MAI_CTL_ERRORE_MSB 2
PWM_CTL_PWEN4_BITS 24:24
TB_PRINTER_CTRL_MASK 0x0000fff3
SD_SECSRT0_ADDR_MS_CLR 0x00001fff
TS_TSENSCTL_CTRL_CLR 0xffffffe3
DMA6_NEXTCONBK_WIDTH 32
A2W_PLLC_CORE1R_WIDTH 10
AVE_OUT_CTRL_INVERT_DSYNC_BITS 18:18
DMA13_TI_PERMAP_MSB 20
SLIM_DMA_MC_STAT_MASK 0x0000000f
SD_DQRCRC1_FALL_LSB 0
CM_TECDIV_DIV_MSB 17
OTP_BOOT_ROM_ROW (((8 +4)+4)+1)
DMA4_TI_DEST_WIDTH_SET 0x00000020
EMMC_CMDTM_CMD_IXCHK_EN_LSB 20
CM_PLLTCTL_BUSY_BITS 7:7
APERF0_BW1_CTRL_ID_MSB 12
USB_GUSBCFG_ULPI_CLK_SUS_M_MSB 19
USB_GOTGCTL_HST_SET_HNP_EN_MSB 10
PM_PASSWORD 0x5a000000
A2W_PLLC_CTRL_PWRDN_SET 0x00010000
USB_GHWCFG4_NUM_IN_EPS_RESET 0x0
DMA8_CS_ERROR_SET 0x00000100
DMA_ENABLE_EN9_LSB 9
GRTCDIM0 0x1A005300 + 0x08:RW
GRTCDIM1 0x1A005300 + 0x88:RW
PM_PADS3_POWOK_SET 0x00000020
HDMI_SCHEDULER_CONTROL_USE_PREDICTS_MSB 2
PM_RSTS_HADSRF_SET 0x00000200
DMA4_TI_SRC_WIDTH_SET 0x00000200
USB_DOEPCTL2_MASK 0xffffffff
V3D_INTENA_WIDTH 32
HDMI_CPU_MASK_CLEAR_WIDTH 32
PM_DSI0_CTRLEN_SET 0x00000001
SMI_DC_REQR_CLR 0xfffff03f
CM_TIMERDIV_DIV_LSB 0
NU_HOSTIO_OF 0x7e008000:RW
EMMC_BOOT_TIMEOUT_MASK 0xffffffff
GP_FSEL4_FSEL44_SET 0x00007000
TB_BOOT_OPT_BANK_MODE_CLR 0xfffffcff
A2W_PLLD_ANA_SCTL_RESET 0000000000
HDMI_TEST 0x7e9020dc:RW
DMA13_CS_INT_CLR 0xfffffffb
A2W_PLLA_ANA_SSCS_STEP_CLR 0xffff0000
DMA9_NEXTCONBK_ADDR_SET 0xffffffe0
TE1_VSWIDTH TECTL_BASE_ADDRESS + 0x0C:RW
CM_VECCTL_MASK 0x000003bf
HD_CSC_CTL_PADMSB_BITS 4:4
A2W_PLLB_SP0_DIV_MSB 7
GR_VCM_ADDR_MASK 0x0000003f
SD_DQRCRC14_FALL_MSB 15
USB_DIEPINT0_IN_TKN_TXFEMP_MSB 4
DMA8_TXFR_LEN_MASK 0x0000ffff
SD_RWC_MAXCNT_SET 0x1f000000
DMA12_TXFR_LEN_XLENGTH_MSB 15
EMMC_CONTROL1_CLK_EN_SET 0x00000004
CM_GNRICCTL_BUSYD_CLR 0xfffffeff
USB_DOEPINT8_WIDTH 32
USB_GHWCFG3_PACKET_COUNT_WIDTH_SET 0x00000070
PM_AVS_INTEN_ALERT_PERI_A_SET 0x00000001
MPHI_INTCTRL_HSDCOFLW_RESET 0x0
DMA7_DEST_AD_D_ADDR_SET 0xffffffff
USB_HCINT0_XACT_ERR_LSB 7
USB_HPRT_RST_BITS 8:8
I2C_SPI_SLV_DR_TXFLEVEL_BITS 26:22
VPU_ARB_CTRL_L2_LIMIT_SET 0x00000003
MPHI_TXAXICFG_TXNPRIO_CLR 0xfffffff0
APERF1_BW2_CTRL_BUS_MSB 4
HD_MAI_CTL_ERRORE_CLR 0xfffffffb
V3D_PCTR6_WIDTH 32
CM_H264CTL_KILL_CLR 0xffffffdf
A2W_SMPS_CTLC2R_MASK 0x00ffffff
DMA6_DEBUG_READ_ERROR_SET 0x00000004
USB_GRSTCTL_DMA_REQ_SET 0x40000000
CM_EVENT_LOSSC_CLR 0xffffff7f
DMA3_CS_DISDEBUG_SET 0x20000000
MPHI_MOUTFS_LEVEL_CLR 0xfffffc00
USB_GNPTXFSIZ_NP_TXF_DEP_SET 0xffff0000
DSI0_DISP0_CTR_MASK 0xffffffff
MS_SEMA_25_MASK_MSB 0
PCM_RXC_A_CH2POS_BITS 13:4
USB_GINTMSK_OTG_INT_RESET 0x0
CM_PLLD_HOLDDSI0_BITS 1:1
DMA13_CS_MASK 0xf0ff017f
I2C_SPI_SLV_RIS_OERIS_BITS 3:3
CM_PLLD_ANARST_CLR 0xfffffeff
HD_MAI_THR_DREQLOW_CLR 0xffffffc0
SDEDM SDCARD_BASE + 0x34:RW
MS_SEMA_31_MASK_LSB 0
DMA13_CS_PRIORITY_MSB 19
SD_CS_DEL_KEEP_CLR 0xfffbffff
SLIM_DCC6_PROT_MASK 0xc001ffff
DMA7_TI_BURST_LENGTH_SET 0x0000f000
CM_H264CTL_SRC_BITS 3:0
HDMI_PERT_DATA 0x7e90208c:RW
CM_GP2CTL_MASK 0x000003bf
USB_GHWCFG3_VENDOR_CTL_INTERFACE_SET 0x00000200
CM_TSENSCTL 0x7e1010e0:RW
A2W_XOSC_BIAS_RESET 0x00000018
DMA5_TI_INTEN_CLR 0xfffffffe
USB_HCDMA0_MASK 0xffffffff
USB_HCINT2_WIDTH 32
PWM_DMAC_ENAB_CLR 0x7fffffff
PCMMODE_FLEN 10
PCM_CS_A_TXD_CLR 0xfff7ffff
SDRAM_SIZE (1024 * 1024 * 128)
A2W_PLLA_ANA3R_WIDTH 24
GP_HEN1_HENn32_CLR 0x00000000
CM_OTPCTL_SRC_SET 0x00000003
MS_SEMA_15_MASK_LSB 0
USB_HCSPLT0_HUB_ADDR_CLR 0xffffc07f
GP_FSEL3_FSEL30_LSB 0
DMA3_TI_SRC_WIDTH_MSB 9
DMA4_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
DMA2_CS_RESET_CLR 0x7fffffff
MS_SEMA_30_WIDTH 1
USB_HCSPLT2 0x7e980544:RW
USB_HCSPLT3 0x7e980564:RW
USB_HCSPLT4 0x7e980584:RW
UART_LSR_THRE_SET 0x00000020
USB_HCSPLT6 0x7e9805c4:RW
USB_HCSPLT7 0x7e9805e4:RW
DMA14_CS_DREQ_STOPS_DMA_LSB 5
DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
PCM_TXC_A_CH2WID_CLR 0xfffffff0
A2W_PLLC_DIG2R_RESET 0x00100401
SMI_DC_PANICW_LSB 12
I2C_SPI_SLV_CR_ENCTRL_BITS 6:6
DSI_LPRX_TO_CNT 0x7e209000 + 0x34:RW
DMA_INT_STATUS_INT9_CLR 0xfffffdff
DMA12_TI_SRC_INC_SET 0x00000100
A2W_HDMI_CTL_RCALR_WIDTH 17
CM_CAM0DIV_MASK 0x0000fff0
USB_DCTL_GMC_MSB 14
APHY_CSR_ADDR_MASTER_DLL_OUTPUT 0x7ee06014:RW
DMA15_CS_ERROR_BITS 8:8
USB_GINTMSK_USB_SUSP_LSB 11
USB_DIEPDMA7_MASK 0xffffffff
MS_SEMA_4_MASK_CLR 0xfffffffe
A2W_PLLD_DSI1R_WIDTH 10
PWM_STA_BERR_LSB 8
USB_PCGCR_STOP_PCLK_LSB 0
CM_EVENT_FLOSSD_LSB 17
CM_PWMDIV 0x7e1010a4:RW
DMA15_CS_DISDEBUG_BITS 29:29
A2W_PLLB_ANA_VCO 0x7e1026f0:RW
CM_TECCTL_BUSY_CLR 0xffffff7f
USB_GHWCFG4_NUM_CRL_EPS_CLR 0xfff0ffff
HD_MAI_DAT_RESET 0000000000
CM_OTPCTL_KILL_LSB 5
L1_IC1_CONTROL_BP_DISABLE_BITS 3:3
SLIM_DCC4_PA1_RESET 0000000000
HDMI_FIFO_CTL_MASTER_SLAVE_N_BITS 0:0
CAM1_CAMICS_MASK 0xffffffff
CM_V3DDIV 0x7e10103c:RW
USB_DIEPDMAB1_MASK 0xffffffff
EMMC_INTERRUPT_CMD_DONE_CLR 0xfffffffe
H264_RC_MASK 0xffffffff
HDMI_V_MASK 0xffffffff
CM_DSI1PCTL_FRAC_LSB 9
USB_DOEPINT0_AHB_ERR_MSB 2
DMA12_CS_INT_BITS 2:2
PCM_TXC_A_CH1POS_MSB 29
USB_HCSPLT0_COMP_SPLT_RESET 0x0
A2W_HDMI_CTL_HFEN_HFEN_LSB 0
HDMI_HORZB_MANUAL_HBP_BITS 29:20
MPHI_C0INDDB_HANDLE_MSB 27
CM_PLLTCTL_KILL_BITS 5:5
L1_D_PRIORITY_c0_l2_priority_CLR 0xfffffff0
I2C0_CLKT_RESET 0x00000040
TB_JTB_CONFIG_TRSTN_LSB 14
A2W_PLLH_ANA3R_RESET 0000000000
USB_DIEPINT12_MASK 0xffffffff
SDRAM_CTRL_DMA (0*(1<<16))
SD_CS_SDTST_MSB 5
HD_VID_CTL_RST_FRAMEC_LSB 29
SD_SB_MASK 0xfff001ff
PCM_DREQ_A_RX_CLR 0xffffff80
USB_DIEPCTL12_WIDTH 32
EMMC_TUNE_STEPS_DDR_STEPS_SET 0x0000003f
UART_LSR_TEMT_MSB 6
DMA10_CONBLK_AD_SCB_ADDR_LSB 5
L1_D_CONTROL_DC1_FLUSH_LSB 2
DMA7_TI_SRC_IGNORE_BITS 11:11
TH1STPC 0x1A008000 + 0x08:RW
UART_LCR_DTR_LSB 0
CM_PLLD_LOADDSI1_LSB 2
USB_GRSTCTL_RXF_FLSH_RESET 0x0
EMMC_IRPT_MASK_CMD_DONE_SET 0x00000001
DMA1_TI_TDMODE_SET 0x00000002
SD_DQLCRC9_RISE_RESET 0x0
APERF1_BW1_RTWAIT_RESET 0000000000
DMA4_TI_TDMODE_LSB 1
MS_MBOX_7_RESET 0000000000
CM_UARTCTL_KILL_MSB 5
DSI0_LP_DLT6_WIDTH 10
PWM_CTL_CLRF1_BITS 6:6
L1_IC1_PRIORITY_IC1_APRIORITY1_SET 0x000000f0
CM_CAM1CTL_SRC_CLR 0xfffffff0
USB_DIEPCTL0_NEXT_EP_MSB 14
USB_DIEPEMPMSK_EP_TXF_EMP_MSK_SET 0x0000ffff
DMA9_TI_WAITS_BITS 25:21
DMA0_DEBUG_READ_ERROR_LSB 2
PM_GNRIC_ISPOW_BITS 2:2
A2W_PLLC_ANA_SCTLR 0x7e102d30:RW
USB_DOEPTSIZ0_SUP_CNT_LSB 29
JMCTRL_UNUSED_BITS ((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12) | (1 << 11))
DMA5_TI_WAITS_LSB 21
DPHY_CSR_CRC_DATA_WIDTH 28
SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_SET 0x000000c0
INTERRUPT_AVSPMON ((64) + 63 )
PWM_CTL_MSEN2_MSB 15
MPHI_C1INDS_WORDS_LSB 0
PCM_TXC_A_CH2EN_BITS 14:14
DMA7_CS_WIDTH 32
SD_SE_T_FAW_LSB 12
SD_DQLCRC6_FALL_LSB 0
SD_PHYC_CRC_CLR_BITS 24:24
SMI_DSR2_RSTROBE_SET 0x0000007f
PM_PXLDO_RSTPLLDR_BITS 17:17
DSI0_PHY_AFEC1_RESET 0000000000
MS_IREQ_0_IREQ_0_CLR 0x00000000
USB_DIEPCTL10 0x7e980a40:RW
USB_DIEPCTL11 0x7e980a60:RW
USB_DIEPCTL12 0x7e980a80:RW
USB_DIEPCTL13 0x7e980aa0:RW
USB_DIEPCTL14 0x7e980ac0:RW
USB_DIEPCTL15 0x7e980ae0:RW
AVE_OUT_STATUS_COEFF_ERROR_SET 0x00000004
CM_LOCK_FLOCKD_LSB 11
CSI2LPRX2 CSI2_BASE_ADDRESS + 0x28:RW
CDPC 0x1C00E000 + 0x00:RW
MS_IREQ_0_WIDTH 32
HDMI_RAM_PACKET_13_6_RESET 0000000000
CAM0_CAMDBG2_WIDTH 32
DMA5_TI_SRC_INC_SET 0x00000100
SMI_DSR0_MODE68_MSB 23
A2W_PLLH_ANA_SCTL_SEL_LSB 0
OTP_VPU_CACHE_KEY_ROW_REDUNDANT 72
PCM_MODE_A_FTXP_BITS 24:24
PCM_RXC_A_CH2WEX_MSB 15
DMA6_DEBUG_OUTSTANDING_WRITES_LSB 4
SMIDCS_START 1
USB_DIEPCTL0_CNAK_CLR 0xfbffffff
CM_VECCTL_BUSYD_LSB 8
CM_ARMCTL_BUSYD_SET 0x00000100
USB_GGPIO_GPI_RESET 0x0
AVE_IN_STATUS_CAPTURING_LSB 31
TE_2TIMER_MASK 0xffffffff
DMA13_CS_ACTIVE_BITS 0:0
TXP_CTRL_FIELD_MSB 3
SD_CS_RESTRT_RESET 0x0
SD_SECEND3_ADDR_MS_SET 0xffffe000
APERF1_BW1_WTRANS_RESET 0000000000
USB_GOTGINT_HST_NEG_DET_SET 0x00020000
USB_DCTL_GOUT_NAK_STS_RESET 0x0
USB_GI2CCTL_RW_DATA_BITS 7:0
TB_BOOT_OPT_SDC_BEHAV_PHY_MSB 5
USB_HPRT_OVR_CURR_ACT_LSB 4
EMMC_CONTROL1_CLK_GENSEL_SET 0x00000020
DMA10_CS_INT_CLR 0xfffffffb
CM_EVENT_GAINB_LSB 1
SCALER_DISPLIST1_MASK 0xffffffff
A2W_PLLA_DIG2_WIDTH 24
USB_GHWCFG4_EN_B_VALID_FILTER_RESET 0x0
PM_PADS5_DRIVE_BITS 2:0
L1_D_CONTROL_DC_EN_STATS_LSB 3
A2W_PLLH_PIXR_MASK 0x000003ff
EMMC_CONTROL2_SIGTYPE_BITS 19:19
USB_DCFG_DEV_ADDR_RESET 0x0
AVE_IN_STATUS_BUF0_COMPL_BITS 1:1
USB_DCFG_PER_SCH_INTV_BITS 25:24
L1_IC1_CONTROL_DISABLE_LSB 0
CM_ISPCTL_GATE_MSB 6
TB_JTB_BITCNT_WIDTH 6
EMMC_HWMAXAMP0 0x7e300048:RW
L2_FLUSH_END_MASK 0x0fffffe0
CM_PULSECTL 0x7e101190:RW
PM_GNRIC_CFG_LSB 16
DMA7_TI_BURST_LENGTH_LSB 12
DMA15_CS_WIDTH 32
DMA14_DEBUG_READ_ERROR_BITS 2:2
HD_VID_CTL_FULRGB_MSB 21
JHADDR_TABLEF (1 << 31)
USB_GPVNDCTL_REG_ADDR_LSB 16
DMA12_TI_INTEN_CLR 0xfffffffe
GR_VCD_BASE 0x1A005A00
MS_SEMA_7_MASK_LSB 0
EMMC_IRPT_EN_CARD_BITS 8:8
USB_GHWCFG2_TOKEN_QUEUE_DEPTH_SET 0x7c000000
TB_TASK_TEXT_FLAG_BITS 16:16
SMI_DSR2_RWIDTH_CLR 0x3fffffff
DMA14_DEST_AD_D_ADDR_BITS 31:0
DMA11_CS_ERROR_SET 0x00000100
DMA9_CS_INT_CLR 0xfffffffb
DMA2_CS_DREQ_BITS 3:3
EMMC_HWCAP0_SDMA_LSB 22
PCMCS_RXERR (1 << 16)
AUX_MU_STAT_CTS 0x00000080
DMA9_TI_SRC_IGNORE_CLR 0xfffff7ff
DMA5_CS_PAUSED_CLR 0xffffffef
GP_FSEL0_FSEL03_CLR 0xfffff1ff
SD_DQLCRC12_FALL_BITS 15:0
A2W_PLLD_CTRL_RESET 0x00010000
DMA6_CS_END_BITS 1:1
SD_DQRCRC8_FALL_LSB 0
SYSAC_V3D_LIMITER_MASK 0x00000fff
APERF0_GEN_CTRL_MASK 0x00000003
MPHI_HSINDS_WORDS_RESET 0x0
DMA7_CS_DREQ_SET 0x00000008
USB_HCINT0_BBL_ERR_CLR 0xfffffeff
AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_MSB 31
SMI_DSW2_WHOLD_CLR 0xffc0ffff
MPHI_MOUTFS_RPTR_MSB 29
IC0_MASK5_RESET 0000000000
TXP_CTRL_GO_LSB 0
DSI0_LP_DLT6 0x7e20905c:RW
DSI0_LP_DLT7 0x7e209060:RW
DMA8_TI_WAIT_RESP_BITS 3:3
A2W_PLLH_PIX 0x7e102560:RW
PM_HDMI_LDOPD_BITS 1:1
PCM_CS_A_EN_BITS 0:0
DMA0_TI_DEST_INC_CLR 0xffffffef
DMA1_CS_PANIC_PRIORITY_LSB 20
VEC_CPS89_CPS1011_MASK 0xffffffff
USB_DIEPCTL9_WIDTH 32
EMMC_RESP3_RESET 0000000000
PM_PROC_MRDONE_MSB 4
SD_SD_T_RCD_MSB 3
GP_AREN2_ARENn64_MSB 5
SD_DQLCRC3_FALL_BITS 15:0
EMMC_STATUS_RETUNING_REQ_MSB 3
MPHI_RXAXICFG_INTHRESH_BITS 16:8
SMI_A_RESET 0000000000
I2C_SPI_SLV_DR_UE_MSB 9
SD_SECEND3_ADDR_LS_RESET 0xfff
PCMDREQ_TXDREQTHR_LSB 8
DMA_ENABLE_EN1_CLR 0xfffffffd
EMMC_IRPT_EN_CTO_ERR_MSB 16
IMASK0_0 0x7e002010:RW
USB_GGPIO_GPI_MSB 15
DMA7_TI_SRC_IGNORE_MSB 11
SMI_DSW1_WSTROBE_MSB 6
HDMI_RAM_PACKET_11_4_MASK 0xffffffff
USB_GUSBCFG_TOUT_CAL_LSB 0
A2W_PLLC_CTRL_NDIV_BITS 9:0
GP_AFEN0_AFENn0_SET 0xffffffff
DMA13_CS_DISDEBUG_SET 0x20000000
FPGA_CTRL0_SW_SPI_CS_CLR 0xfffffeff
USB_HFIR_IN_BITS 15:0
HDMI_SCHEDULER_CONTROL_POSTLN_AVOID_SET 0x00003f00
DMA6_CS_ACTIVE_BITS 0:0
DMA3_TI_SRC_WIDTH_LSB 9
PM_AVS_INTEN 0x7e100088:RW
SD_VIN_SPLIT_RESET 0x0
CAM0_CAMICC_WIDTH 32
APERF0_BW2_CTRL_LATHALT_BITS 28:28
CM_CCP2CTL_SRC_LSB 0
PWM_CTL_MSEN4_LSB 31
GP_LEV0_LEVn0_BITS 31:0
SLIM_DCC8_PROT 0x7e210310:RW
SMI_CS_PAD_SET 0x000000c0
DMA0_CONBLK_AD_WIDTH 32
EMMC_DMA_STATUS 0x7e300054:RW
A2W_SMPS_L_SCV_RESET 0000000000
AJB_D0_RISE 0x000100
PWM_CTL_RPTL1_CLR 0xfffffffb
CM_TSENSCTL_MASK 0x000003b3
CM_DSI0ECTL_KILL_CLR 0xffffffdf
EMMC_FORCE_IRPT_CTO_ERR_MSB 16
CM_GP2DIV_RESET 0000000000
HDMI_FIFO_CTL_RECENTER_DONE_SET 0x00004000
EMMC_CMDTM_CMD_ISDATA_MSB 21
A2W_PLLH_FRAC_FRAC_CLR 0xfff00000
USB_DTXFSTS13_MASK 0xffffffff
DMA12_TI_SRC_IGNORE_CLR 0xfffff7ff
USB_DIEPTXF1_FIFO_STADDR_MSB 15
AUX_MU_STAT_TXFILL 0xFF000000
SMI_DSR1_RHOLD_SET 0x003f0000
MPHI_INTSTAT_HSDCFOFLW_CLR 0xf7ffffff
USB_DPTXFSIZ3_MASK 0xffffffff
V3D_SRQCS_WIDTH 24
HDMI_RAM_PACKET_6_1_MASK 0xffffffff
GP_FSEL4_FSEL49_MSB 29
USB_GINTMSK_ENUM_DONE_CLR 0xffffdfff
USB_DOEPTSIZ11_MASK 0xffffffff
V3D_INTCTL_MASK 0xffffffff
A2W_SMPS_CTLA0R_RESET 0000000000
DMA3_TXFR_LEN_XLENGTH_CLR 0xffff0000
CAM0_CAMIBSA1_MASK 0xffffffff
SMI_DSW2_WIDTH 32
USB_HCSPLT5_MASK 0xffffffff
DMA11_TI_WAIT_RESP_BITS 3:3
USB_GRXSTSP_HST_BCNT_LSB 4
APERF1_BW1_CTRL_ID_MSB 12
V3D_DBSSR_WIDTH 32
CM_PLLB_HOLDARM_SET 0x00000002
DSI0_HS_DLT3_MASK 0x000003fc
A2W_PLLB_SP2_CHENB_MSB 8
EMMC_INTERRUPT_CARD_IN_CLR 0xffffffbf
MPHI_HSINDS_DISCARD_RESET 0x0
SH_CMD_RESET 0000000000
USB_HCINT0_STALL_SET 0x00000008
CM_TIMERCTL_WIDTH 10
SD_PT2_T_INIT5_SET 0x0000ffff
USB_GI2CCTL_RW_LSB 30
DMA15_SOURCE_AD 0x7ee0500c:RO
USB_GHWCFG2_ARCHITECTURE_CLR 0xffffffe7
CAM1_CAMDLT_WIDTH 32
PWM_CTL_PWEN4_CLR 0xfeffffff
HD_VID_CTL_ERROR_MSB 26
DMA5_TI_DEST_WIDTH_BITS 5:5
USB_GRXSTSP_DEV_BCNT_BITS 14:4
USB_HCCHAR0_ODD_FRM_SET 0x20000000
DMA12_TI_DEST_WIDTH_CLR 0xffffffdf
EMMC_FORCE_IRPT_READ_RDY_CLR 0xffffffdf
L1_IC0_CONTROL_ENABLE_STATS_LSB 2
USB_DFIFO5_MASK 0xffffffff
CM_PLLH_MASK 0x00000307
SMICS_TXD 28
SMICS_TXE 30
APERF0_BW0_WTWAIT_MASK 0xffffffff
CM_HSMCTL_ENAB_CLR 0xffffffef
INTERRUPT_DMA0 ((64) + 16 )
INTERRUPT_DMA1 ((64) + 17 )
INTERRUPT_DMA2 ((64) + 18 )
INTERRUPT_DMA3 ((64) + 19 )
INTERRUPT_DMA4 ((64) + 20 )
INTERRUPT_DMA5 ((64) + 21 )
INTERRUPT_DMA6 ((64) + 22 )
INTERRUPT_DMA7 ((64) + 23 )
INTERRUPT_DMA8 ((64) + 24 )
INTERRUPT_DMA9 ((64) + 25 )
SMICS_TXW 26
A2W_PLLD_DSI1_BYPEN_LSB 9
ARM_BD_BELL0 0x00000100
ARM_BD_BELL1 0x00000200
ARM_BD_BELL2 0x00000400
ARM_BD_BELL3 0x00000800
A2W_PLLB_SP1_CHENB_LSB 8
USB_DSTS_ENUM_SPD_CLR 0xfffffff9
PM_DESCRIPTION "Power manager"
TXP_CTRL_DITHER_LSB 13
CSI2_RC CSI2_BASE_ADDRESS + 0x00:RW
CM_BURSTCNT_RESET 0000000000
USB_HPRT_MASK 0x0007fdff
EMMC_INTERRUPT_RETUNE_BITS 12:12
CMI_USBCTL_GATE_MSB 6
DMA5_TI_PERMAP_CLR 0xffe0ffff
CSI2_RS CSI2_BASE_ADDRESS + 0x04:RW
HDMI_HOTPLUG_INT_WIDTH 3
DMA5_TI_DEST_INC_LSB 4
GP_FSEL5_FSEL59_SET 0x38000000
MS_MBOX_5_WIDTH 32
MS_MBOX_6_MBOX_MSB 31
HDMI_TX_PHY_HDMI_TX_PHY_CTL_1 (HDMI_BASE_ADDRESS + 0x2c0) + 8:RW
USB_DIEPCTL2_MASK 0xffffffff
DMA0_CS_INT_CLR 0xfffffffb
DMA4_CS_DISDEBUG_SET 0x20000000
DMA12_DEBUG_FIFO_ERROR_LSB 1
USB_DAINT 0x7e980818:RW
DMA9_TI 0x7e007908:RO
CCP2TX_TIC_TEIE_CLR 0xfffffffd
I2C_SPI_SLV_DR_TXBUSY_CLR 0xfffeffff
CM_TD1CTL_ENAB_MSB 4
EMMC_FORCE_IRPT_BLOCK_GAP_BITS 2:2
DMA3_CS_WIDTH 32
DMA1_STRIDE_D_STRIDE_MSB 31
SCALER_DISPCTRL_DSP1_PANIC_MSB 27
CM_LOCK_FLOCKH_MSB 12
CM_EMMCCTL_MASK 0x000003bf
MPHI_C1INDCF_WIDTH 32
A2W_SMPS_C_CLK_TDEN_MSB 3
IC0_WAKEUP_RESET 0x10000000
PCMCS_RXD (1 << 20)
PCMCS_RXF (1 << 22)
PCM_INTEN_A_TXW_BITS 0:0
ARM_AIS0_HAVEDATA 0x00000010
PIXELVALVE0_STAT 0x7e20602c:RW
DMA1_TI_PERMAP_LSB 16
SD_SECEND0_ADDR_MS_LSB 13
IMASK7_0 0x7e00202c:RW
PCM_GRAY_EN_LSB 0
HD_VID_CTL_FULSYNC_BITS 22:22
V3D_PCTRS4_MASK 0x0000001f
DMA2_CS_ABORT_BITS 30:30
CM_DSI0PDIV_DIV_CLR 0xffffefff
TXP_CTRL_GO_BITS 0:0
MS_SEMA_26_RESET 0000000000
MPHI_HSINDDB_HANDLE_CLR 0xf00fffff
SPI_CS_INTD_BITS 9:9
CM_TD0CTL_SRC_MSB 3
A2W_PLLB_ANA_SSCS_MODE_SET 0x00010000
HDMI_RAM_PACKET_13_8_MASK 0xffffffff
MS_MBOX_2_MBOX_BITS 31:0
DMA6_CS_INT_CLR 0xfffffffb
USB_DOEPINT0_TXF_EMPTY_MSB 7
TB_JTB_CONFIG_TMS_RISE_BITS 8:8
A2W_XOSC_CTRL_DDREN_SET 0x00000010
CMTIMER 0x7C:RW
MPHI_INTSTAT_TXEND_SET 0x00010000
SMI_DSW2_WDREQ_CLR 0xffffff7f
DMA4_CS_DREQ_MSB 3
CM_PLLD_HOLDDSI1_SET 0x00000008
INTERRUPT_PLL ((64) + 45 )
APERF0_BW2_RTRANS_WIDTH 32
USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_RESET 0x0
PM_CAM1_LDOLPEN_CLR 0xfffffffd
CM_GNRICCTL_MASH_MSB 10
AVE_OUT_CTRL_SOFT_RESET_MSB 30
A2W_PLLB_SP2_BYPEN_CLR 0xfffffdff
DMA15_TI_NO_WIDE_BURSTS_LSB 26
CM_PLLTCNT1_CNT_LSB 0
TB_BOOT_OPT_NO_PRINT_BITS 6:6
GP_FSEL4_FSEL45_LSB 15
USB_GHWCFG4_EN_PWROPT_CLR 0xffffffef
A2W_PLLC_CTRLR 0x7e102920:RW
ARM_ERRHALT 0x7E00B000 +0x448:RW
DMA15_CS_RESET_MSB 31
SD_DMRCRC1_HIGH_LSB 16
MS_ICSET_0_ICSET_0_SET 0x00000001
CM_DSI1EDIV_DIV_BITS 15:4
L1_IC0_RD_HITS 0x7ee02040:RW
CGMSAE_REVID 0x7e80605c:RW
CM_PCMCTL_BUSY_CLR 0xffffff7f
ARM_C0_APROTMSK 0x0000F000
AVE_IN_MAX_TRANSFER_MAX_TRANSFER_LSB 0
DMA6_DEBUG_VERSION_LSB 25
DMA4_CS_DREQ_LSB 3
EMMC_INTERRUPT_CCRC_ERR_LSB 17
DMA14_TI_DEST_IGNORE_CLR 0xffffff7f
HDMI_RAM_PACKET_8_5_MASK 0xffffffff
TXP_CTRL_WIDTH 32
SLIM_DCC5_PA1_WIDTH 24
CCP2TX_TIC_RESET 0000000000
MPHI_C1INDDB_HANDLE_MSB 27
CM_GP0CTL 0x7e101070:RW
HDMI_RAM_PACKET_2_4_MASK 0xffffffff
EMMC_IRPT_MASK_BLOCK_GAP_MSB 2
HDMI_DETECTED_HORZA_MANUAL_VPOL_CLR 0xffffbfff
L1_D_PRIORITY_c1_l2_priority_CLR 0xfff0ffff
DMA15_CS_ACTIVE_CLR 0xfffffffe
FPGA_STATUS0_NAND_RNB_MSB 6
CM_PLLH_ANARST_MSB 8
A2W_PLLC_ANA0R_WIDTH 24
DMA7_DEBUG_DMA_STATE_BITS 24:16
TB_JTB_CONFIG_BITCNT_LSB 23
GP_FSEL4_FSEL48_MSB 26
CM_TD0CTL_FRAC_BITS 9:9
USB_HPTXSTS_HPTXQTOP_SET 0xff000000
USB_GUSBCFG_FS_INTF_MSB 5
IC0_MASK3_WIDTH 31
USB_HCCHAR2_WIDTH 32
MPHI_MINFS_RPTR_BITS 29:20
A2W_PLLH_RCAL_MASK 0x000003ff
SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_SET 0x0000000c
SMI_DC_REQW_LSB 0
PM_GNRIC_ISPOW_MSB 2
DMA4_TI_DEST_INC_MSB 4
PCM_MODE_A_FTXP_CLR 0xfeffffff
A2W_PLLB_DIG0R_RESET 0000000000
EMMC_IRPT_MASK_RETUNE_BITS 12:12
GRMCS 0x1A005C00 + 0x00:RW
CAM1_CAMDBG1_MASK 0xffffffff
I2CCLKT 0x7e205000 + 0x1C:RW
ASB_V3D_S_CTRL_FULL_BITS 3:3
MPHI_INTSTAT_OMFUFLW_RESET 0x0
SD_DQRCRC1_WIDTH 32
A2W_PLLC_CORE1_DIV_LSB 0
CCP2TX_TAC_CTATADJ_CLR 0x0fffffff
HD_SPARE 0x7e808024:RW
SD_SC_WL_SET 0x00000007
DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
DMA6_DEBUG_RESET 0000000000
EMMC_BUS_CTRL_IRQSEL_LSB 20
CM_PWMCTL_MASH_MSB 10
DMA5_CS_PANIC_PRIORITY_LSB 20
ASB_H264_M_CTRL_CLR_ACK_MSB 1
I2C_SPI_SLV_DR_TXFF_SET 0x00040000
HDMI_HBR_AUDIO_PACKET_HEADER_MASK 0x000fffff
A2W_SMPS_A_MODE_BSTPWMB_SET 0x00000001
USB_GRSTCTL_TXF_NUM_BITS 10:6
CM_TDCLKEN_USBDFT_SET 0x00000800
PM_SMPS 0x7e10006c:RW
CM_TD1CTL_KILL_CLR 0xffffffdf
A2W_PLLA_ANA_KAIP_KP_BITS 3:0
DMA5_STRIDE_S_STRIDE_MSB 15
DMA4_TI_DEST_DREQ_LSB 6
I2C1_DLEN 0x7e804008:RW
ARM_3_ALL_IRQS (0x7E00B000 +0xB00)+0xF8:RW
SD_DQLCRC4_RISE_SET 0xffff0000
CAM1_CAMICC_RESET 0000000000
HD_MAI_SMP_MASK 0xffffffff
DMA3_TI_TDMODE_MSB 1
CM_HSMDIV_DIV_SET 0x0000fff0
GROPCTRS0 0x1A005100 + 0x084:RW
GROPCTRS1 0x1A005100 + 0x08C:RW
GROPCTRS2 0x1A005100 + 0x094:RW
GROPCTRS3 0x1A005100 + 0x09C:RW
ARM_IRQ_ENBL3 0x7E00B000 +0x218:RW
GROPCTRS5 0x1A005100 + 0x0AC:RW
GROPCTRS6 0x1A005100 + 0x0B4:RW
GROPCTRS7 0x1A005100 + 0x0BC:RW
GROPCTRS8 0x1A005100 + 0x0C4:RW
GROPCTRS9 0x1A005100 + 0x0CC:RW
SD_DQLCRC3_RISE_RESET 0x0
DMA11_CS_END_CLR 0xfffffffd
SH_HSTS_REW_TIME_OUT_SET 0x00000080
PIXELVALVE1_VC_MASK 0x007fffff
EMMC_BUS_CTRL_BE_PWR_MSB 30
AVE_OUT_OFFSET 0x7e240008:RW
CM_PULSECTL_KILL_BITS 5:5
DSI1_HS_CLT1_RESET 0000000000
A2W_PLLC_MULTI 0x7e102f20:RW
DMA1_CS_ACTIVE_LSB 0
MPHI_C0INDS_WORDS_MSB 20
PCM_FIFO_A_WIDTH 32
USB_DOEPINT0_EP_DISBLD_SET 0x00000002
ARM_1_MAIL1_SND (0x7E00B000 +0x900)+0xB4:RW
ST_CHI_WIDTH 32
PM_AVS_RSTDR_ARM_P_MSB 4
CM_LOCK_LOCKH_CLR 0xffffffef
ASB_H264_S_CTRL_CLR_REQ_BITS 0:0
DMA6_TI_INTEN_CLR 0xfffffffe
SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_SET 0x0000ff00
CCP2TX_TS_TFP_CLR 0xffffffbf
CM_INTEN_GAINC_MSB 2
DMA5_CS_ERROR_SET 0x00000100
DMA6_DEBUG_DMA_STATE_SET 0x01ff0000
SMI_DSR3_RESET 0x0101000c
A2W_SMPS_CTLB0_MASK 0x00ffffff
CM_PLLTCNT2_CNT_MSB 23
USB_DOEPINT0_BACK2BACK_SETUP_BITS 6:6
USB_HPRT_RES_LSB 6
DMA11_TXFR_LEN_MASK 0x0000ffff
USB_DOEPCTL0_MPS_MSB 10
USB_DOEPINT0_WIDTH 32
A2W_PLLB_SP0_MASK 0x000003ff
USB_DIEPEMPMSK 0x7e980834:RW
A2W_PLLB_ANA1_RESET 0x001d0000
EMMC_IRPT_EN_INT_A_LSB 9
CM_DFTCTL_SRC_LSB 0
DMA15_TI_BURST_LENGTH_LSB 12
PWM_STA_FULL1_SET 0x00000001
USB_GOTGINT_SES_END_DET_SET 0x00000004
MPHI_RXAXICFG_WIDTH 17
SD_SECSRT0_WIDTH 32
AVE_IN_MAX_TRANSFER_MASK 0xffffffff
DMA4_DEBUG_DMA_STATE_BITS 24:16
USB_GUSBCFG_IND_PASS_THRU_LSB 24
A2W_PLLC_ANA_KAIP 0x7e102330:RW
HDMI_RAM_PACKET_CONFIG_MASK 0x00013fff
TXP_CTRL_GO_SET 0x00000001
PCM_CS_A_RXCLR_CLR 0xffffffef
I2C_SPI_SLV_CR_EN_MSB 0
USB_GUSBCFG_HNP_CAP_BITS 9:9
DMA_ENABLE_EN9_BITS 9:9
ST_C2_WIDTH 32
USB_GINTMSK_ISO_OUT_DROP_LSB 14
SLIM_CON2_RESET 0000000000
DMA13_TI_DEST_DREQ_BITS 6:6
I2C_SPI_SLV_ICR_TXIC_CLR 0xfffffffd
USB_GNPTXSTS_MASK 0x7fffffff
SD_DQRCRC6_RISE_SET 0xffff0000
CM_EVENT_OCDONE_LSB 21
MPHI_MOUTFS_UFLOW_RESET 0x0
USB_DOEPCTL13_MASK 0xffffffff
PM_GRAFX_ISPOW_SET 0x00000004
A2W_SMPS_C_CLK_USEOSC_SET 0x00000004
APERF0_BW0_CTRL_BUS_SET 0x0000001f
DMA1_TI_DEST_INC_CLR 0xffffffef
HDMI_DETECTED_VERTB1_MASK 0x003fff00
DMA4_CONBLK_AD_SCB_ADDR_LSB 5
HDMI_CEC_CNTRL_1_RESET 0x0000e7be
SD_PHYC_MDLL_TMODE_MSB 16
SMI_DA_ADDR_BITS 5:0
CM_EVENT_RESUS_MSB 22
FPGA_DCM_WR_DATA_ADDRESS_BITS 23:16
GP_FSEL1_FSEL18_CLR 0xf8ffffff
USB_DIEPCTL0_EO_FR_NUM_MSB 16
CM_SLIMCTL_KILL_BITS 5:5
HDMI_RAM_PACKET_4_8_MASK 0xffffffff
IC0_C_MASK 0x0000000f
A2W_PLLB_ANA_SSCS_STEP_BITS 15:0
FPGA_DCM_RD_DATA_MASK 0x0000ffff
DMA6_CONBLK_AD_SCB_ADDR_MSB 31
DMA3_CS_INT_CLR 0xfffffffb
A2W_PLLH_RCAL_DIV_SET 0x000000ff
A2W_PLLA_CCP2_CHENB_LSB 8
L1_L1_SANDBOX_START4_START_ADDR_SET 0x3fffffe0
DMA2_STRIDE_WIDTH 32
USB_GRSTCTL_AHB_IDLE_LSB 31
EMMC_IRPT_MASK_DTO_ERR_SET 0x00100000
ARM_I0_BANK1 0x00000100
A2W_PLLC_CORE2_DIV_MSB 7
A2W_HDMI_CTL3_WIDTH 24
TS_TSENSSTAT_INTERUPT_LSB 11
DMA9_TI_WAITS_CLR 0xfc1fffff
DMA14_CS_INT_MSB 2
USB_GOTGINT_HST_NEG_SUC_STS_CHG_BITS 9:9
PCM_INTSTC_A_TXERR_MSB 2
HDMI_HDCP_CTL_WIDTH 17
MS_SEMA_28_MASK 0x00000001
DMA8_CS_ACTIVE_LSB 0
SMI_DD_WIDTH 18
A2W_PLLD_DIG0R_WIDTH 24
SMI_CS_TXE_SET 0x40000000
PM_CAM0_LDOHPEN_CLR 0xfffffffb
DMA4_STRIDE_D_STRIDE_BITS 31:16
HDMI_RAM_PACKET_3_1 0x7e902470:RW
DMA1_CONBLK_AD_WIDTH 32
MPHI_C0INDDB_MENDINT_MSB 30
USB_DPTXFSIZ13_WIDTH 32
DMA4_SOURCE_AD_S_ADDR_LSB 0
APERF1_BW1_RPEND_MASK 0x000000ff
DMA8_CS_PAUSED_SET 0x00000010
A2W_PLLH_AUX_DIV_SET 0x000000ff
CM_EVENT_FLOSSA_SET 0x00004000
TB_TASK_TXTCLR 0x7e20b0f0:RW
SD_DQRCRC15_FALL_CLR 0xffff0000
L2_CONT_OFF_l2_flush_flush_limit_MSB 19
CM_TIMERCTL_BUSYD_SET 0x00000100
EMMC_INTERRUPT_INT_C_BITS 11:11
GP_FSEL1_FSEL12_BITS 8:6
CM_SMIDIV_DIV_SET 0x0000fff0
AVE_OUT_CR_COEFF_GREEN_COEFF_BITS 19:10
TB_BOOT_OPT_NO_PRINT_LSB 6
CM_HSMCTL_ENAB_BITS 4:4
SD_SECEND0_ADDR_LS_BITS 12:0
GP_PUD_PUD_BITS 1:0
USB_DTXFSTS10 0x7e980a58:RW
USB_DTXFSTS11 0x7e980a78:RW
USB_DTXFSTS12 0x7e980a98:RW
USB_DTXFSTS13 0x7e980ab8:RW
USB_DTXFSTS14 0x7e980ad8:RW
USB_DTXFSTS15 0x7e980af8:RW
TB_JTB_CONFIG_TMS_RISE_MSB 8
CM_TD1CTL_WIDTH 13
DMA3_STRIDE_S_STRIDE_SET 0x0000ffff
GP_FSEL0_FSEL04_BITS 14:12
HDMI_HORZB_MANUAL_HBP_CLR 0xc00fffff
HDMI_PACKET_FIFO_STATUS 0x7e902124:RW
USB_DIEPTSIZ0_SUP_CNT_RESET 0x0
MPHI_TXAXICFG_TXNPRIO_LSB 0
MS_IREQ_0_MASK 0xffffffff
DMA1_CS_PANIC_PRIORITY_BITS 23:20
PM_PROC_POWOK_CLR 0xfffffffd
PWM_RNG4_RESET 0x00000020
AVE_IN_STATUS_INTERLACED_CLR 0xfffffbff
SD_MRT_MASK 0x000001ff
SYSAC_DUMMY_STATUS_IDLE_BITS 0:0
CPG_Debug3_WIDTH 32
MS_SEMA_26_MASK_CLR 0xfffffffe
MPHI_OUTDDB_CHANNEL_BITS 28:28
AVE_IN_LINE_LENGTH_LINE_LENGTH_BITS 11:0
CAM1_CAMDBG0_WIDTH 32
SPI_CLK_CDIV_SET 0x0000ffff
A2W_PLLB_CTRL 0x7e1021e0:RW
FPGA_DCM_CTRL_REMOTE_RST_LSB 0
HDMI_RAM_PACKET_4_1 0x7e902494:RW
SYSAC_JPEG_PRIORITY_P_PRIORITY_LSB 4
CAM0_CAMIBWP_WIDTH 32
AVE_IN_STATUS_LINE_NUM_HIT_SET 0x00000010
EMMC_IRPT_EN_CMD_DONE_MSB 0
DSI1_INT_STAT_WIDTH 32
VEC_CPS1617_CPS1819_MASK 0xffffffff
IC0_FORCE1_CLR_MASK 0xffffffff
VPU_ARB_CTRL_UC_THRESHOLD_SET 0x00000030
TB_JTB_CONFIG_BITCNT_MSB 29
GROPCTR_FBC_CZ_EVICTIONS 0x31
APERF1_BW0_WTWAIT_MASK 0xffffffff
DMA_ENABLE_EN5_SET 0x00000020
MPHI_C0INDCF_ORUN_RESET 0x0
DMA6_TI_DEST_WIDTH_CLR 0xffffffdf
SMI_DSR3_RHOLD_BITS 21:16
HDMI_VERTA0_MANUAL_VSP0_CLR 0xfe0fffff
PM_DSI0_RESET 0000000000
DMA10_TI_WAITS_SET 0x03e00000
MPHI_C1INDDB_MENDINT_RESET 0x0
VPU_ARB_CTRL_UC_ALGORITHM_RESET 0x0
DMA7_DEBUG_READ_ERROR_MSB 2
DMA5_DEBUG_FIFO_ERROR_SET 0x00000002
SCALER_DISPECTRL_BUSY_STATUS_LSB 8
SLIM_MC_OUT_CON_MASK 0x00000048
CM_GNRICCTL_KILL_LSB 5
CM_PLLC_HOLDCORE0_MSB 1
IDCKSEL 0x10002018:RW
PM_RSTC_QRCFG_MSB 13
USB_HCSPLT0_SPLT_ENA_LSB 31
DMA12_TI_WAITS_BITS 25:21
PCM_TXC_A_RESET 0000000000
SMI_DSW3_WFORMAT_CLR 0xff7fffff
DMA5_DEBUG_DMA_STATE_MSB 24
ARM_1_MAIL1_STA (0x7E00B000 +0x900)+0xB8:RW
USB_DOEPTSIZ8_MASK 0xffffffff
DMA1_TI_WAITS_MSB 25
USB_DCTL_GMC_BITS 14:13
AVE_IN_CURRENT_ADDRESS 0x7e910018:RW
DMA2_TXFR_LEN_YLENGTH_BITS 29:16
HD_VID_CTL_ENABLE_MSB 31
A2W_PLLA_ANA_VCO_WIDTH 1
CCP2TX_TC_SWR_BITS 31:31
SH_HSTS_CRC7_ERROR_MSB 4
SD_DQLCRC0_RISE_RESET 0x0
SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_CLR 0xffffff3f
CM_LOCK_FLOCKA_SET 0x00000100
DMA5_CS_DISDEBUG_SET 0x20000000
DSI0_HS_CLT1 0x7e209048:RW
DSI0_CTRL_CTRL1_BITS 1:1
DMA4_TXFR_LEN_YLENGTH_CLR 0xc000ffff
PCM_TXC_A_CH2POS_BITS 13:4
EMMC_IRPT_MASK_BLOCK_GAP_BITS 2:2
CAM0_CAMMISC_RESET 0000000000
PCM_MODE_A_FSLEN_LSB 0
SH_CMD_BUSY_CMD_MSB 11
GP_LEV0_LEVn0_CLR 0x00000000
DMA0_STRIDE_S_STRIDE_CLR 0xffff0000
SD_SA_POWSAVE_RESET 0x0
USB_DCTL_RMT_WKUP_SIG_RESET 0x0
ASB_APB_ID 0x62726467
DMA12_DEST_AD_MASK 0xffffffff
MPHI_TXAXICFG_INTHRESH_RESET 0x0
HDMI_CP_CONFIG 0x7e902054:RW
SCALER_DISPCTRL_TILE_WID_LSB 16
CM_INTEN_LOSSB_BITS 6:6
USB_GRXSTSP_DEV_DPID_SET 0x00018000
CM_HSMCTL_FRAC_SET 0x00000200
SYSAC_V3D_LIMITER_INCREMENT_CLR 0xfffffffe
APERF0_BW1_CTRL_EN_CLR 0xbfffffff
PM_USB_CTRLEN_SET 0x00000001
EMMC_RESP3_MASK 0xffffffff
EMMC_STATUS_DAT_ACTIVE_SET 0x00000004
DMA5_DEBUG_VERSION_MSB 27
PM_RSTS_HADWRH_MSB 6
VEC_CPS1617_CPS1819 0x7e806130:RW
SYSAC_UC_ARBITER_CONTROL_LIMIT_LSB 0
PWM_CTL_POLA3_SET 0x00100000
CM_PLLC_LOADCORE1_SET 0x00000004
AVE_OUT_OFFSET_RED_OFFSET_SET 0x00ff0000
AVE_IN_OUTSTANDING_BUFF1_WIDTH 8
MPHI_HSINDDB_TENDINT_SET 0x20000000
MS_SEMA_1_MASK 0x00000001
USB_HFNUM_NUM_SET 0x0000ffff
CM_VECCTL 0x7e1010f8:RW
DMA10_TI_DEST_WIDTH_CLR 0xffffffdf
DMA6_CS_ABORT_LSB 30
EMMC_HWCAP0_V3_3_SET 0x01000000
MS_SEMA_28_WIDTH 1
SLIM_DCC0_CON_WIDTH 32
TXP_CTRL_BUSY_CLR 0xfffffffd
DMA9_CS_PANIC_PRIORITY_LSB 20
CM_INTEN_FGAINB_MSB 11
SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_MSB 1
EMMC_EXRDFIFO_CFG_RD_THRSH_LSB 0
DMA_TI_INT (1<<0)
SMI_DSW0_WFORMAT_SET 0x00800000
EMMC_STATUS_WRITE_TRANSFER_SET 0x00000100
PWMSTA_BERR 8
VEC_FCW_SECAM_B_MASK 0xffffffff
HDMI_READ_POINTERS_DRFT_EMPTY_MINUS_LSB 17
A2W_PLLC_CORE2_MASK 0x000003ff
DMA9_CS_RESET_MSB 31
I2C_SPI_SLV_DMACR_TXDMAE_BITS 1:1
SH_ARG_RESET 0000000000
I2C_SPI_SLV_DMACR_DMAONERR_LSB 2
USB_DIEPTSIZ9_WIDTH 32
APERF0_BW1_CTRL_EN_SET 0x40000000
DMA2_TI_DEST_IGNORE_SET 0x00000080
GP_AREN1_ARENn32_BITS 31:0
A2W_SMPS_C_CTL_UPEN_CLR 0xfffffffd
CAM0_CAMDBCTL 0x7e800300:RW
CCP2RPC0 CCP2_BASE_ADDRESS + 0x104:RW
CCP2RPC1 CCP2_BASE_ADDRESS + 0x204:RW
PWM_CTL_USEF1_BITS 5:5
CSI2_THSSET CSI2_BASE_ADDRESS + 0x18:RW
AUX_MU_IER_RXIRQEN 0x01
USB_HCINT0_CH_HLTD_SET 0x00000002
EMMC_CMDTM_CMD_RSPNS_TYPE_SET 0x00030000
SMI_DSR1_WIDTH 32
PCM_TXC_A 0x7e203010:RW
SPI_CS_DMAEN_LSB 8
PWM_STA_STA1_CLR 0xfffffdff
A2W_PLLB_ARM_CHENB_SET 0x00000100
ARM_C0_APROTSYST 0x0000F000
SCALER_DISPBASE0 0x7e40004c:RW
PM_GNRIC_POWUP_SET 0x00000001
MPHI_HSINDDB_WIDTH 30
MS_SEMA_14_RESET 0000000000
DMA12_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
CM_TECCTL_KILL_SET 0x00000020
USB_DIEPCTL0_SET_ODD_FR_BITS 29:29
DMA12_CS_ABORT_MSB 30
UART_LSR_RFE_SET 0x00000080
ASB_ISP_M_CTRL_WCOUNT_LSB 14
FPGA_DCM_WR_DATA_DATA_LSB 0
USB_DIEPCTL1_WIDTH 32
SMIDS_FORMAT 23
USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_MSB 15
SD_SB_COLBITS_MSB 1
EMMC_IRPT_EN_CARD_IN_BITS 6:6
SYSAC_UC_ARBITER_CONTROL_DELAY_SET 0x0000000c
DMA11_CS_INT_MSB 2
SMI_DSR3_RSTROBE_MSB 6
SMI_DSR3_MODE68_SET 0x00800000
USB_DPTXFSIZ11_MASK 0xffffffff
ASB_V3D_S_CTRL_CLR_ACK_SET 0x00000002
PM_GNRIC_WIDTH 23