--------------------------------------------------------------------------- SARUWATARI INSTRUCTION SET --------------------------------------------------------------------------- ########################################################################### ------------+----------------+------------+------------+------------------- I-TYPE (00) | OPCODE (6 bit) | RS (5 bit) | RD (5 bit) | IMM (16 bit) ------------+----------------+------------+------------+------------------- addi | 000001 | Reg(RD) = Reg(RS) + ext_sign(IMM) ------------+----------------+--------------------------------------------- subi | 000010 | Reg(RD) = Reg(RS) - ext_sign(IMM) ------------+----------------+--------------------------------------------- lw | 000011 | Reg(RD) = Mem(Reg(RS) + ext_sign(IMM)) ------------+----------------+--------------------------------------------- sw | 000100 | Mem(RS + ext_sign(IMM)) = Reg(RD) ------------+----------------+--------------------------------------------- beqz | 000101 | if (RS == 0) -> PC + 4 + IMM ** -----------+----------------+--------------------------------------------- bnqz | 000110 | if (RS != 0) -> PC + 4 + IMM ** ------------+----------------+--------------------------------------------- multi | 000111 | Reg(RD) = Reg(RS) * ext_sign(IMM) ------------+----------------+--------------------------------------------- ########################################################################### ------------+------------+------------+---------------------+-------------- R-TYPE (01) | RS1(5 bit) | RS2(5 bit) | RD (5 bit) | FUNC (11 bit) ------------+------------+------------+---------------------+-------------- add | Reg(RD) = Reg(RS1) + Reg(RS2) | 00000000001 ------------+-----------------------------------------------+-------------- sub | Reg(RD) = Reg(RS1) - Reg(RS2) | 00000000010 ------------+-----------------------------------------------+-------------- mult | Reg(RD) = Reg(RS1) * Reg(RS2) | 00000000011 ------------+-----------------------------------------------+-------------- slt | if (Reg(RS1) < Reg(RS2)) -> Reg(RD) = 1 else 0| 00000000100 ------------+-----------------------------------------------+-------------- sgt | if (Reg(RS1) > Reg(RS2)) -> Reg(RD) = 1 else 0| 00000000101 ------------+-----------------------------------------------+-------------- div | Reg(RD) = Reg(RS1) / Reg(RS2) | 00000000110 ------------+-------------------------------------------------------------- ########################################################################### ------------+----------------+--------------------------------------------- J-TYPE (10) | OPCODE (6 bit) | name(26 bit) ------------+----------------+--------------------------------------------- j | 100000 | PC = name ------------+----------------+--------------------------------------------- jal | 100001 | r31 = PC; PC = name; ------------+----------------+--------------------------------------------- ------------+----------------+--------------------------------------------- NOP | 000000 | ------------+----------------+--------------------------------------------- ** IMM, in questo caso, e` un offset (positivo o negativo) rispetto all'attuale program counter. INSTRUCTION SAMPLES: addi r1,r2,7 000001 00010 00001 0000000000000111 sw r4,20(r0) 000100 00000 00100 0000000000010100 beqz r0,20 000101 00000 00000 0000000000010100 div r1,r2,r3 010000 00010 00011 00001 00000000110 add r1,r2,r3 01000000010000110000100000000001 slt r10,r11,r12 01000001011011000101000000000101 mult r1,r2,r3 010000 00010 00011 00001 00000000011 mult r2,r2,r3 010000 00010 00011 00010 00000000011 addi r1,r2,7 000001 00010 00001 0000000000000111 multi r2,r1,7 000111 00011 00001 0000000000000111 -- test with nop 00000100001000010000000000001010 00000100010000100000000000000111 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 01000000001000100001100000000001 00000000000000000000000000000000