cpldfit: version P.40xd Xilinx Inc. Fitter Report Design Name: gzleddrvr Date: 1-11-2013, 11:23PM Device Used: XC9572XL-5-PC44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 52 /72 ( 72%) 157 /360 ( 44%) 70 /216 ( 32%) 51 /72 ( 71%) 25 /34 ( 74%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 13/18 20/54 28/90 9/ 9* FB2 6/18 26/54 24/90 6/ 9 FB3 15/18 8/54 45/90 4/ 9 FB4 18/18* 16/54 60/90 6/ 7 ----- ----- ----- ----- 52/72 70/216 157/360 25/34 * - Resource is exhausted ** Global Control Resources ** Signal 'clk' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 11 11 | I/O : 22 28 Output : 13 13 | GCK/IO : 3 3 Bidirectional : 0 0 | GTS/IO : 0 2 GCK : 1 1 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 25 25 ** Power Data ** There are 52 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'gzleddrvr.ise'. ************************* Summary of Mapped Logic ************************ ** 13 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State digit_enas<0> 1 1 FB1_2 1~ I/O O STD FAST SET digit_enas<1> 1 1 FB1_5 2~ I/O O STD FAST RESET digit_enas<2> 1 1 FB1_6 3~ I/O O STD FAST RESET digit_enas<3> 1 1 FB1_8 4~ I/O O STD FAST RESET segments<0> 4 6 FB1_15 8~ I/O O STD FAST RESET segments<1> 4 6 FB1_17 9~ I/O O STD FAST RESET segments<2> 4 6 FB2_2 35~ I/O O STD FAST RESET segments<3> 4 6 FB2_5 36~ I/O O STD FAST RESET segments<4> 4 6 FB2_6 37~ I/O O STD FAST RESET segments<5> 4 6 FB2_8 38~ I/O O STD FAST RESET segments<6> 4 6 FB2_15 43~ I/O O STD FAST RESET segments<7> 4 6 FB2_17 44~ I/O O STD FAST RESET miso 9 12 FB4_17 34 I/O O STD FAST ** 39 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State cur_digit<1> 1 1 FB1_10 STD RESET cur_digit<0> 0 0 FB1_11 STD RESET bit_cnt<0> 2 2 FB1_12 STD SET digit_cnt<0> 3 5 FB1_13 STD RESET bit_cnt<2> 3 4 FB1_14 STD SET bit_cnt<1> 3 3 FB1_16 STD SET digit_cnt<1> 4 6 FB1_18 STD RESET display<3><7> 3 8 FB3_4 STD RESET display<3><6> 3 8 FB3_5 STD RESET display<3><5> 3 8 FB3_6 STD RESET display<3><4> 3 8 FB3_7 STD RESET display<3><3> 3 8 FB3_8 STD RESET display<3><2> 3 8 FB3_9 STD RESET display<3><1> 3 8 FB3_10 STD RESET display<3><0> 3 8 FB3_11 STD RESET display<2><7> 3 8 FB3_12 STD RESET display<2><6> 3 8 FB3_13 STD RESET display<2><5> 3 8 FB3_14 STD RESET display<2><4> 3 8 FB3_15 STD RESET display<2><3> 3 8 FB3_16 STD RESET display<2><2> 3 8 FB3_17 STD RESET display<2><1> 3 8 FB3_18 STD RESET display<2><0> 3 8 FB4_1 STD RESET display<1><7> 3 8 FB4_2 STD RESET display<1><6> 3 8 FB4_3 STD RESET display<1><5> 3 8 FB4_4 STD RESET display<1><4> 3 8 FB4_5 STD RESET display<1><3> 3 8 FB4_6 STD RESET display<1><2> 3 8 FB4_7 STD RESET display<1><1> 3 8 FB4_8 STD RESET display<1><0> 3 8 FB4_9 STD RESET display<0><7> 3 8 FB4_10 STD RESET display<0><6> 3 8 FB4_11 STD RESET display<0><5> 3 8 FB4_12 STD RESET display<0><4> 3 8 FB4_13 STD RESET display<0><3> 3 8 FB4_14 STD RESET display<0><2> 3 8 FB4_15 STD RESET display<0><1> 3 8 FB4_16 STD RESET display<0><0> 3 8 FB4_18 STD RESET ** 12 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use clk FB1_9 5~ GCK/I/O GCK inputs<6> FB1_11 6~ GCK/I/O I inputs<7> FB1_14 7~ GCK/I/O I inputs<0> FB3_14 19~ I/O I inputs<1> FB3_15 20~ I/O I inputs<2> FB3_16 24~ I/O I inputs<3> FB3_17 22~ I/O I inputs<4> FB4_2 25~ I/O I inputs<5> FB4_5 26~ I/O I sclk FB4_11 28 I/O I mosi FB4_14 29 I/O I sel FB4_15 33 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 20/34 Number of signals used by logic mapping into function block: 20 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) digit_enas<0> 1 0 0 4 FB1_2 1~ I/O O (unused) 0 0 0 5 FB1_3 (b) (unused) 0 0 0 5 FB1_4 (b) digit_enas<1> 1 0 0 4 FB1_5 2~ I/O O digit_enas<2> 1 0 0 4 FB1_6 3~ I/O O (unused) 0 0 0 5 FB1_7 (b) digit_enas<3> 1 0 0 4 FB1_8 4~ I/O O (unused) 0 0 0 5 FB1_9 5 GCK/I/O GCK cur_digit<1> 1 0 0 4 FB1_10 (b) (b) cur_digit<0> 0 0 0 5 FB1_11 6 GCK/I/O I bit_cnt<0> 2 0 0 3 FB1_12 (b) (b) digit_cnt<0> 3 0 0 2 FB1_13 (b) (b) bit_cnt<2> 3 0 0 2 FB1_14 7 GCK/I/O I segments<0> 4 0 0 1 FB1_15 8~ I/O O bit_cnt<1> 3 0 0 2 FB1_16 (b) (b) segments<1> 4 0 0 1 FB1_17 9~ I/O O digit_cnt<1> 4 0 0 1 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: bit_cnt<0> 8: digit_enas<1> 15: display<2><0> 2: bit_cnt<1> 9: digit_enas<2> 16: display<2><1> 3: bit_cnt<2> 10: digit_enas<3> 17: display<3><0> 4: cur_digit<0> 11: display<0><0> 18: display<3><1> 5: cur_digit<1> 12: display<0><1> 19: sclk 6: digit_cnt<0> 13: display<1><0> 20: sel 7: digit_enas<0> 14: display<1><1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs digit_enas<0> .........X.............................. 1 digit_enas<1> ......X................................. 1 digit_enas<2> .......X................................ 1 digit_enas<3> ........X............................... 1 cur_digit<1> ...X.................................... 1 cur_digit<0> ........................................ 0 bit_cnt<0> ..................XX.................... 2 digit_cnt<0> XXX...............XX.................... 5 bit_cnt<2> XX................XX.................... 4 segments<0> ...XX.....X.X.X.X....................... 6 bit_cnt<1> X.................XX.................... 3 segments<1> ...XX......X.X.X.X...................... 6 digit_cnt<1> XXX..X............XX.................... 6 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 26/28 Number of signals used by logic mapping into function block: 26 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) segments<2> 4 0 0 1 FB2_2 35~ I/O O (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 0 5 FB2_4 (b) segments<3> 4 0 0 1 FB2_5 36~ I/O O segments<4> 4 0 0 1 FB2_6 37~ I/O O (unused) 0 0 0 5 FB2_7 (b) segments<5> 4 0 0 1 FB2_8 38~ I/O O (unused) 0 0 0 5 FB2_9 39 GSR/I/O (unused) 0 0 0 5 FB2_10 (b) (unused) 0 0 0 5 FB2_11 40 GTS/I/O (unused) 0 0 0 5 FB2_12 (b) (unused) 0 0 0 5 FB2_13 (b) (unused) 0 0 0 5 FB2_14 42 GTS/I/O segments<6> 4 0 0 1 FB2_15 43~ I/O O (unused) 0 0 0 5 FB2_16 (b) segments<7> 4 0 0 1 FB2_17 44~ I/O O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: cur_digit<0> 10: display<1><3> 19: display<2><6> 2: cur_digit<1> 11: display<1><4> 20: display<2><7> 3: display<0><2> 12: display<1><5> 21: display<3><2> 4: display<0><3> 13: display<1><6> 22: display<3><3> 5: display<0><4> 14: display<1><7> 23: display<3><4> 6: display<0><5> 15: display<2><2> 24: display<3><5> 7: display<0><6> 16: display<2><3> 25: display<3><6> 8: display<0><7> 17: display<2><4> 26: display<3><7> 9: display<1><2> 18: display<2><5> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs segments<2> XXX.....X.....X.....X................... 6 segments<3> XX.X.....X.....X.....X.................. 6 segments<4> XX..X.....X.....X.....X................. 6 segments<5> XX...X.....X.....X.....X................ 6 segments<6> XX....X.....X.....X.....X............... 6 segments<7> XX.....X.....X.....X.....X.............. 6 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 8/46 Number of signals used by logic mapping into function block: 8 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 11 I/O (unused) 0 0 0 5 FB3_3 (b) display<3><7> 3 0 0 2 FB3_4 (b) (b) display<3><6> 3 0 0 2 FB3_5 12 I/O (b) display<3><5> 3 0 0 2 FB3_6 (b) (b) display<3><4> 3 0 0 2 FB3_7 (b) (b) display<3><3> 3 0 0 2 FB3_8 13 I/O (b) display<3><2> 3 0 0 2 FB3_9 14 I/O (b) display<3><1> 3 0 0 2 FB3_10 (b) (b) display<3><0> 3 0 0 2 FB3_11 18 I/O (b) display<2><7> 3 0 0 2 FB3_12 (b) (b) display<2><6> 3 0 0 2 FB3_13 (b) (b) display<2><5> 3 0 0 2 FB3_14 19 I/O I display<2><4> 3 0 0 2 FB3_15 20 I/O I display<2><3> 3 0 0 2 FB3_16 24 I/O I display<2><2> 3 0 0 2 FB3_17 22 I/O I display<2><1> 3 0 0 2 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: bit_cnt<0> 4: digit_cnt<0> 7: sclk 2: bit_cnt<1> 5: digit_cnt<1> 8: sel 3: bit_cnt<2> 6: mosi Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs display<3><7> XXXXXXXX................................ 8 display<3><6> XXXXXXXX................................ 8 display<3><5> XXXXXXXX................................ 8 display<3><4> XXXXXXXX................................ 8 display<3><3> XXXXXXXX................................ 8 display<3><2> XXXXXXXX................................ 8 display<3><1> XXXXXXXX................................ 8 display<3><0> XXXXXXXX................................ 8 display<2><7> XXXXXXXX................................ 8 display<2><6> XXXXXXXX................................ 8 display<2><5> XXXXXXXX................................ 8 display<2><4> XXXXXXXX................................ 8 display<2><3> XXXXXXXX................................ 8 display<2><2> XXXXXXXX................................ 8 display<2><1> XXXXXXXX................................ 8 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 16/38 Number of signals used by logic mapping into function block: 16 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use display<2><0> 3 0 0 2 FB4_1 (b) (b) display<1><7> 3 0 0 2 FB4_2 25 I/O I display<1><6> 3 0 0 2 FB4_3 (b) (b) display<1><5> 3 0 0 2 FB4_4 (b) (b) display<1><4> 3 0 0 2 FB4_5 26 I/O I display<1><3> 3 0 0 2 FB4_6 (b) (b) display<1><2> 3 0 0 2 FB4_7 (b) (b) display<1><1> 3 0 0 2 FB4_8 27 I/O (b) display<1><0> 3 0 0 2 FB4_9 (b) (b) display<0><7> 3 0 0 2 FB4_10 (b) (b) display<0><6> 3 0 0 2 FB4_11 28 I/O I display<0><5> 3 0 0 2 FB4_12 (b) (b) display<0><4> 3 0 0 2 FB4_13 (b) (b) display<0><3> 3 0 0 2 FB4_14 29 I/O I display<0><2> 3 0 0 2 FB4_15 33 I/O I display<0><1> 3 0 \/2 0 FB4_16 (b) (b) miso 9 4<- 0 0 FB4_17 34 I/O O display<0><0> 3 0 /\2 0 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: bit_cnt<0> 7: inputs<1> 12: inputs<6> 2: bit_cnt<1> 8: inputs<2> 13: inputs<7> 3: bit_cnt<2> 9: inputs<3> 14: mosi 4: digit_cnt<0> 10: inputs<4> 15: sclk 5: digit_cnt<1> 11: inputs<5> 16: sel 6: inputs<0> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs display<2><0> XXXXX........XXX........................ 8 display<1><7> XXXXX........XXX........................ 8 display<1><6> XXXXX........XXX........................ 8 display<1><5> XXXXX........XXX........................ 8 display<1><4> XXXXX........XXX........................ 8 display<1><3> XXXXX........XXX........................ 8 display<1><2> XXXXX........XXX........................ 8 display<1><1> XXXXX........XXX........................ 8 display<1><0> XXXXX........XXX........................ 8 display<0><7> XXXXX........XXX........................ 8 display<0><6> XXXXX........XXX........................ 8 display<0><5> XXXXX........XXX........................ 8 display<0><4> XXXXX........XXX........................ 8 display<0><3> XXXXX........XXX........................ 8 display<0><2> XXXXX........XXX........................ 8 display<0><1> XXXXX........XXX........................ 8 miso XXX..XXXXXXXX..X........................ 12 display<0><0> XXXXX........XXX........................ 8 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FTCPE_bit_cnt0: FTCPE port map (bit_cnt(0),'1',NOT sclk,'0',sel); FTCPE_bit_cnt1: FTCPE port map (bit_cnt(1),bit_cnt(0),NOT sclk,'0',sel); FTCPE_bit_cnt2: FTCPE port map (bit_cnt(2),bit_cnt_T(2),NOT sclk,'0',sel); bit_cnt_T(2) <= (NOT bit_cnt(1) AND NOT bit_cnt(0)); FTCPE_cur_digit0: FTCPE port map (cur_digit(0),'1',clk,'0','0'); FTCPE_cur_digit1: FTCPE port map (cur_digit(1),cur_digit(0),clk,'0','0'); FTCPE_digit_cnt0: FTCPE port map (digit_cnt(0),'1',NOT sclk,sel,'0',digit_cnt_CE(0)); digit_cnt_CE(0) <= (NOT bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0)); FTCPE_digit_cnt1: FTCPE port map (digit_cnt(1),digit_cnt(0),NOT sclk,sel,'0',digit_cnt_CE(1)); digit_cnt_CE(1) <= (NOT bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0)); FDCPE_digit_enas0: FDCPE port map (digit_enas(0),digit_enas(3),clk,'0','0'); FDCPE_digit_enas1: FDCPE port map (digit_enas(1),digit_enas(0),clk,'0','0'); FDCPE_digit_enas2: FDCPE port map (digit_enas(2),digit_enas(1),clk,'0','0'); FDCPE_digit_enas3: FDCPE port map (digit_enas(3),digit_enas(2),clk,'0','0'); FDCPE_display05: FDCPE port map (display(0)(5),mosi,sclk,'0','0',display_CE(0)(5)); display_CE(0)(5) <= (NOT sel AND NOT digit_cnt(0) AND NOT digit_cnt(1) AND bit_cnt(2) AND NOT bit_cnt(1) AND bit_cnt(0)); FDCPE_display04: FDCPE port map (display(0)(4),mosi,sclk,'0','0',display_CE(0)(4)); display_CE(0)(4) <= (NOT sel AND NOT digit_cnt(0) AND NOT digit_cnt(1) AND bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0)); FDCPE_display07: FDCPE port map (display(0)(7),mosi,sclk,'0','0',display_CE(0)(7)); display_CE(0)(7) <= (NOT sel AND NOT digit_cnt(0) AND NOT digit_cnt(1) AND bit_cnt(2) AND bit_cnt(1) AND bit_cnt(0)); FDCPE_display03: FDCPE port map (display(0)(3),mosi,sclk,'0','0',display_CE(0)(3)); display_CE(0)(3) <= (NOT sel AND NOT digit_cnt(0) AND NOT digit_cnt(1) AND NOT bit_cnt(2) AND bit_cnt(1) AND bit_cnt(0)); FDCPE_display06: FDCPE port map (display(0)(6),mosi,sclk,'0','0',display_CE(0)(6)); display_CE(0)(6) <= (NOT sel AND NOT digit_cnt(0) AND NOT digit_cnt(1) AND bit_cnt(2) AND bit_cnt(1) AND NOT bit_cnt(0)); FDCPE_display02: FDCPE port map (display(0)(2),mosi,sclk,'0','0',display_CE(0)(2)); display_CE(0)(2) <= (NOT sel AND NOT digit_cnt(0) AND NOT digit_cnt(1) AND NOT bit_cnt(2) AND bit_cnt(1) AND NOT bit_cnt(0)); FDCPE_display01: FDCPE port map (display(0)(1),mosi,sclk,'0','0',display_CE(0)(1)); display_CE(0)(1) <= (NOT sel AND NOT digit_cnt(0) AND NOT digit_cnt(1) AND NOT bit_cnt(2) AND NOT bit_cnt(1) AND bit_cnt(0)); FDCPE_display00: FDCPE port map (display(0)(0),mosi,sclk,'0','0',display_CE(0)(0)); display_CE(0)(0) <= (NOT sel AND NOT digit_cnt(0) AND NOT digit_cnt(1) AND NOT bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0)); FDCPE_display15: FDCPE port map (display(1)(5),mosi,sclk,'0','0',display_CE(1)(5)); display_CE(1)(5) <= (NOT sel AND digit_cnt(0) AND NOT digit_cnt(1) AND bit_cnt(2) AND NOT bit_cnt(1) AND bit_cnt(0)); FDCPE_display16: FDCPE port map (display(1)(6),mosi,sclk,'0','0',display_CE(1)(6)); display_CE(1)(6) <= (NOT sel AND digit_cnt(0) AND NOT digit_cnt(1) AND bit_cnt(2) AND bit_cnt(1) AND NOT bit_cnt(0)); FDCPE_display11: FDCPE port map (display(1)(1),mosi,sclk,'0','0',display_CE(1)(1)); display_CE(1)(1) <= (NOT sel AND digit_cnt(0) AND NOT digit_cnt(1) AND NOT bit_cnt(2) AND NOT bit_cnt(1) AND bit_cnt(0)); FDCPE_display10: FDCPE port map (display(1)(0),mosi,sclk,'0','0',display_CE(1)(0)); display_CE(1)(0) <= (NOT sel AND digit_cnt(0) AND NOT digit_cnt(1) AND NOT bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0)); FDCPE_display12: FDCPE port map (display(1)(2),mosi,sclk,'0','0',display_CE(1)(2)); display_CE(1)(2) <= (NOT sel AND digit_cnt(0) AND NOT digit_cnt(1) AND NOT bit_cnt(2) AND bit_cnt(1) AND NOT bit_cnt(0)); FDCPE_display14: FDCPE port map (display(1)(4),mosi,sclk,'0','0',display_CE(1)(4)); display_CE(1)(4) <= (NOT sel AND digit_cnt(0) AND NOT digit_cnt(1) AND bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0)); FDCPE_display17: FDCPE port map (display(1)(7),mosi,sclk,'0','0',display_CE(1)(7)); display_CE(1)(7) <= (NOT sel AND digit_cnt(0) AND NOT digit_cnt(1) AND bit_cnt(2) AND bit_cnt(1) AND bit_cnt(0)); FDCPE_display13: FDCPE port map (display(1)(3),mosi,sclk,'0','0',display_CE(1)(3)); display_CE(1)(3) <= (NOT sel AND digit_cnt(0) AND NOT digit_cnt(1) AND NOT bit_cnt(2) AND bit_cnt(1) AND bit_cnt(0)); FDCPE_display22: FDCPE port map (display(2)(2),mosi,sclk,'0','0',display_CE(2)(2)); display_CE(2)(2) <= (NOT sel AND NOT digit_cnt(0) AND digit_cnt(1) AND NOT bit_cnt(2) AND bit_cnt(1) AND NOT bit_cnt(0)); FDCPE_display25: FDCPE port map (display(2)(5),mosi,sclk,'0','0',display_CE(2)(5)); display_CE(2)(5) <= (NOT sel AND NOT digit_cnt(0) AND digit_cnt(1) AND bit_cnt(2) AND NOT bit_cnt(1) AND bit_cnt(0)); FDCPE_display26: FDCPE port map (display(2)(6),mosi,sclk,'0','0',display_CE(2)(6)); display_CE(2)(6) <= (NOT sel AND NOT digit_cnt(0) AND digit_cnt(1) AND bit_cnt(2) AND bit_cnt(1) AND NOT bit_cnt(0)); FDCPE_display27: FDCPE port map (display(2)(7),mosi,sclk,'0','0',display_CE(2)(7)); display_CE(2)(7) <= (NOT sel AND NOT digit_cnt(0) AND digit_cnt(1) AND bit_cnt(2) AND bit_cnt(1) AND bit_cnt(0)); FDCPE_display21: FDCPE port map (display(2)(1),mosi,sclk,'0','0',display_CE(2)(1)); display_CE(2)(1) <= (NOT sel AND NOT digit_cnt(0) AND digit_cnt(1) AND NOT bit_cnt(2) AND NOT bit_cnt(1) AND bit_cnt(0)); FDCPE_display20: FDCPE port map (display(2)(0),mosi,sclk,'0','0',display_CE(2)(0)); display_CE(2)(0) <= (NOT sel AND NOT digit_cnt(0) AND digit_cnt(1) AND NOT bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0)); FDCPE_display23: FDCPE port map (display(2)(3),mosi,sclk,'0','0',display_CE(2)(3)); display_CE(2)(3) <= (NOT sel AND NOT digit_cnt(0) AND digit_cnt(1) AND NOT bit_cnt(2) AND bit_cnt(1) AND bit_cnt(0)); FDCPE_display24: FDCPE port map (display(2)(4),mosi,sclk,'0','0',display_CE(2)(4)); display_CE(2)(4) <= (NOT sel AND NOT digit_cnt(0) AND digit_cnt(1) AND bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0)); FDCPE_display35: FDCPE port map (display(3)(5),mosi,sclk,'0','0',display_CE(3)(5)); display_CE(3)(5) <= (NOT sel AND digit_cnt(0) AND digit_cnt(1) AND bit_cnt(2) AND NOT bit_cnt(1) AND bit_cnt(0)); FDCPE_display36: FDCPE port map (display(3)(6),mosi,sclk,'0','0',display_CE(3)(6)); display_CE(3)(6) <= (NOT sel AND digit_cnt(0) AND digit_cnt(1) AND bit_cnt(2) AND bit_cnt(1) AND NOT bit_cnt(0)); FDCPE_display37: FDCPE port map (display(3)(7),mosi,sclk,'0','0',display_CE(3)(7)); display_CE(3)(7) <= (NOT sel AND digit_cnt(0) AND digit_cnt(1) AND bit_cnt(2) AND bit_cnt(1) AND bit_cnt(0)); FDCPE_display34: FDCPE port map (display(3)(4),mosi,sclk,'0','0',display_CE(3)(4)); display_CE(3)(4) <= (NOT sel AND digit_cnt(0) AND digit_cnt(1) AND bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0)); FDCPE_display33: FDCPE port map (display(3)(3),mosi,sclk,'0','0',display_CE(3)(3)); display_CE(3)(3) <= (NOT sel AND digit_cnt(0) AND digit_cnt(1) AND NOT bit_cnt(2) AND bit_cnt(1) AND bit_cnt(0)); FDCPE_display32: FDCPE port map (display(3)(2),mosi,sclk,'0','0',display_CE(3)(2)); display_CE(3)(2) <= (NOT sel AND digit_cnt(0) AND digit_cnt(1) AND NOT bit_cnt(2) AND bit_cnt(1) AND NOT bit_cnt(0)); FDCPE_display31: FDCPE port map (display(3)(1),mosi,sclk,'0','0',display_CE(3)(1)); display_CE(3)(1) <= (NOT sel AND digit_cnt(0) AND digit_cnt(1) AND NOT bit_cnt(2) AND NOT bit_cnt(1) AND bit_cnt(0)); FDCPE_display30: FDCPE port map (display(3)(0),mosi,sclk,'0','0',display_CE(3)(0)); display_CE(3)(0) <= (NOT sel AND digit_cnt(0) AND digit_cnt(1) AND NOT bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0)); miso_I <= ((bit_cnt(2) AND bit_cnt(1) AND NOT bit_cnt(0) AND inputs(6)) OR (NOT bit_cnt(2) AND bit_cnt(1) AND NOT bit_cnt(0) AND inputs(2)) OR (bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0) AND inputs(4)) OR (NOT bit_cnt(2) AND NOT bit_cnt(1) AND NOT bit_cnt(0) AND inputs(0)) OR (bit_cnt(2) AND bit_cnt(1) AND bit_cnt(0) AND inputs(7)) OR (bit_cnt(2) AND NOT bit_cnt(1) AND bit_cnt(0) AND inputs(5)) OR (NOT bit_cnt(2) AND bit_cnt(1) AND bit_cnt(0) AND inputs(3)) OR (NOT bit_cnt(2) AND NOT bit_cnt(1) AND bit_cnt(0) AND inputs(1))); miso <= miso_I when miso_OE = '1' else 'Z'; miso_OE <= NOT sel; FDCPE_segments0: FDCPE port map (segments(0),segments_D(0),clk,'0','0'); segments_D(0) <= ((display(0)(0) AND cur_digit(0) AND cur_digit(1)) OR (display(1)(0) AND NOT cur_digit(0) AND NOT cur_digit(1)) OR (display(2)(0) AND cur_digit(0) AND NOT cur_digit(1)) OR (display(3)(0) AND NOT cur_digit(0) AND cur_digit(1))); FDCPE_segments1: FDCPE port map (segments(1),segments_D(1),clk,'0','0'); segments_D(1) <= ((display(0)(1) AND cur_digit(0) AND cur_digit(1)) OR (display(1)(1) AND NOT cur_digit(0) AND NOT cur_digit(1)) OR (display(2)(1) AND cur_digit(0) AND NOT cur_digit(1)) OR (display(3)(1) AND NOT cur_digit(0) AND cur_digit(1))); FDCPE_segments2: FDCPE port map (segments(2),segments_D(2),clk,'0','0'); segments_D(2) <= ((display(0)(2) AND cur_digit(0) AND cur_digit(1)) OR (display(1)(2) AND NOT cur_digit(0) AND NOT cur_digit(1)) OR (display(2)(2) AND cur_digit(0) AND NOT cur_digit(1)) OR (display(3)(2) AND NOT cur_digit(0) AND cur_digit(1))); FDCPE_segments3: FDCPE port map (segments(3),segments_D(3),clk,'0','0'); segments_D(3) <= ((display(0)(3) AND cur_digit(0) AND cur_digit(1)) OR (display(1)(3) AND NOT cur_digit(0) AND NOT cur_digit(1)) OR (display(2)(3) AND cur_digit(0) AND NOT cur_digit(1)) OR (display(3)(3) AND NOT cur_digit(0) AND cur_digit(1))); FDCPE_segments4: FDCPE port map (segments(4),segments_D(4),clk,'0','0'); segments_D(4) <= ((display(0)(4) AND cur_digit(0) AND cur_digit(1)) OR (display(1)(4) AND NOT cur_digit(0) AND NOT cur_digit(1)) OR (display(2)(4) AND cur_digit(0) AND NOT cur_digit(1)) OR (display(3)(4) AND NOT cur_digit(0) AND cur_digit(1))); FDCPE_segments5: FDCPE port map (segments(5),segments_D(5),clk,'0','0'); segments_D(5) <= ((display(0)(5) AND cur_digit(0) AND cur_digit(1)) OR (display(1)(5) AND NOT cur_digit(0) AND NOT cur_digit(1)) OR (display(2)(5) AND cur_digit(0) AND NOT cur_digit(1)) OR (display(3)(5) AND NOT cur_digit(0) AND cur_digit(1))); FDCPE_segments6: FDCPE port map (segments(6),segments_D(6),clk,'0','0'); segments_D(6) <= ((display(0)(6) AND cur_digit(0) AND cur_digit(1)) OR (display(1)(6) AND NOT cur_digit(0) AND NOT cur_digit(1)) OR (display(2)(6) AND cur_digit(0) AND NOT cur_digit(1)) OR (display(3)(6) AND NOT cur_digit(0) AND cur_digit(1))); FDCPE_segments7: FDCPE port map (segments(7),segments_D(7),clk,'0','0'); segments_D(7) <= ((display(0)(7) AND cur_digit(0) AND cur_digit(1)) OR (display(1)(7) AND NOT cur_digit(0) AND NOT cur_digit(1)) OR (display(2)(7) AND cur_digit(0) AND NOT cur_digit(1)) OR (display(3)(7) AND NOT cur_digit(0) AND cur_digit(1))); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9572XL-5-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC9572XL-5-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 digit_enas<0> 23 GND 2 digit_enas<1> 24 inputs<2> 3 digit_enas<2> 25 inputs<4> 4 digit_enas<3> 26 inputs<5> 5 clk 27 KPR 6 inputs<6> 28 sclk 7 inputs<7> 29 mosi 8 segments<0> 30 TDO 9 segments<1> 31 GND 10 GND 32 VCC 11 KPR 33 sel 12 KPR 34 miso 13 KPR 35 segments<2> 14 KPR 36 segments<3> 15 TDI 37 segments<4> 16 TMS 38 segments<5> 17 TCK 39 KPR 18 KPR 40 KPR 19 inputs<0> 41 VCC 20 inputs<1> 42 KPR 21 VCC 43 segments<6> 22 inputs<3> 44 segments<7> Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572xl-5-PC44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : OFF Global Ouput Enable Optimization : OFF Input Limit : 54 Pterm Limit : 25